CN102820302B - Storage chip, the embedded device of encapsulation - Google Patents

Storage chip, the embedded device of encapsulation Download PDF

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Publication number
CN102820302B
CN102820302B CN201110154392.3A CN201110154392A CN102820302B CN 102820302 B CN102820302 B CN 102820302B CN 201110154392 A CN201110154392 A CN 201110154392A CN 102820302 B CN102820302 B CN 102820302B
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input
flash
spi
pin
chip
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CN201110154392.3A
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CN102820302A (en
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龙钢
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北京兆易创新科技股份有限公司
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Abstract

The present invention relates to a kind of storage chip of encapsulation and the embedded device of this storage chip of application.Above-mentioned storage chip comprises: the SPI NOR FLASH of encapsulation and parallel PSRAM; SPI NOR FLASH comprises clock input pin CLK1 and four input and output pin; Parallel PSRAM comprise clock input pin CLK2, more than four address input and data input and output pin; Wherein, four input and output pins of SPI NOR FLASH input with any four addresses of parallel PSRAM and are connected respectively with data input and output pin, and CLK1 and CLK2 is connected.Utilize technical scheme of the present invention, the area of the storage chip be packaged into can be reduced.

Description

Storage chip, the embedded device of encapsulation

Technical field

The present invention relates to chip encapsulation technology field, particularly relate to a kind of storage chip of encapsulation and apply the embedded device of this storage chip.

Background technology

Along with various portable information apparatus is to the diversification day by day of internal memory property requirements, in order to the problem that the integrated level and function that solve one chip are perfect not, occurring can by multi-chip package (the Multi Chip Package of several chip package at a place, MCP) technology, its advantage is the chip package of two to three kinds of different qualities to be formed a chip together, so just can reduce the space shared by chip, improve integrated level and the perfect in shape and function of chip.The integrated circuit suppliers of the global heavyweights such as Samsung, hyundai electronics, Intel has an optimistic view of these kind of internal memory market prospects in the recent period one after another, competitively releases Related product.

MCP technology is mainly used in memory at present, to meet the electronic installations such as mobile phone, computer, MP3, LCD TV, DVD to the complex characteristics demand of memory.

Parallel non-volatile flash memory (Parallel NOR FLASH) and parallel false static random access memory (PSRAM) are mainly packaged together formation storage chip by existing MCP technology.In this storage chip, data wire (or claiming data pins) and the address wire (or claiming address pins) of Parallel NOR FLASH and parallel PSRAM all want multiplexing ability normally to work, for the Parallel NOR FLASH of 64M bit, it has 16 data lines and 21 address wires, address wire multiplexing in the storage chip thus encapsulated and data wire add up to 37.And utilize MCP technology when carrying out chip package, converge on a ball by the mode of routing by two lines (or claiming pin) multiplexing in two chips, then above-mentioned at least have 37 balls by the storage chip that the Parallel NOR FLASH of 64M bit and parallel PSRAM encapsulates.Visible, utilize Parallel NOR FLASH and parallel PSRAM to carry out chip package, the quantity of ball is more, and routing difficulty is comparatively large, and this also causes the area of the storage chip of encapsulation can not be too little.In addition, the walk abreast area of PSRAM of area ratio due to Parallel NOR FLASH is much bigger, and the area of this storage chip decides primarily of Parallel NOR FLASH, and due to the Area comparison of Parallel NOR FLASH large, therefore, the Area comparison of the storage chip be packaged into is large.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of storage chip of encapsulation and applies the embedded device of this storage chip, can reduce the area of the storage chip encapsulated.

The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of storage chip of encapsulation, and this chip comprises: the serial non-volatile flash memory SPI NOR FLASH of encapsulation and parallel false static random access memory PSRAM; SPI NOR FLASH comprises clock input pin CLK1 and four input and output pin; Parallel PSRAM comprise clock input pin CLK2, more than four address input and data input and output pin; Wherein, four input and output pins of SPI NOR FLASH input with any four addresses of parallel PSRAM and are connected respectively with data input and output pin, and CLK1 and CLK2 is connected.

The invention has the beneficial effects as follows: in the present invention, owing to only the clock input pin CLK1 of SPI NOR FLASH being connected with the clock input pin CLK2 of parallel PSRAM, four input and output pins of SPI NOR FLASH are inputted with any four addresses of parallel PSRAM and is connected respectively with data input and output pin, thus realize the multiplexing of these pins, and other pins of two chips are not multiplexing, the storage chip of the two encapsulation can be made normally to work, therefore, present invention substantially reduces chip package and need multiplexing number of pin.The minimizing of number of pin, mean that in storage chip, the quantity of soldered ball greatly reduces, routing difficulty also correspondingly reduces greatly, and the area of the storage chip of encapsulation can reduce further.Meanwhile, because the area of SPI NOR FLASH is also much smaller than Parallel NOR FLASH, therefore, the area of the storage chip of this encapsulation provided by the invention is also just much smaller than sealed storage chip of the prior art.

On the basis of technique scheme, the present invention can also do following improvement:

Further, four input and output pins of SPI NOR FLASH input with the address of minimum four bits of parallel PSRAM and are connected respectively with data input and output pin.

Further, described SPI NOR FLASH is standard SPI NOR FLASH, and its four input and output pins are respectively SI, SO, WP# and HOLD#; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3; Wherein, SI and ADQ0, SO and ADQ1, WP# and ADQ2, HOLD# and ADQ3 are connected respectively.

Further, described SPI NOR FLASH is two passage SPI NOR FLASH, and its four input and output pins are respectively I/O0, I/O1, WP# and HOLD#; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3; Wherein, I/O0 and ADQ0, I/O1 and ADQ1, WP# and ADQ2, HOLD# and ADQ3 are connected respectively.

Further, described SPI NOR FLASH is four-way SPI NOR FLASH, and its four input and output pins are respectively I/O0, I/O1, I/O2 and I/O3; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3; Wherein, I/O0 and ADQ0, I/O1 and ADQ1, I/O2 and ADQ2, I/O3 and ADQ3 are connected respectively.

Further, SPI NOR FLASH folded envelope vertical with parallel PSRAM is described storage chip;

Or SPI NOR FLASH and parallel PSRAM is encapsulated as described storage chip side by side.

Further, this storage chip is fine-pitch ball grid array 52 ball sealing dress FBGA-52 chip or fine-pitch ball grid array 48 ball sealing dress FBGA-48 chip.

Present invention also offers a kind of embedded device applying above-mentioned storage chip, this embedded device comprises process chip and storage chip;

Described storage chip is the storage chip of encapsulation according to claim 1;

Described process chip comprises the input and output pin that sheet selects more than pin, clock output pin CLK and four;

Described SPI NOR FLASH and described parallel PSRAM also has respective sheet to select enable pin; The sheet of described process chip selects that pin selects enable pin with the sheet of described SPI NOR FLASH, the sheet of described parallel PSRAM selects enable pin to be all connected;

The be connected clock input pin of formed described storage chip of described CLK1, CLK2 is connected with CLK;

Four input and output pins of described SPI NOR FLASH input with any four addresses of parallel PSRAM and are connected respectively with data input and output pin, and four input and output pins of the described storage chip formed are connected with any four in the input and output pin of described process chip respectively.

Further, four input and output pins of SPI NOR FLASH input with the address of minimum four bits of parallel PSRAM and are connected respectively with data input and output pin, and four input and output pins of the described storage chip formed are connected with the input and output pin of minimum four bits of described process chip respectively.

Further, SPI NOR FLASH folded envelope vertical with parallel PSRAM is described storage chip;

Or SPI NOR FLASH and parallel PSRAM is encapsulated as described storage chip side by side.

Accompanying drawing explanation

Fig. 1 is the structure chart of the storage chip of encapsulation provided by the invention;

Fig. 2 is the structure chart of the embodiment of the storage chip that various SPI NOR FLASH and parallel PSRAM provided by the invention encapsulates;

Fig. 3 is the encapsulating structure figure of the FBGA-52 chip of the SPI NOR FLASH of 64M bit provided by the invention and the parallel PSRAM encapsulation of 32M bit;

Fig. 4 is the structure chart of embedded device provided by the invention.

Embodiment

Be described principle of the present invention and feature below in conjunction with accompanying drawing, example, only for explaining the present invention, is not intended to limit scope of the present invention.

Fig. 1 is the structure chart of the storage chip of encapsulation provided by the invention.As shown in Figure 1, this storage chip comprises: the serial non-volatile flash memory (SPI NOR FLASH) be encapsulated and parallel false static random access memory (PSRAM); SPI NOR FLASH comprises clock input pin (CLK1) and four input and output pins; Parallel PSRAM comprise clock input pin (CLK2), more than four address input and data input and output pin; Wherein, four input and output pins of SPI NOR FLASH input with the address of any four of parallel PSRAM and are connected respectively with data input and output pin, and CLK1 and CLK2 is connected.

Here, SPI NOR FLASH is the nonvolatile flash memory of serial, and its number of pin is than Parallel NOR FLASH much less used in prior art, and therefore, its area is also much smaller than Parallel NOR FLASH.

As shown in Figure 1, SPI NOR FLASH has 4 input and output pins, these input and output pins can be the pin of SPI NOR FLASH input and output data, each pin corresponds to a bit of its data stored of input and output, in Fig. 1, the input and output pin of the 1st is corresponding with the highest-order bit, 2nd bit input and output pin is corresponding with time higher bit position, and the rest may be inferred, and the 3rd, 4 bit input and output pins are corresponding with secondary low bit and lowest bit position respectively.

The clock input pin CLK1 of SPI NOR FLASH is the input end of clock of this chip.

The present invention parallel PSRAM used has n address input and data input and output pin, and n is here not less than 4.It is worthy of note, the address input of parallel PSRAM and data input and output pin can as the address input pins of this chip, to feed to parallel PSRAM Input Address, as the pin of its input and output data, parallel PSRAM input and output data can also be supplied.Each address input of parallel PSRAM is all corresponding with the address of parallel PSRAM or a bit of data with data input and output pin, such as, shown in Fig. 1 the 1st bit address input and data input and output pin corresponding with the highest-order bit of its address or data, 2nd bit address input and data input and output pin corresponding with secondary higher bit position, the rest may be inferred, n-th bit address input and data input and output pin corresponding with lowest bit position.

In addition, the clock input pin CLK2 of parallel PSRAM is the input end of clock of this chip.

In the present invention, be connected by CLK1 and CLK2, mean and carry out the two multiplexing, like this, CLK1 pin and CLK2 pin are respectively connected with a ball by a routing.

Equally, in the present invention, four input and output pins of SPI NOR FLASH are inputted with any four addresses of parallel PSRAM and is connected respectively with data input and output pin, mean these pins are also achieved multiplexing, like this, two pins be connected respectively are connected with a ball by a routing, and this only needs four balls to realize.Value it is noted that the ball described in the present invention, all refer to the soldered ball on the storage chip of encapsulation.

The address of the above-mentioned parallel PSRAM be connected respectively with SPI NOR FLASH tetra-input and output pins inputs and data input and output pin is that its any four addresses input and data input and output pin, and the way comparing main flow is at present: inputted in four input and output pins of SPI NOR FLASH and the address of minimum four bits of parallel PSRAM and be connected respectively with data input and output pin (the n-th-3 in Fig. 1 input and data input and output pin to the n-th bit address).

The present invention utilizes MCP technology, is encapsulated in by SPI NOR FLASH and parallel PSRAM in a Plastic Package shell, and the storage chip obtained is the chip of a kind of one-level list encapsulation, and this chip has saved the space of printed circuit board (PCB) (PCB) greatly.In addition, the complexity of this storage chip is relatively low, without the need to high-air-tightness and stand strict mechanical shock test's requirement, when needing employing high-density packages in limited PCB surface is long-pending, can reach higher packaging density.

As can be seen here, in the present invention, owing to only the clock input pin CLK1 of SPI NOR FLASH being connected with the clock input pin CLK2 of parallel PSRAM, four input and output pins of SPI NOR FLASH are inputted with any four addresses of parallel PSRAM and is connected respectively with data input and output pin, thus realize the multiplexing of these pins, and other pins of two chips are not multiplexing, the storage chip of the two encapsulation can be made normally to work, therefore, present invention substantially reduces chip package and need multiplexing number of pin.The minimizing of number of pin, mean that in storage chip, the quantity of soldered ball greatly reduces, routing difficulty also correspondingly reduces greatly, and the area of the storage chip of encapsulation can reduce further.Meanwhile, because the area of SPI NOR FLASH is also much smaller than Parallel NOR FLASH, therefore, the area of the storage chip of this encapsulation provided by the invention is also just much smaller than sealed storage chip of the prior art.

Four input and output pins of SPI NOR FLASH input with any four addresses of parallel PSRAM and are connected respectively with data input and output pin by the present invention, while meeting chip package application demand, decrease the number of the input and output pin encapsulating the storage chip obtained, therefore, this storage chip is when being connected with other chips, the wiring quantity of input and output pin is less, thus reduces the application cost of this storage chip.

The kind of SPI NOR FLASH is many, and such as, have standard SPI NOR FLASH, its clock frequency is 120MHz; Also have two passage SPI NOR FLASH, its clock frequency is 240MHz; Also have four-way SPI NOR FLASH, its clock frequency is 480MHz.

SPI NOR FLASH in the present invention can be any one above-mentioned SPI NOR FLASH.Fig. 2 is the structure chart of the embodiment of the storage chip that various SPI NOR FLASH and parallel PSRAM provided by the invention encapsulates, this embodiment is according to current main-stream way, four input and output pins of SPI NOR FLASH are inputted with the address of minimum four bits of parallel PSRAM and is connected respectively with data input and output pin, but it is not intended Fig. 2 to the input and output pin of SPI NOR FLASH in the present invention and the address of parallel PSRAM inputs and annexation between data input and output pin makes restriction, as long as four input and output pins of SPI NOR FLASH input with any four addresses of parallel PSRAM the embodiment be connected respectively with data input and output pin, all within protection scope of the present invention.

As shown in Figure 2, often kind of SPI NOR FLASH holds pin VSS with all having voltage input pin VCC and voltage, parallel PSRAM holds pin VSS with also having voltage input pin VCC and voltage, and meanwhile, it holds pin VSSQ with also having data input and output voltage pin VCCQ and data input and output.

In Fig. 2, when SPI NOR FLASH is standard SPI NOR FLASH, its four input and output pins are respectively SI, SO, WP# and HOLD# according to the data bits order from low to high of correspondence; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3 according to the data bits order from low to high of correspondence; Wherein, SI and ADQ0, SO and ADQ1, WP# and ADQ2, HOLD# and ADQ3 are connected respectively, namely input SI, SO, WP# and HOLD# input and output pin in standard SPI NOR FLASH and ADQ0, ADQ1, ADQ2, ADQ3 address in parallel PSRAM and data input and output pin achieves multiplexing respectively, the data transmission bauds of the storage chip formed like this is 120Mbits/s.

When SPI NOR FLASH is two passage SPI NOR FLASH, its four input and output pins are respectively I/O0, I/O1, WP# and HOLD# according to the data bits order from low to high of correspondence; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3 according to the data bits order from low to high of correspondence; Wherein, I/O0 and ADQ0, I/O1 and ADQ1, WP# and ADQ2, HOLD# and ADQ3 are connected respectively, namely to I/O0, I/O1, WP# and HOLD# input and output pin in two passage SPI NOR FLASH and ADQ0, ADQ1, ADQ2, ADQ3 address in parallel PSRAM inputs and data input and output pin achieves multiplexing respectively, the data transmission bauds of the storage chip formed like this is 240Mbits/s.

When SPI NOR FLASH is four-way SPI NOR FLASH, its four input and output pins are respectively I/O0, I/O1, I/O2 and I/O3 according to the data bits order from low to high of correspondence; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3 according to the data bits order from low to high of correspondence; Wherein, I/O0 and ADQ0, I/O1 and ADQ1, I/O2 and ADQ2, I/O3 and ADQ3 are connected respectively, namely input I/O0, I/O1, I/O2 and I/O3 input and output pin in four-way SPI NOR FLASH and ADQ0, ADQ1, ADQ2, ADQ3 address in parallel PSRAM and data input and output pin achieves multiplexing respectively, the data transmission bauds of the storage chip formed like this is 480Mbits/s.

Visible, the SPI NOR FLASH in the present invention can preferred four-way SPI NOR FLASH, and like this, the data transmission bauds of the storage chip of encapsulation can up to 480Mbits/s.

The mode encapsulated chip is a lot, such as, there is vertical folded envelope mode, also packaged type arranged side by side is had, the present invention can be wherein any one to the packaged type of SPI NOR FLASH and parallel PSRAM, namely SPI NOR FLASH can vertical folded envelope be above-mentioned storage chip with parallel PSRAM, also can be encapsulated as above-mentioned storage chip side by side.

The storage chip encapsulated by SPI NOR FLASH and parallel PSRAM provided by the present invention, can be fine-pitch ball grid array 52 ball sealing dress (FBGA-52) chip, also can be fine-pitch ball grid array 48 ball sealing dress (FBGA-48) chip.

Here, FBGA is the abbreviation of Fine-Pitch Ball Grid Array (fine-pitch ball grid array), it is a kind of face battle array pin configuration having soldered ball in bottom, this structure can make erection space needed for encapsulation close to chip size, like this, the ratio of chip area and package area is more than 1: 1.14, quite close to 1: 1 ideal situation, the storage chip of encapsulation provided by the invention is FBGA-52 chip or FBGA-48 chip, further reduces the gross area of storage chip.Utilize this chip, more chip can be loaded in equal area, thus increase the memory capacity of chip unit are.

For the FBGA-52 chip of the parallel PSRAM encapsulation of the SPI NOR FLASH of 64M bit and 32M bit, its encapsulating structure can be arranged as shown in Figure 3.This chip shown in Fig. 3 has 52 pins, be distributed in 6 row 10 row, every a line English alphabet is numbered, each row is numbered by a numeral, such as, line A the 5th arranges upper byte enable (UB#) pin that the pin of (being called for short A capable 5 to arrange) is parallel PSRAM.

In Fig. 3, CLK1 pin on SPI NOR FLASH is connected with the CLK2 pin on parallel PSRAM multiplexing rear formation CLK pin (B capable 4 arranges), and this pin is as the clock input pin of the storage chip of SPI NOR FLASH and parallel PSRAM chip package.

Have two VCCQ pins in Fig. 3, lay respectively at capable 1 row of C and E capable 8 arranges, these two VCCQ pins can as the data input and output voltage pin of SPI NOR FLASH and parallel PSRAM chip.Equally, also have two VSSQ pins in Fig. 3, lay respectively at capable 10 row of C and E capable 3 arranges, the two also can hold pin to use as the data input and output of SPI NOR FLASH and parallel PSRAM chip.In addition, the VCC pin of capable 5 row of B can be used as the voltage input pin of the two, and the VSS pin of capable 1 row of D holds pin with can be used as the voltage of the two.

Due to the present invention by four input and output pins of SPI NOR FLASH (as the SI of standard SPI NOR FLASH, SO, WP# and HOLD# pin, the I/O0 of two passage SPI NOR FLASH, I/O1, WP# and HOLD# pin, the I/O0 of four-way SPI NOR FLASH, I/O1, I/O2 and I/O3 pin) input with the address of any four bits of parallel PSRAM respectively and data input and output pin (four addresses as lowest bit position input and data input and output pin ADQ0, ADQ1, ADQ2, ADQ3) be connected and realize multiplexing, define four input and output pins of whole storage chip, therefore, the mark of above pin in SPI NOR FLASH is there is not in Fig. 3, and with the corresponding input and output pin represented to the mark of respective pin in its multiplexing parallel PSRAM on the storage chip that is packaged into.As in Fig. 3, parallel PSRAM has 16 address inputs and data input and output pin, ADQ numeral is below larger, the bit of its correspondence is also higher, such as, ADQ0 is that the address of parallel PSRAM inputs and pin corresponding with lowest bit position in data input and output pin, and ADQ15 is then corresponding with the highest-order bit.Equally, the ADQ0-ADQ15 in Fig. 3 can be the address input pin of parallel PSRAM chip, with Input Address, can also be the pin of its data input and output, for inputing or outputing data.

In Fig. 3, the implication of other pins is as shown in the table.

ADQ4-ADQ15 The input of parallel PSRAM address and data input and output 4-15 position A16-A20 Parallel PSRAM address inputs 16-20 position UB# Parallel PSRAM upper byte is enable LB# Parallel PSRAM low byte is enable AVD# Parallel PSRAM address effectively inputs CRE Parallel PSRAM control register is enable CS# Parallel PSRAM sheet selects enable OE# Parallel PSRAM output enable WE# Parallel PSRAM writes enable CE# SPI NOR FLASH chip is selected enable NC Empty WAIT# Parallel PSRAM data effectively judge RESET# SPI NOR FLASH resets CRE Parallel PSRAM register controls enable

The length of the storage chip shown in Fig. 3 and width can all reach 6.00 millimeters, and thickness can reach 0.90 millimeter, and error is 0.10 millimeter.Spheroid maximum distance between centers on this storage chip length direction is (in Fig. 3 on 1-the 10th column direction, often row the 1st arrange ball and the 10th ball arranged between centre-to-centre spacing) be 4.50 millimeters, spheroid maximum distance between centers on Width is (in Fig. 3 on A-line F direction, centre-to-centre spacing often between row line A and the ball of line F) be 2.50 millimeters, further, often row and the centre-to-centre spacing often arranged between two adjacent balls are 0.50 millimeter; The diameter of each ball is 0.30 millimeter, and error is 0.05 millimeter; The height of each ball on storage chip surface is 0.23 millimeter, and error is 0.50 millimeter.

The storage chip of above-mentioned encapsulation provided by the invention can be applied to XIP (execute In Place performs in chip) storage architecture, and SPI NOR FLASH can store application program, runs this application program in parallel PSRAM.

Present invention also offers a kind of embedded device applying the storage chip of above-mentioned encapsulation, Fig. 4 is the structure chart of embedded device provided by the invention.As shown in Figure 4, this embedded device comprises process chip and storage chip, here storage chip is the storage chip of above-mentioned encapsulation, and the storage chip of this encapsulation comprises: the serial non-volatile flash memory (SPI NOR FLASH) of encapsulation and parallel false static random access memory (PSRAM); SPI NOR FLASH comprises clock input pin CLK1 and four input and output pin; Parallel PSRAM comprises address input and the data input and output pin of more than clock input pin CLK2 and four; Wherein, four input and output pins of SPI NOR FLASH input with any four addresses of parallel PSRAM and are connected respectively with data input and output pin, and CLK1 and CLK2 is connected.

Process chip comprises the input and output pin that sheet selects more than pin, clock output pin CLK and four;

SPI NOR FLASH and parallel PSRAM also has respective sheet to select enable pin; The sheet of process chip selects pin and the sheet of SPI NOR FLASH to select enable pin, the sheet of parallel PSRAM selects enable pin to be all connected;

The be connected clock input pin of formed storage chip of CLK1, CLK2 is connected with CLK;

Four input and output pins of SPI NOR FLASH input with any four addresses of parallel PSRAM and are connected respectively with data input and output pin, and four input and output pins of the storage chip formed are connected with any four in the input and output pin of process chip respectively.

In this embedded device, four input and output pins of SPI NOR FLASH and all addresses of parallel PSRAM input identical with the respective pin in the purposes of data input and output pin and the storage chip of the encapsulation shown in Fig. 1, that is: the input and output pin of SPI NOR FLASH is the pin of its input and output data, and each pin corresponds to a bit of data; The address input of parallel PSRAM and data input and output pin are the pin of its address input pin and data I/O, and each pin is corresponding with a bit of address or data.The input and output pin of the process chip in this embedded device is the pin of its OPADD, input/output data, and each pin is corresponding with a bit of address or data.

In this embedded device, process chip selects the sheet of pin and respective chip to select enable pin that chip selection signal is sent to SPI NOR FLASH and parallel PSRAM respectively by sheet, thus make these two chips in running order respectively, choosing SPI NOR FLASH and parallel PSRAM for the moment, also export clock signal to this selected chip by the clock input pin (CLK1 or CLK2) of CLK and respective chip successively, make the clock synchronous of itself and process chip.

When chip selection signal is chosen SPI NOR FLASH and is not chosen parallel PSRAM, parallel PSRAM does not work, process chip is by the input and output pin of each bit of SPI NOR FLASH, the application program that SPI NOR FLASH stores by the input and output pin of self reads, then, process chip chip selection signal is chosen parallel PSRAM and is not chosen SPI NOR FLASH, then SPI NOR FLASH does not work, process chip can by the application program that read and corresponding data successively by the input and output pin of each bit of self, the address input of each bit of parallel PSRAM and data input and output pin are sent in parallel PSRAM and are carried out computing.

Four input and output pins of above-mentioned SPI NOR FLASH input with any four addresses of parallel PSRAM: four input and output pins of SPI NOR FLASH input with the address of minimum four bits of parallel PSRAM and are connected respectively with data input and output pin, then four input and output pins of storage chip that this annexation is formed are connected with the input and output pin of minimum four bits of process chip respectively.Identical with Fig. 1, in Fig. 4 SPI NOR FLASH four input and output pins in, 1-4 position successively with data to be up to lowest bit position corresponding, in n (n is not less than 4) the individual address input of parallel PSRAM and data input and output pin, 1-n position successively with address or data to be up to lowest bit position corresponding, equally, in Fig. 4 process chip the individual input and output pin of m (m is not less than 4) in, 1-m position successively with address or data to be up to lowest bit position corresponding, the 1-4 bit input and output pin that then above-mentioned main flow way correspond to SPI NOR FLASH inputs to the n-th bit address with (n-3) of parallel PSRAM respectively and is connected with data input and output pin, four input and output pins of the storage chip of the encapsulation formed are connected to m bit input and output pin with (m-3) position of process chip respectively.

Above-mentioned SPI NOR FLASH and the packaged type of parallel PSRAM can be vertical folded envelope, and namely the two vertical folded envelope is the storage chip of above-mentioned encapsulation.Certainly, the two also can take packaged type arranged side by side to encapsulate, and namely SPI NOR FLASH and parallel PSRAM is encapsulated as the storage chip of above-mentioned encapsulation side by side.

This embedded device is owing to have employed the storage chip of above-mentioned encapsulation, thus area is more much smaller than prior art, is more broadly applicable to the various portable electron device such as mobile phone, laptop computer, panel computer and the various industrial control field such as various compressor, wood-based plate press.

As can be seen here, the present invention has the following advantages:

(1) in the present invention, owing to only the clock input pin CLK1 of SPI NOR FLASH being connected with the clock input pin CLK2 of parallel PSRAM, four input and output pins of SPI NOR FLASH are inputted with any four addresses of parallel PSRAM and is connected respectively with data input and output pin, thus realize the multiplexing of these pins, and other pins of two chips are not multiplexing, the storage chip of the two encapsulation can be made normally to work, therefore, present invention substantially reduces chip package and need multiplexing number of pin.The minimizing of number of pin, mean that in storage chip, the quantity of soldered ball greatly reduces, routing difficulty also correspondingly reduces greatly, and the area of the storage chip of encapsulation can reduce further.Meanwhile, because the area of SPI NOR FLASH is also much smaller than Parallel NOR FLASH, therefore, the area of the storage chip of this encapsulation provided by the invention is also just much smaller than sealed storage chip of the prior art.

(2) four input and output pins of SPI NOR FLASH input with the address of parallel PSRAM and are connected respectively with data input and output pin by the present invention, while meeting chip package application demand, decrease the number of the input and output pin of storage chip, therefore, this chip is when being connected with other chips, the wiring quantity of input and output pin is less, thus reduces the application cost of chip.

(3) the SPI NOR FLASH in the present invention can preferred four-way SPI NOR FLASH, and like this, the data transmission bauds of the storage chip of encapsulation can up to 480Mbits/s.

(4) storage chip provided by the invention is FBGA-52 chip or FBGA-48 chip, further reduces the gross area of the storage chip of encapsulation.Utilize this chip, more chip can be loaded in equal area, thus increase the memory capacity of chip unit are.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a storage chip for encapsulation, it is characterized in that, this chip comprises: the serial non-volatile flash memory SPI NOR FLASH of encapsulation and parallel false static random access memory PSRAM; SPI NOR FLASH comprises clock input pin CLK1 and four input and output pin; Parallel PSRAM comprise clock input pin CLK2, more than four address input and data input and output pin; Wherein, four input and output pins of SPI NOR FLASH input with any four addresses of parallel PSRAM and are connected respectively with data input and output pin, and CLK1 and CLK2 is connected.
2. storage chip according to claim 1, is characterized in that, four input and output pins of SPI NOR FLASH input with the address of minimum four bits of parallel PSRAM and are connected respectively with data input and output pin.
3. storage chip according to claim 2, is characterized in that, described SPI NOR FLASH is standard SPI NOR FLASH, and its four input and output pins are respectively SI, SO, WP# and HOLD#; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3; Wherein, SI and ADQ0, SO and ADQ1, WP# and ADQ2, HOLD# and ADQ3 are connected respectively.
4. storage chip according to claim 2, is characterized in that, described SPI NOR FLASH is two passage SPI NOR FLASH, and its four input and output pins are respectively I/O0, I/O1, WP# and HOLD#; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3; Wherein, I/O0 and ADQ0, I/O1 and ADQ1, WP# and ADQ2, HOLD# and ADQ3 are connected respectively.
5. storage chip according to claim 2, is characterized in that, described SPI NOR FLASH is four-way SPI NOR FLASH, and its four input and output pins are respectively I/O0, I/O1, I/O2 and I/O3; Address input and the data input and output pin of minimum four bits of parallel PSRAM are respectively ADQ0, ADQ1, ADQ2, ADQ3; Wherein, I/O0 and ADQ0, I/O1 and ADQ1, I/O2 and ADQ2, I/O3 and ADQ3 are connected respectively.
6. the storage chip according to the arbitrary claim in claim 1-5, is characterized in that, SPI NOR FLASH folded envelope vertical with parallel PSRAM is described storage chip;
Or SPI NOR FLASH and parallel PSRAM is encapsulated as described storage chip side by side.
7. the storage chip according to the arbitrary claim in claim 1-5, is characterized in that, this storage chip is fine-pitch ball grid array 52 ball sealing dress FBGA-52 chip or fine-pitch ball grid array 48 ball sealing dress FBGA-48 chip.
8. an embedded device, is characterized in that, this embedded device comprises process chip and storage chip;
Described storage chip is the storage chip of encapsulation according to claim 1;
Described process chip comprises the input and output pin that sheet selects more than pin, clock output pin CLK and four;
Described SPI NOR FLASH and described parallel PSRAM also has respective sheet to select enable pin; The sheet of described process chip selects that pin selects enable pin with the sheet of described SPI NOR FLASH, the sheet of described parallel PSRAM selects enable pin to be all connected;
The be connected clock input pin of formed described storage chip of described CLK1, CLK2 is connected with CLK;
Four the input and output pins being inputted the formed described storage chip that to be connected respectively with data input and output pin by four input and output pins of described SPI NOR FLASH and any four addresses of parallel PSRAM are connected with the input and output pin of minimum four bits of described process chip respectively.
9. embedded device according to claim 8, it is characterized in that, four input and output pins of SPI NOR FLASH input with the address of minimum four bits of parallel PSRAM and are connected respectively with data input and output pin, and four input and output pins of the described storage chip formed are connected with the input and output pin of minimum four bits of described process chip respectively.
10. embedded device according to claim 8 or claim 9, is characterized in that, SPI NOR FLASH folded envelope vertical with parallel PSRAM is described storage chip;
Or SPI NOR FLASH and parallel PSRAM is encapsulated as described storage chip side by side.
CN201110154392.3A 2011-06-09 2011-06-09 Storage chip, the embedded device of encapsulation CN102820302B (en)

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CN103247612B (en) 2013-04-09 2015-09-23 北京兆易创新科技股份有限公司 A kind of enhancement mode FLASH chip and a kind of chip packaging method
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