CN102819997B - Display method and device for displaying acceleration - Google Patents
Display method and device for displaying acceleration Download PDFInfo
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- CN102819997B CN102819997B CN201210243649.7A CN201210243649A CN102819997B CN 102819997 B CN102819997 B CN 102819997B CN 201210243649 A CN201210243649 A CN 201210243649A CN 102819997 B CN102819997 B CN 102819997B
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Abstract
The invention provides a display method and a device for displaying acceleration. The display method for displaying acceleration comprises the steps that a processor divides each of at least one predetermined area in a display interface in at least one regular pattern sub interface and obtains position and size of each regular pattern sub interface; in a subsequent screen brushing display, the processor transports the position, size and color value of each regular pattern sub interface to a field-programmable gate array; and the field-programmable gate array transports the position, size and color value of each regular pattern sub interface to a display, and the display is controlled to display.
Description
Technical field
The application relates to technical field of medical equipment, more specifically, relates to a kind of display packing for showing acceleration and device.
Background technology
In the prior art, when patient monitor works, because the parameters such as electrocardio are Real-Time Monitoring and display, therefore, for must brush screen with more new data, also be just need to refresh for those constant contents (such as, menu control etc.) in real time display.Current way is that the value of all pixels (such as, coordinate position value, color value etc.) is transported to display by processor again.Fig. 1 is the diagram of the patient monitor display interface that prior art is shown.As shown in Figure 1, non-invasive blood pressure is measured color shared by (NIBP) data and content etc. and all may be changed, if each pixel to be transported to display, display speed will be caused slack-off, cause the wasting of resources simultaneously.
Such as, 16 chromatic graph sheets of one width 800*600 resolution are shown on patient monitor display screen, if processor carries a pixel to display at every turn, then need to carry 800*600 X-coordinate, 800*600 Y-coordinate, also need carrying 800*600 16 color values, greatly reduce display speed, and serious waste of resources.
Summary of the invention
According to an aspect of the present invention, provide a kind of display packing for showing acceleration, described method comprises: each at least one presumptive area in display interface be divided in respectively in the sub-interface of at least one regular figure by processor, and obtain position, the size at the sub-interface of described regular figure; During each brush screen display, by processor, the position at sub-for described regular figure interface, size, color value are transported to field programmable gate array; By field programmable gate array, the position at sub-for described regular figure interface, size, color value are transported to display and control display and show.
When the sub-interface of regular figure covers with being shown other region in interface or the sub-interface portion of Else Rule figure, can be multiple regular figure grandson interfaces by the part Further Division that sub-for described regular figure interface is not capped by processor, obtain each position in multiple regular figure grandson interface, size, and during each brush screen display, only the position at not capped multiple regular figure grandson interfaces, size, color value can be transported to field programmable gate array by processor.
Other region in the display interface at the partly sub-interface of cover up rule figure or the quantity at the sub-interface of Else Rule figure can be one or two.
The step being multiple regular figure grandson interface by the part Further Division that sub-for described regular figure interface is not capped by processor can comprise: the part be not capped to divide the sub-interface of described regular figure according to the principle of the minimum number at the multiple regular figure grandson interfaces divided by processor.
By processor, each step be divided in respectively in the sub-interface of at least one regular figure at least one presumptive area in display interface can be comprised: each at least one presumptive area described is divided in the sub-interface of at least one regular figure by least one presumptive area that can not be changed based on position in display interface by processor respectively.
The described display packing for showing acceleration also can comprise: the sub-interface of described regular figure obtained and/or the position at described regular figure grandson interface, size store in memory by processor.
Field programmable gate array can have function of hardware acceleration.
According to an aspect of the present invention, provide a kind of display device for showing acceleration, described device comprises: processor, each at least one presumptive area in display interface is divided in the sub-interface of at least one regular figure respectively, obtain the position at the sub-interface of each regular figure, size, and during each brush screen display, the position at sub-for each regular figure interface, size, color value are transported to field programmable gate array; Field programmable gate array, is transported to display and controls display show the position at sub-for each regular figure interface, size, color value; Display, shows under the control of programmable gate array at the scene.
When the sub-interface of regular figure covers with being shown other region in interface or the sub-interface portion of Else Rule figure, the part Further Division that sub-for described regular figure interface is not capped can be multiple regular figure grandson interfaces by processor, obtain each position in multiple regular figure grandson interface, size, and during each brush screen display, the position at not capped multiple regular figure grandson interfaces, size, color value only can be transported to field programmable gate array by processor.
Other region in the display interface at the partly sub-interface of cover up rule figure or the quantity at the sub-interface of Else Rule figure can be one or two.
Processor can divide according to the principle of minimum number at the multiple regular figure grandson interfaces divided the part that the sub-interface of described regular figure is not capped.
Each presumptive area at least one presumptive area described is divided in the sub-interface of at least one regular figure by least one presumptive area that processor can not be able to change based on position in display interface respectively.
The described display device for showing acceleration also can comprise: storer, stores the position at the sub-interface of described regular figure and/or the described regular figure grandson interface obtained by processor, size.
Field programmable gate array can have function of hardware acceleration.
Beneficial effect
According to exemplary embodiment of the present invention, owing to the presumptive area in display interface being divided in the sub-interface of different regular figures, and starting point coordinate, length, width, the color value at the sub-interface of described regular figure is only transmitted when showing, thus do not need coordinate and the color value of carrying each pixel, improve display speed; When certain a little interface is capped, owing to again dividing capped sub-interface, and only carries not capped grandson interface, thus can display speed be improved equally.In addition, due to based on there is function of hardware acceleration but the FPGA without hardware hierarchical function carries out the display of the display interface of the content comprising covering, thus hardware performance can be saved, reduce costs.
Part in ensuing description is set forth the present invention other in and/or advantage, some will be clearly by describing, or can learn through enforcement of the present invention.
Accompanying drawing explanation
By the detailed description of carrying out below in conjunction with accompanying drawing, above and other objects of the present invention and feature will become apparent, wherein:
Fig. 1 is the diagram of the patient monitor display interface that prior art is shown;
Fig. 2 illustrates according to an exemplary embodiment of the present invention for showing the diagram of the display device of acceleration;
Fig. 3 illustrates to divide by the diagram at the sub-interface of regular figure that covers of Else Rule figure interface portion ground according to an exemplary embodiment of the present invention;
Fig. 4 illustrates according to an exemplary embodiment of the present invention for showing the process flow diagram of the regular figure cutting display packing of acceleration.
Embodiment
Now, describe exemplary embodiment of the present invention in detail, its example represents in the accompanying drawings, and wherein, identical label represents identical parts all the time.
Fig. 2 illustrates according to an exemplary embodiment of the present invention for showing the diagram of the display device of acceleration.
As described in Figure 2, the display device according to an exemplary embodiment of the present invention for showing acceleration comprises processor 210, FPGA 220, display 230.
Each at least one presumptive area in display interface can be divided in the sub-interface of different regular figures by processor 210 respectively, obtain the position at the sub-interface of described regular figure, size, and in brush screen display subsequently, the position at sub-for described regular figure interface, size, color value are transported to FPGA 220.Should understand, regular figure refers to the regular figure of tool in programming, can include but not limited to rectangle, triangle etc.With rectangle exemplarily, obtain the position at the sub-interface of each rectangle, large I is more specifically embodied as starting point coordinate, length, the width of determining the sub-interface of each rectangle.In addition, only exemplarily, processor 210 at least one presumptive area (cardiogram (ECG) region 110 such as, shown in Fig. 1, the blood oxygen saturation (SpO that can not be able to change based on position in display interface
2) region 120 etc.) each at least one presumptive area described is divided in the sub-interface of different regular figures respectively.In addition, only exemplarily, processor 210 can be minimum and the principle that can comprise the region of expectation completely comes the sub-interface of division rule figure according to the size at the sub-interface of regular figure divided, such as, processor 210 also can by the numeric area in cardiogram (ECG) region 110 (namely, the region at " 60 " place) be divided in a sub-interface of regular figure, more specifically, only with rectangle exemplarily, processor 210 can use four limits rectangle tangent with this numeric area respectively this numeric area to be divided in the sub-interface of rectangle, the size at the sub-interface of rectangle is now minimum and can comprise this numeric area completely.
In addition, when the sub-interface of regular figure covers with being shown other region in interface or the sub-interface portion of Else Rule figure, the part Further Division that sub-for described regular figure interface is not capped can be also multiple regular figure grandson interfaces by processor 210, obtain each position in multiple regular figure grandson interface, size, and in brush screen display subsequently, only the position at not capped multiple regular figure grandson interfaces, size, color value can be transported to FPGA 220.Should understand, partly other region at the sub-interface of cover up rule figure or the sub-interface of Else Rule figure can be any amount, arbitrary size, and can the sub-interface of cover up rule figure at an arbitrary position.Preferably, partly other region at the sub-interface of cover up rule figure or the quantity at the sub-interface of Else Rule figure can be one or two.In addition, if partly other region at the sub-interface of cover up rule figure or the sub-interface of Else Rule figure are ejected suddenly, then processor 210 using other region at the sub-interface of partly cover up rule figure of described unexpected ejection or the sub-interface of Else Rule figure as the sub-interface of new regular figure, and can obtain their position, size.
Here, only exemplarily, processor 210 can divide according to the principle of minimum number at the multiple regular figure grandson interfaces divided the part that the sub-interface of described regular figure is not capped, now, need the minimum number of the regular figure of carrying, can display speed be improved.Fig. 3 illustrates to divide according to an exemplary embodiment of the present invention by the diagram at the sub-interface of regular figure that covers of Else Rule figure interface portion ground.Should understand, the example of rectangle as regular figure is only shown in Fig. 3, but the present invention be not limited to this.As shown in Figure 3, the sub-interface of rectangle 310 is partly covered by the sub-interface 320 of rectangle, now, for the division at the sub-interface 310 of rectangle, following several method can be had: according to the long limit of the summit A at the sub-interface of rectangle 320 and the extended line of minor face, the part that sub-for rectangle interface 310 is not capped can be divided into three rectangle grandson interfaces 311,312,313; According to the extended line on the long limit of the summit A at the sub-interface of rectangle 320, the part that sub-for rectangle interface 310 is not capped can be divided into two rectangle grandson interface 311+312,313; According to the extended line of the minor face of the summit A at the sub-interface 320 of rectangle, the part that sub-for rectangle interface 310 is not capped can be divided into two rectangle grandson interfaces 311,312+313.According to the principle of the minimum number at the multiple regular figure grandson interfaces divided, latter two dividing mode is all feasible, that is, best for using straight line to divide, not all right again with two straight lines divisions, not all right again with three straight lines divisions, until irregular figure to be divided into the regular figure that can carry out carrying, the regular figure at this moment obtained is the regular figure of minimum number.Should understand, Fig. 3 and division methods thereof are example, partly the sub-interface of Else Rule figure at the sub-interface of cover up rule figure can be any amount, arbitrary size, and can the sub-interface of cover up rule figure at an arbitrary position, the not capped irregular figure of similar method to the sub-interface of regular figure now can be adopted to divide, do not repeat them here.
The position at sub-for each regular figure interface, size, color value can be transported to display and control display and show by FPGA 220.Here, only exemplarily, FPGA 220 can have function of hardware acceleration, but does not have hardware hierarchical function.
Display 230 can show under the control of FPGA 220.Should understand, display 230 carries out display and belongs to this area common technology means under the control of FPGA 220, in order to avoid fuzzy theme of the present invention, does not repeat them here.
In addition, the display device according to an exemplary embodiment of the present invention for showing acceleration also can comprise storer, for storing position, the size at the sub-interface of each regular figure and/or each regular figure grandson interface obtained by processor 210.
Fig. 4 illustrates according to an exemplary embodiment of the present invention for showing the process flow diagram of the display packing of acceleration.
As shown in Figure 4, at operation S410, by processor, each at least one presumptive area in display interface is divided in the sub-interface of different regular figures respectively, and obtains position, the size at the sub-interface of each regular figure.
At operation S420, in brush screen display subsequently, by processor, the position at sub-for each regular figure interface, size, color value are transported to field programmable gate array.
At operation S430, by field programmable gate array, the position at the described sub-interface of each regular figure, size, color value are transported to display and control display and show.
According to exemplary embodiment of the present invention, owing to the presumptive area in display interface being divided in the sub-interface of different regular figures, and only transmit the position at the sub-interface of each regular figure, size, color value when showing, thus do not need coordinate and the color value of carrying each pixel, improve display speed; When certain a little interface is capped, owing to again dividing capped sub-interface, and only carries not capped grandson interface, thus can display speed be improved equally.In addition, due to based on there is function of hardware acceleration but the FPGA without hardware hierarchical function carries out the display of the display interface of the content comprising covering, thus hardware performance can be saved, reduce costs.
Although illustrate and describe the present invention with reference to certain exemplary embodiments, but it will be apparent to one skilled in the art that the various changes can made when not departing from the spirit and scope of the present invention of scope by claim and equivalents thereof in form and details.
Claims (12)
1., for showing a display packing for acceleration, described method comprises:
By processor, each at least one presumptive area in display interface is divided in the sub-interface of at least one regular figure respectively, and obtains position, the size at the sub-interface of each regular figure;
During each brush screen display, by processor, the position at sub-for each regular figure interface, size, color value are transported to field programmable gate array;
By field programmable gate array, the position at the described sub-interface of each regular figure, size, color value are transported to display and control display and show,
Wherein, when the sub-interface of regular figure covers with being shown other region in interface or the sub-interface portion of Else Rule figure, be multiple regular figure grandson interfaces by processor by the part Further Division that sub-for described regular figure interface is not capped, obtain each position in multiple regular figure grandson interface, size, and during each brush screen display, only the position at not capped multiple regular figure grandson interfaces, size, color value are transported to field programmable gate array by processor.
2. as claimed in claim 1 for showing the display packing of acceleration, wherein, other region in the display interface at the partly sub-interface of cover up rule figure or the quantity at the sub-interface of Else Rule figure are one or two.
3. as claimed in claim 1 for showing the display packing of acceleration, wherein, the step being multiple regular figure grandson interface by the part Further Division that sub-for described regular figure interface is not capped by processor comprises: the part be not capped to divide the sub-interface of described regular figure according to the principle of the minimum number at the multiple regular figure grandson interfaces divided by processor.
4. as claimed in claim 1 for showing the display packing of acceleration, wherein, by processor, each step be divided in respectively in the sub-interface of at least one regular figure at least one presumptive area in display interface is comprised: each at least one presumptive area described is divided in the sub-interface of at least one regular figure by least one presumptive area that can not be changed based on position in display interface by processor respectively.
5. as claimed in claim 1 for showing the display packing of acceleration, also comprise: the position at the sub-interface of each regular figure obtained and/or each regular figure grandson interface, size store in memory by processor.
6. the display packing for showing acceleration as described in one of Claims 1 to 5, wherein, field programmable gate array has function of hardware acceleration.
7., for showing a display device for acceleration, described device comprises:
Processor, each at least one presumptive area in display interface is divided in the sub-interface of at least one regular figure respectively, obtain the position at the sub-interface of each regular figure, size, and during each brush screen display, the position at sub-for each regular figure interface, size, color value are transported to field programmable gate array;
Field programmable gate array, is transported to display and controls display show the position at sub-for each regular figure interface, size, color value;
Display, shows under the control of programmable gate array at the scene,
Wherein, when the sub-interface of regular figure covers with being shown other region in interface or the sub-interface portion of Else Rule figure, the part Further Division that sub-for described regular figure interface is not capped is multiple regular figure grandson interfaces by processor, obtain each position in multiple regular figure grandson interface, size, and during each brush screen display, the position at not capped multiple regular figure grandson interfaces, size, color value are only transported to field programmable gate array by processor.
8. as claimed in claim 7 for showing the display device of acceleration, wherein, other region in the display interface at the partly sub-interface of cover up rule figure or the quantity at the sub-interface of Else Rule figure are one or two.
9. as claimed in claim 7 for showing the display device of acceleration, wherein, processor divides according to the principle of the minimum number at the multiple regular figure grandson interfaces divided the part that the sub-interface of described regular figure is not capped.
10. as claimed in claim 7 for showing the display device of acceleration, wherein, each presumptive area at least one presumptive area described is divided in the sub-interface of at least one regular figure by processor can not change based on position in display interface at least one presumptive area respectively.
11. is as claimed in claim 7 for showing the display device of acceleration, also comprises: storer, store the position at the sub-interface of each regular figure and/or each regular figure grandson interface obtained by processor, size.
12. display device for showing acceleration as described in one of claim 7 ~ 11, wherein, field programmable gate array has function of hardware acceleration.
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| CN201210243649.7A CN102819997B (en) | 2012-07-13 | 2012-07-13 | Display method and device for displaying acceleration |
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| CN201210243649.7A CN102819997B (en) | 2012-07-13 | 2012-07-13 | Display method and device for displaying acceleration |
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| CN102819997B true CN102819997B (en) | 2015-05-20 |
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| CN108255523A (en) * | 2016-12-28 | 2018-07-06 | 北京普源精电科技有限公司 | Graphical user interface creating method, device, system and FPGA |
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| CN101471040B (en) * | 2007-12-25 | 2011-05-18 | 安凯(广州)微电子技术有限公司 | Simulated overlapping surface implementing method based on MPU interface LCD module |
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| US7205979B2 (en) * | 1987-03-17 | 2007-04-17 | Sun Microsystems, Inc. | Computer data entry and manipulation apparatus and method |
| CN1527243A (en) * | 2003-03-05 | 2004-09-08 | 卡西欧计算机株式会社 | Image reading device |
| CN101036147A (en) * | 2004-07-15 | 2007-09-12 | 爱克发公司 | Image display system and method |
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Address after: 518102, Shenzhen, Guangdong Province, Baoan District, Xixiang Bao Road 168, Shenzhen famous industrial products display procurement center, block A, building seven Applicant after: Shenzhen Biocare Bio-Medical Equipment Co., Ltd. Address before: 518102, Shenzhen, Guangdong Province, Baoan District, Xixiang Bao Road 168, Shenzhen famous industrial products display procurement center, block A, building seven Applicant before: Shenzhen Biocare Electronics Co., Ltd. |
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