CN102819411A - Display control circuit - Google Patents
Display control circuit Download PDFInfo
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- CN102819411A CN102819411A CN2011101555329A CN201110155532A CN102819411A CN 102819411 A CN102819411 A CN 102819411A CN 2011101555329 A CN2011101555329 A CN 2011101555329A CN 201110155532 A CN201110155532 A CN 201110155532A CN 102819411 A CN102819411 A CN 102819411A
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- bmc
- display
- module
- selection module
- chip
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Abstract
The invention relates to a display control circuit, which comprises a core logic control module, a system display chip, a BMC (baseboard management controller), a BMC display chip and a selecting module. When the BMC is started and a starting program of the system display chip is not completed, a first level control signal is outputted by the BMC to a control end of the selecting module to gate an information transfer channel between a first input end and an output end of the selecting module, and data to be displayed of the BMC is inputted into the first input end of the selecting module by the BMC display chip, and is outputted to an interface used for connecting a display from the output end of the selecting module. After the BMC is started and before the starting program of the system display chip is completed, the data to be displayed of the BMC of the display control circuit can be displayed on the display through the BMC display chip and the selecting module.
Description
Technical field
The present invention relates to a kind of display control circuit.
Background technology
At present; The system for computer display chip can have been realized BMC (Baseboard Management Controller; Baseboard management controller) and the switching displayed between the system; But when BMC starts and this system's display chip when not accomplishing start-up routine, BMC shows then and can't realize through this system's display chip.
Summary of the invention
In view of above content, be necessary to provide a kind of and start and this system's display chip can be realized the display control circuit of BMC demonstration when not accomplishing start-up routine as BMC.
A kind of display control circuit comprises:
One system's display chip;
One BMC;
The one core logic control module that links to each other with this system's display chip and this BMC is used to judge whether this system's display chip accomplishes start-up routine, and accomplishes and send one first when starting and control signal to this BMC recognizing this system's display chip;
The one BMC display chip that links to each other with this BMC; And
One selects module, comprises the output terminal that second control end that first control end, that second input end that the first input end, that links to each other with this BMC display chip links to each other with this system's display chip, links to each other with first pin of one second interface of this BMC links to each other with second pin of this second interface and links to each other with second interface that is used to be connected a display; When this BMC starts and this system's display chip when not accomplishing start-up routine; This BMC exports first group and controls signal to this selection module with the first input end of this selection module of gating and the information transfer channel between the output terminal; Then the data to be displayed of this BMC through this selections module of this BMC display chip input first input end and export second this interface to from the output terminal of this selection module so that the data to be displayed of this BMC of this display demonstration; After this system's display chip is accomplished start-up routine; This core logic control module is sent first and is controlled signal to this BMC; Make this BMC export second group of control end that controls signal to this selection module with second input end of this selection module of gating and the information transfer channel between the output terminal, then first data to be displayed of computer system inputs to second input end of this selection module and exports this second interface to from the output terminal of this selection module through this system's display chip.
Above-mentioned display control circuit is opened the first input end of this selection module and the information transfer channel between the output terminal according to first group of control signal of BMC output; So that BMC starts the back and this system's display chip is accomplished before the start-up routine, the data to be displayed of BMC can be shown in this display.
Description of drawings
Fig. 1 is the block scheme of the preferred embodiments of display control circuit of the present invention.
The main element symbol description
| |
100 |
| The core |
90 |
| System's |
60 |
| The BMC |
70 |
| Select |
50 |
| |
40 |
| BMC | 80 |
Following embodiment will combine above-mentioned accompanying drawing to further specify the present invention.
Embodiment
Please refer to Fig. 1; First interface 40 that being used on display control circuit 100 of the present invention and the computing machine (figure does not show) is connected a display links to each other; The preferred embodiments of this display control circuit 100 comprises that the BMC display chip 70 and that system's display chip 60, that BMC (Baseboard Management Controller, baseboard management controller) 80, that a core logic control module 90, links to each other with this core logic control module 90 links to each other with this core logic control module 90 links to each other with BMC 80 selects module 50.
In this embodiment, this core logic control module 90 comprises the north and south bridge chip, and it is used to judge whether system's display chip 60 accomplishes start-up routine, and transmission one controls signal to this BMC 80 after recognizing these system's display chip 60 completion start-up routines.
This selection module 50 comprises first to the 3rd input end, first control end, second control end and an output terminal.First control end of this selection module 50 and second control end are connected first pin and second pin of one second interface 20 of this BMC 80 respectively; This selects first to the 3rd input end of module 50 to link to each other with this BMC display chip 70, this system's display chip 60 and this core logic control module 90 respectively, and this selects the output terminal of module 50 to connect this interface 40.Signal-selectivity ground conducting first input end that this selection module 50 is used for receiving according to its control end or the information transfer channel between second input end and the output terminal.In this embodiment; This second interface 20 is GPIO (General Purpose Input Output; General input and output) interface; This selection module 50 is an electronic switch chip, and this electronic switch chip comprises first to the 3rd input pin, first to second a control pin and the output pin.
Principle of work in the face of preferred embodiments of the present invention describes down:
After computing machine powers on; This BMC 80 starts and first pin through this second interface 20 and second pin send first group and control signal to this selection module 50; So that should select the information transfer channel between module 50 gating first input ends and the output terminal; At this moment, the data to be displayed of this BMC 80 through this BMC display chip 70 these selection modules 50 of input first input end and export this interface 40 to from the output terminal of this selection module 50 and show to import this display.
After a time period; Transmission one first controlled signal to this BMC 80 after this core logic control module 90 recognized these system's display chip 60 completion start-up routines; So that sending second group, first pin and second pin of this BMC 80 through this second interface 20 control signal to this selection module 50; Then make information transfer channel between this selection module 50 gatings, second input end and the output terminal; At this moment, first data to be displayed of system through this system's display chip 60 these selection modules 50 of input second input end and export this interface 40 to from the output terminal of this selection module 50 and show to import this display.When these core logic control module 90 transmissions one second control signal to this BMC 80; This BMC 80 sends the 3rd group and controls signal to this selection module 50; So that should select the information transfer channel between module 50 gatings the 3rd input end and the output terminal; At this moment; Directly select the 3rd input end input of module 50 from second data to be displayed of the system of this core logic control module 90 outputs, and export first interface 40 to from output terminal and show to import this display from this selection module 50 from this.Above-mentioned this Logic control module 90 sends first control signals, second control signal of redispatching earlier and is merely convenient explanation, and in fact, this Logic control module 90 also can send second control signal earlier.
Show at this display during first or second data to be displayed of this computer system; Can send the 3rd through the mode of Long-distance Control and control signal to this BMC 80, thereby make this display show the data to be displayed of this BMC so that this BMC 80 transmissions control signal to this selection module 50 for first group.
Accomplished at this system's display chip 60 during the data to be displayed of start-up routine and this BMC 80 of this display demonstration; Can send the 4th through the mode of Long-distance Control and control signal to this BMC 80, thereby make this display show first or second data to be displayed of this computer system so that this BMC 80 transmissions control signal to this selection module 50 for second group or the 3rd group.
Above-mentioned display control circuit 100 is optionally opened the information transfer channel between first input end, second input end or the 3rd input end and the output terminal of this selection module 50 according to first, second or the 3rd group of control signal of this BMC 80 outputs; So that this BMC 80 starts the back and this system's display chip 60 is accomplished before the start-up routine; The data to be displayed of this BMC 80 can be shown in this display through this BMC display chip 70 and this selection module 50; After this system's display chip 60 is accomplished start-up routine; First data to be displayed of system can be shown in this display through this system's display chip 60 and this selection module 50, and second data to be displayed of system also can select module 50 to be shown in this display through this.
The above is merely the preferable embodiment of the present invention, and any technician who is familiar with the present technique field is in the technical scope that the present invention discloses, and the variation that can expect easily or alternative all is encompassed within protection scope of the present invention.
Claims (7)
1. display control circuit comprises:
One system's display chip;
One BMC;
The one core logic control module that links to each other with this system's display chip and this BMC is used to judge whether this system's display chip accomplishes start-up routine, and accomplishes and send one first when starting and control signal to this BMC recognizing this system's display chip;
The one BMC display chip that links to each other with this BMC; And
One selects module, comprises the output terminal that second control end that first control end, that second input end that the first input end, that links to each other with this BMC display chip links to each other with this system's display chip, links to each other with first pin of one second interface of this BMC links to each other with second pin of this second interface and links to each other with second interface that is used to be connected a display; When this BMC starts and this system's display chip when not accomplishing start-up routine; This BMC exports first group and controls signal to this selection module with the first input end of this selection module of gating and the information transfer channel between the output terminal; Then the data to be displayed of this BMC through this selections module of this BMC display chip input first input end and export second this interface to from the output terminal of this selection module so that the data to be displayed of this BMC of this display demonstration; After this system's display chip is accomplished start-up routine; This core logic control module is sent first and is controlled signal to this BMC; Make this BMC export second group of control end that controls signal to this selection module with second input end of this selection module of gating and the information transfer channel between the output terminal, then first data to be displayed of computer system inputs to second input end of this selection module and exports this second interface to from the output terminal of this selection module through this system's display chip.
2. display control circuit as claimed in claim 1 is characterized in that: this core logic control module comprises the north and south bridge chip.
3. display control circuit as claimed in claim 1 is characterized in that: this second interface is the GPIO interface.
4. display control circuit as claimed in claim 1 is characterized in that: this selection module also comprises the 3rd input end that links to each other with this kernel control module; Show at this display during first data to be displayed of this computer system; This core logic control module is sent one second and is controlled signal to this BMC; Make this BMC send the 3rd group and control signal to this selection module; So that should select the information transfer channel between module gating the 3rd input end and the output terminal, thereby make second data to be displayed of this computer system directly export this second interface to through this selection module.
5. display control circuit as claimed in claim 4 is characterized in that: this selection module is an electronic switch chip, and this electronic switch chip comprises first to the 3rd input pin, first to second a control pin and the output pin.
6. display control circuit as claimed in claim 4; It is characterized in that: show at this display during first or second data to be displayed of this computer system; Send the 3rd through the mode of Long-distance Control and control signal to this BMC; Make this BMC send first group and control signal to this selection module, thereby make this display show the data to be displayed of this BMC.
7. display control circuit as claimed in claim 5; It is characterized in that: accomplished at this system's display chip during the data to be displayed of start-up routine and this BMC of this display demonstration; Send the 4th through the mode of Long-distance Control and control signal to this BMC; Control signal to this selection module so that this BMC sends second or the 3rd group, thereby make this display show first or second data to be displayed of this computer system.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101555329A CN102819411A (en) | 2011-06-10 | 2011-06-10 | Display control circuit |
| TW100120967A TW201250652A (en) | 2011-06-10 | 2011-06-16 | Display control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101555329A CN102819411A (en) | 2011-06-10 | 2011-06-10 | Display control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102819411A true CN102819411A (en) | 2012-12-12 |
Family
ID=47303542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101555329A Pending CN102819411A (en) | 2011-06-10 | 2011-06-10 | Display control circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102819411A (en) |
| TW (1) | TW201250652A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104407961A (en) * | 2014-10-28 | 2015-03-11 | 英业达科技有限公司 | Calculator system for displaying corresponding information of condition of host and display method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090132799A1 (en) * | 2007-11-20 | 2009-05-21 | Dell Products L. P. | Systems and Methods for Configuring Out-of-Band Bios Settings |
| CN101471037A (en) * | 2007-12-28 | 2009-07-01 | 英业达股份有限公司 | Service system |
| TW200935299A (en) * | 2008-02-05 | 2009-08-16 | Inventec Corp | Server system |
-
2011
- 2011-06-10 CN CN2011101555329A patent/CN102819411A/en active Pending
- 2011-06-16 TW TW100120967A patent/TW201250652A/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090132799A1 (en) * | 2007-11-20 | 2009-05-21 | Dell Products L. P. | Systems and Methods for Configuring Out-of-Band Bios Settings |
| CN101471037A (en) * | 2007-12-28 | 2009-07-01 | 英业达股份有限公司 | Service system |
| TW200935299A (en) * | 2008-02-05 | 2009-08-16 | Inventec Corp | Server system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104407961A (en) * | 2014-10-28 | 2015-03-11 | 英业达科技有限公司 | Calculator system for displaying corresponding information of condition of host and display method |
| CN104407961B (en) * | 2014-10-28 | 2017-12-26 | 英业达科技有限公司 | For showing the calculator system and display methods of host posture corresponding informance |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201250652A (en) | 2012-12-16 |
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Application publication date: 20121212 |