CN102810491A - Monitoring method for removing polycrystalline silicon false gate by gate-last process - Google Patents
Monitoring method for removing polycrystalline silicon false gate by gate-last process Download PDFInfo
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- CN102810491A CN102810491A CN201110149722XA CN201110149722A CN102810491A CN 102810491 A CN102810491 A CN 102810491A CN 201110149722X A CN201110149722X A CN 201110149722XA CN 201110149722 A CN201110149722 A CN 201110149722A CN 102810491 A CN102810491 A CN 102810491A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000012544 monitoring process Methods 0.000 title abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 87
- 238000012360 testing method Methods 0.000 claims abstract description 80
- 238000001739 density measurement Methods 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 20
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- 239000013078 crystal Substances 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 11
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000013401 experimental design Methods 0.000 claims description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
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- 238000005516 engineering process Methods 0.000 abstract description 20
- 238000005259 measurement Methods 0.000 abstract description 15
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- 238000001039 wet etching Methods 0.000 description 5
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Abstract
The invention provides a monitoring method for a process of removing a polycrystalline silicon dummy gate by a gate-last process, which comprises the following steps: forming a polysilicon dummy gate structure and a test structure on the surface of the wafer; determining a density measurement target and an error range of the test structure; and measuring the density of the test structure by using an XRR device, and judging whether the polycrystalline silicon dummy gate is completely removed. The technology can effectively monitor the thickness and the density of the multilayer film, has the advantages of rapid measurement and accurate result, is just in the initial stage of the application of the technology in the integrated circuit industry, and is a wafer process monitoring means with great development potential. According to the measuring method of the invention, whether the polysilicon dummy gate is completely removed can be rapidly, accurately and effectively monitored and judged, and meanwhile, the measuring method does not cause damage to the wafer.
Description
Technical field
The present invention relates to a kind of manufacturing approach of semiconductor device, more particularly, relate to the method for supervising that a kind of back grid technique removes the false grid processing procedure of polysilicon.
Background technology
With the successful Application of high K/ metal gate engineering on 45 nm technology node, make it become the indispensable key modules chemical industry of the following technology node of inferior 30 nanometers journey.Only adhere to that at present the Intel company of metal gate (gate last) route has obtained success on 45 nanometers and 32 nanometer volume productions behind the high K/.The industry giants such as Samsung, Taiwan Semiconductor Manufacturing Co., Infineon that follow IBM industry alliance in recent years closely also will before the emphasis of exploitation turn to gate last engineering by high K/ elder generation's metal gate (gate first).
In the Gate last engineering, after accomplishing ion at high temperature annealing, need dig up the polycrystalline grid, then be filled into metal gate electrode, flow process sees Fig. 1 for details.Like Figure 1A, form insulating barrier 2, polysilicon false grid 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5 on the substrate 1 successively.Like Figure 1B, remove polysilicon false grid 3, form gate openings 6, fill the metal gate electrode material then.Polycrystalline grid sidewall 4 is the side wall (spacer) of silica or silicon nitride material, and the insulating barrier 2 below the polycrystalline grid is the good high K of deposit or silica or silicon oxy-nitride material.At present, industrial quarters has three process routes to accomplish the removal work of the false grid of polycrystalline, is respectively dry etching, wet etching, and dry method-wet-mixed etching; See from experiment and results reported, be more prone to back 2 kinds of methods.
After the false grid 3 of polycrystalline are removed, need carry out effective monitoring means and judge whether polysilicon is got rid of fully, the residual of any polycrystalline all can be caused great negative effect to device electrical performance.This technology belongs to 32nm and following advanced technologies, after the false grid 3 of polycrystalline remove, how effectively processing procedure to be monitored, and does not see any report as yet.Method is to see that through scanning electron microscopy the false grid 3 of polycrystalline remove the cross section of back wafer the most intuitively, but this method has destructiveness to wafer, and feedback result is very slow, in the time of can't directly being used for volume production to the effective monitoring of processing procedure.Simultaneously, the monitoring of integrated circuit industry bound pair manufacturing process at present is most of, and what adopt is the optical measurement means, and with constantly the dwindling of technology node, device architecture becomes increasingly complex, and the film of lamination is more and more thinner, and the traditional optical method for measurement has run into very big challenge.For this reason, be badly in need of intuitively a kind of, to wafer undamaged quick and precisely effectively method for supervising judge that the false grid of polycrystalline remove whether thoroughly.
Summary of the invention
Therefore, the objective of the invention is to propose the method for supervising that a kind of back grid technique removes the false grid processing procedure of polysilicon, whether false grid thoroughly remove so that polysilicon is judged in effective monitoring quick and precisely, and simultaneously, this method for measurement can not bring damage to wafer.
The invention provides the method for supervising that a kind of back grid technique removes the false grid processing procedure of polysilicon, may further comprise the steps: form false grid structure of polysilicon and test structure at crystal column surface; Confirm test structure density measurement target and error range; Use the density of XRR device measuring test structure, judge whether the false grid of polysilicon remove fully.
The present invention also provides a kind of back grid technique to remove the method for supervising of the false grid processing procedure of polysilicon, may further comprise the steps: form false grid structure of polysilicon and test structure at crystal column surface; Confirm that thickness of insulating layer measures target and error range in the test structure; Use the thickness of XRR device measuring insulating barrier and polysilicon, judge whether polysilicon removes fully and/or over etching takes place.
Wherein, the false grid of test structure and polysilicon adopt same process to be produced in the same horizontal plane simultaneously.Wherein, test structure comprises insulating barrier, polysilicon, sidewall, the interlayer dielectric layer on the substrate.Wherein, test structure has predetermined pattern density, and this pattern density is defined as the ratio of polysilicon width and polysilicon distance.Wherein, the density range of test structure is 10%-100%.Wherein, the density range of test structure is 50%.
Wherein, test structure is positioned on the line of cut of the inner individual chips of wafer unit, and it is inner perhaps to be positioned at the individual chips unit.
Wherein, test structure is rectangle or square.Wherein, test structure is of a size of a kind of among 20 μ m * 20 μ m, 30 μ m * 30 μ m, the 50 μ m * 50 μ m.
Wherein, insulating barrier is high k material, silica or silicon oxynitride.
Wherein, combine the XRR means of testing, obtain polysilicon by test structure density and/or the thickness of insulating layer and the error range of the sample wafer of removing fully through experimental design (DOE).
Wherein,, then judge removal fully of polysilicon, need aftertreatment if test structure density and/or thickness of insulating layer exceed error range.
This patent has proposed monitoring route and the test structure after the false grid of two polycrystalline remove; Whether adopted the false grid of X ray reflection technology (XRR) monitoring polycrystalline to remove thoroughly; This technology can the effective monitoring plural layers thickness and density, have rapid measuring, the result is advantage accurately; This technology just has been in the starting stage in the application of integrated circuit industry circle, is a kind of wafer process monitoring means that development potentiality is arranged very much.According to method for measurement of the present invention, effective monitoring quick and precisely judges whether the false grid of polysilicon thoroughly remove, and this method for measurement can not bring damage to wafer simultaneously.
Purpose according to the invention, and in these other unlisted purposes, in the scope of the application's independent claims, be able to satisfy.Embodiments of the invention are limited in the independent claims, and concrete characteristic is limited in its dependent claims.
Description of drawings
Followingly specify technical scheme of the present invention with reference to accompanying drawing, wherein:
Fig. 1 has shown the back grid technique sketch map of prior art;
Fig. 2 has shown XRR measuring technique sketch map;
Fig. 3 has shown the shape and size sketch map of resolution chart; And
Fig. 4 has shown the structural representation of resolution chart.
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention, disclose and propose to adopt the XRR measurement technology that grid technique polysilicon false grid in back are removed to monitor, and provided corresponding test structure.It is pointed out that structure like the similar Reference numeral representation class.
The method for measurement that the present invention proposes based on X ray reflection technology (X-ray reflectivity is called for short XRR) solves above-mentioned technical problem.This technology just has been in the starting stage in the application of integrated circuit industry circle, is a kind of process monitoring means that development potentiality is arranged very much.Its basic principle is that X ray is reached sample surfaces at a certain angle, and X ray can reflect when after penetrating film, running into the layer of material interface; Obtain the thickness of the film of surveying through the phase difference that calculates incident X-rays and reflection X ray.The X ray that from film, reflects has carried thin-film information, and this technology is the thickness and the density of measuring complex plural layers effectively.Its outstanding strong penetrability characteristics of X ray make the measurement process not receive the restriction of metal and nonmetallic materials, and much lamination helps its modeling and measurement more more.It is fast that this method has measurement speed simultaneously; The result is advantage accurately, and its measurement process is seen sketch 2, launches X ray with a certain special angle to crystal column surface from x-ray source; On its symmetric position, X-ray detector is set, obtains thickness according to phase difference through the calculating control system that links to each other.
With reference to accompanying drawing 1, on substrate 1, form insulating barrier 2, polysilicon false grid 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5 successively, remove polysilicon false grid 3 then, form gate openings 6.Visible by Fig. 1, after the false grid 3 of polycrystalline remove, wafer when the quality of layer film (also be on the crystal column surface IDL5 and between each layer film quality sum of the folded sidewall of establishing 4, gate openings 6) will obviously reduce, density reduces thereupon; Therefore through monitoring, can judge whether the false grid of polycrystalline are removed clean fully to wafer fc-specific test FC density of texture; It is directly perceived to adopt this method measurement to have test result, to wafer not damaged and the high characteristics of efficiency of measurement, is fit to the false grid of polycrystalline and removes the effective monitoring of back to technology.
Particularly, the method that removes the false grid of polysilicon according to the back grid technique of one embodiment of the present of invention may further comprise the steps:
At first, form false grid structure of polysilicon and test structure at crystal column surface.As shown in Figure 1, crystal column surface is formed with the false grid structure of polysilicon, also promptly on substrate 1, forms insulating barrier 2, polysilicon false grid 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5 successively, removes polysilicon false grid 3 then, forms gate openings 6.Simultaneously, like Fig. 3, shown in Figure 4, crystal column surface through with form the identical technology of the false grid of polysilicon forms the polysilicon material in same horizontal plane test structure 7.Test structure 7 is shaped as for example rectangle, and instance can be put to the proof the square or rectangular structure, as long as its structure can form specific phase difference for the X ray reflection of special angle.For the square that embodiment lifted, size (long a multiply by wide b) includes but not limited to 20 μ m * 20 μ m, 30 μ m * 30 μ m, 50 μ m * 50 μ m etc., referring to Fig. 3.The figure of test structure 7 is band side wall polycrystalline grid, and unified with making technology, enlarged drawing is seen Fig. 4, also is that test structure 7 also comprises substrate 1, insulating barrier 2, gate lateral wall 4, IDL5.The pattern density of test structure 7 is defined as the ratio of width d between polycrystalline grid width c and the polycrystalline grid, i.e. c/d, and its density range 10%-100%, instance can put to the proof 50%; Pattern density for 50%, the concrete size of c is as the criterion with the grid width (gate CD) of actual product.Test structure 7 positions can be on the line of cut of the inner individual chips of wafer unit saving chip area, or inside, individual chips unit with the resolution chart between the different chips of personal settings so that adjust to different grid widths.
Secondly, confirm test structure density measurement target and error range.Can go up specifically created a plurality of resolution charts 7 at the wafer (also promptly being not used in the subsequent use wafer that cuts into chip product at last) of test usefulness earlier; Also can form a plurality of resolution charts 7 in the zones of different on a certain wafer; Through this experimental design (design of experimental; DOE) and adopt the XRR means of testing, the wafer of confirming a certain product type the false grid of polycrystalline remove clean back (can do destructive SEM or TEM test to print, choose the false grid 3 of those polysilicons by the wafer of removing fully as sample) the density of resolution chart 7; Also be standard pattern density, the thickness of the false grid 3 of polysilicon this moment should be 0.After measuring the data of multiple batches of wafer multi-disc, obtain the excursion of resolution chart 7 density.Measure target and error range according to The above results reasonable definition wafer sort density of texture; The density of test structure was 50% when for example DOE and XRR obtained that the false grid 3 of polysilicon are removed fully on the wafer of a certain product type; Its excursion is 5%, judges that then the false grid of polysilicon are removed fully and do not had the standard of over etching is that test structure 7 density are 50% ± 5%.Wherein, after the DOE experiment purpose finds the false grid of polycrystalline thoroughly to remove exactly, the excursion of wafer sort density of texture.
Then, the polysilicon of removing in false grid of polysilicon and the test structure is also dry.Can adopt the dry etching of carbon fluorine-based plasma etching to remove the polysilicon in false grid 3 of polysilicon and the test structure 7; Also can adopt etching liquid wet etchings such as KOH, TAMH to remove the false grid 3 of polysilicon, can also be the mixing etching of these dry method, wet etching.The flow of choose reasonable etching raw material or concentration, air pressure or the like parameter is controlled etching speed, makes polysilicon in false grid 3 of in preset time polysilicon and the test structure 7 basically by complete etching.Dry run can be to put into insulating box to toast, or uses inert gas such as nitrogen, argon gas to dry up.
Then, use XRR device measuring test structure 7 density, judge whether polysilicon removes fully.If the density of test structure 7 is (range of tolerable variance is confirmed by the 2nd step) in error range, erosion removal is clean can to think the false grid 3 of polycrystalline.If the density of many test structures 7 not in error range, thinks then that the false grid 3 of polycrystalline remove totally fully, need to handle again again, also be about to this batch sample and send processing line back to and carry out secondarily etched.
Above embodiments of the invention obtain the variable density scope after the false grid of polysilicon are removed fully through experimental design, pass through the test structure density of X ray reflection testing of equipment actual product then, thereby judge whether the false grid 3 of polysilicon are removed fully.This test and back grid etching are removed the method for the false grid of polysilicon, have avoided all adopting for mass product the destructive testing of SEM or TEM, have improved testing efficiency and have provided cost savings.
Embodiment 2
Similar with embodiment 1, the method that removes the false grid of polysilicon according to the back grid technique of an alternative embodiment of the invention may further comprise the steps:
At first, form false grid structure of polysilicon and test structure at crystal column surface.As shown in Figure 1, crystal column surface is formed with the false grid structure of polysilicon, also promptly on substrate 1, forms insulating barrier 2, polysilicon false grid 3, gate lateral wall 4, interlayer dielectric layer (IDL) 5 successively, removes polysilicon false grid 3 then, forms gate openings 6.Simultaneously, like Fig. 3, shown in Figure 4, crystal column surface through with form the identical technology of the false grid of polysilicon forms the polysilicon material in same horizontal plane test structure 7.Test structure 7 is shaped as for example rectangle, and instance can be put to the proof the square or rectangular structure, as long as its structure can form specific phase difference for the X ray reflection of special angle.For the square that embodiment lifted, size (long a multiply by wide b) includes but not limited to 20 μ m * 20 μ m, 30 μ m * 30m, 50 μ m * 50 μ m etc., referring to Fig. 3.The figure of test structure 7 is band side wall polycrystalline grid, and unified with making technology, enlarged drawing is seen Fig. 4, also is that test structure 7 also comprises substrate 1, insulating barrier 2, gate lateral wall 4, IDL5.The pattern density of test structure 7 is defined as the ratio of width d between polycrystalline grid width c and the polycrystalline grid (also being polysilicon gate spacing d), i.e. c/d, and its density range 10%-100%, instance can put to the proof 50%; Pattern density for 50%, the concrete size of c is as the criterion with the grid width (gate CD) of actual product.Test structure 7 positions can be on the line of cut of the inner individual chips of wafer unit saving chip area, or inside, individual chips unit with the resolution chart between the different chips of personal settings so that adjust to different grid widths.
Secondly, confirm that thickness of insulating layer measures target and error range.Can go up specifically created a plurality of resolution charts 7 at the wafer (also promptly being not used in the subsequent use wafer that cuts into chip product at last) of test usefulness earlier; Also can form a plurality of resolution charts 7 in the zones of different on a certain wafer; Through this experimental design (design of experimental; DOE) and adopt the XRR means of testing, the wafer of confirming a certain product type the false grid of polycrystalline remove clean back (can do destructive SEM or TEM test to print, choose the false grid 3 of those polysilicons by the wafer of removing fully as sample) insulating barrier 2 thickness of resolution chart 7 bottoms; Also be the standard, insulated layer thickness, the thickness of the false grid 3 of polysilicon this moment should be 0.After measuring the data of multiple batches of wafer multi-disc, obtain the scope of insulating barrier 2 varied in thickness.Measure target and error range according to The above results reasonable definition wafer thickness of insulating layer; Insulating barrier 2 thickness were 15nm when for example DOE and XRR obtained that the false grid 3 of polysilicon are removed fully on the wafer of a certain product type; Its excursion is 1nm, judges that then the false grid of polysilicon are removed fully and do not had the standard of over etching is that insulating barrier 2 thickness are 15 ± 1nm on the wafer.
Then, the polysilicon of removing in false grid of polysilicon and the test structure is also dry.Can adopt the dry etching of carbon fluorine-based plasma etching to remove the polysilicon in false grid 3 of polysilicon and the test structure 7; Also can adopt etching liquid wet etchings such as KOH, TAMH to remove the false grid 3 of polysilicon, can also be the mixing etching of these dry method, wet etching.The flow of choose reasonable etching raw material or concentration, air pressure or the like parameter is controlled etching speed, makes polysilicon in false grid 3 of in preset time polysilicon and the test structure 7 basically by complete etching.
Then, use insulating barrier 2 and polysilicon 3 thickness in the XRR device measuring test structure 7, judge whether polysilicon removes fully and/or over etching takes place.If the thickness of polysilicon 3 is 0, and insulating barrier 2 thickness (range of tolerable variance is confirmed by the 2nd step) in error range, erosion removal is clean can to think the false grid 3 of polycrystalline, and does not have excessive erosion to take place.If polysilicon 3 thickness are 0, insulating barrier 2 thickness surpass error range, then think the generation over etching, and this batch products is scrapped.As crossing polysilicon 3 thickness is not 0, even measure insulating barrier 2 thickness in error range, thinks that the false grid 3 of polycrystalline remove totally fully yet, needs to handle again again, is about to this batch sample yet and sends processing line back to and carry out secondarily etched.
Test and lithographic method according to above second embodiment of the invention; Owing to measure insulating barrier and polysilicon thickness simultaneously; Not only can convenient and swiftly judge whether remove polysilicon gate fully accurately; Therefore can also judge simultaneously whether over etching takes place, test convenient efficiently that product yield that obtains and reliability have significantly and promote.
According to measurement of the present invention and lithographic method, avoided all adopting the destructive testing of SEM or TEM for mass product, improved testing efficiency and provided cost savings.Therefore in addition, can also judge simultaneously whether over etching takes place, test convenient efficiently that product yield that obtains and reliability have significantly and promote.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and device architecture is made various suitable changes and equivalents.In addition, can make by disclosed instruction and manyly possibly be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, the object of the invention does not lie in and is limited to as being used to realize preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacturing approach thereof will comprise all embodiment that fall in the scope of the invention.
Claims (13)
1. grid technique removes the method for supervising of the false grid processing procedure of polysilicon after one kind, may further comprise the steps:
Form false grid structure of polysilicon and test structure at crystal column surface;
Confirm test structure density measurement target and error range;
Use the density of XRR device measuring test structure, judge whether the false grid of polysilicon remove fully.
2. grid technique removes the method for supervising of the false grid processing procedure of polysilicon after one kind, may further comprise the steps:
Form false grid structure of polysilicon and test structure at crystal column surface;
Confirm that thickness of insulating layer measures target and error range in the test structure; And
Use the thickness of XRR device measuring insulating barrier and polysilicon, judge whether polysilicon removes fully and/or over etching takes place.
3. like the method for claim 1 or 2, wherein, the false grid of test structure and polysilicon adopt same process to be produced in the same horizontal plane simultaneously.
4. like the method for claim 1 or 2, wherein, test structure comprises insulating barrier, polysilicon, sidewall, the interlayer dielectric layer on the substrate.
5. like the method for claim 1 or 2, wherein, test structure has predetermined pattern density, and this pattern density is defined as the ratio of polysilicon width and polysilicon distance.
6. like the method for claim 1 or 2, wherein, test structure is positioned on the line of cut of the inner individual chips of wafer unit, and it is inner perhaps to be positioned at the individual chips unit.
7. like the method for claim 1 or 2, wherein, test structure is rectangle or square.
8. method as claimed in claim 7, wherein, test structure is of a size of a kind of among 20 μ m * 20 μ m, 30 μ m * 30 μ m, the 50 μ m * 50 μ m.
9. like the method for claim 1 or 2, wherein, the density range of test structure is 10%-100%.
10. method as claimed in claim 9, wherein, the density range of test structure is 50%.
11. method as claimed in claim 2, wherein, insulating barrier is high k material, silica or silicon oxynitride.
12. like the method for claim 1 or 2, wherein, combine the XRR means of testing, obtain polysilicon by test structure density and/or the thickness of insulating layer and the error range of the sample wafer of removing fully through experimental design (DOE).
13. like the method for claim 1 or 2, wherein,, then judge removal fully of polysilicon, need aftertreatment if test structure density and/or thickness of insulating layer exceed error range.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105347296A (en) * | 2014-08-19 | 2016-02-24 | 中国科学院微电子研究所 | Monitoring method of MEMS transverse etching process |
| CN105448759A (en) * | 2014-08-19 | 2016-03-30 | 中国科学院微电子研究所 | Method for monitoring source-drain trench process |
| CN105448758A (en) * | 2014-08-19 | 2016-03-30 | 中国科学院微电子研究所 | Method for monitoring channel etching process |
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| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| US6713753B1 (en) * | 2001-07-03 | 2004-03-30 | Nanometrics Incorporated | Combination of normal and oblique incidence polarimetry for the characterization of gratings |
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| CN105347296A (en) * | 2014-08-19 | 2016-02-24 | 中国科学院微电子研究所 | Monitoring method of MEMS transverse etching process |
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