CN102790476A - Dynamic balance analysis device - Google Patents
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- CN102790476A CN102790476A CN201110127722XA CN201110127722A CN102790476A CN 102790476 A CN102790476 A CN 102790476A CN 201110127722X A CN201110127722X A CN 201110127722XA CN 201110127722 A CN201110127722 A CN 201110127722A CN 102790476 A CN102790476 A CN 102790476A
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Abstract
The invention discloses a dynamic balance analysis device. A vibration signal is generated by externally input unbalanced rotation of a motor, and then processed by a front signal processing unit so as to be sent to an FIFO (first in first out) connected with the front signal processing unit; an FFT (fast fourier transform) processor is connected with the FIFO, so that the processed intermediate data and initial data are stored in a double-port RAM (random access memory) storage unit connected with the FFT processor; a data processing unit is connected with the double-port RAM storage unit, so that output compensation mass and relative position are acquired by calculation and then are sent to a display unit connected with the data processing unit for displaying; a control unit is respectively connected with the front signal processing unit, the FFT processor, the double-port RAM storage unit and the data processing unit for reading address, writing address, enabling signals and performing startup control for each relevant module. The device uses the FFT real-time analysis technology to greatly improve the system solution and analysis speed, and is suitable for extensively popularizing in application occasions such as dynamic balance detection, vibration analysis and compensation.
Description
Technical field
The present invention relates to a kind of dynamic balance analysis device, relate in particular to a kind of portable dynamic balance detecting device analysis of vibration measurement such as various main shafts, large-scale turntables.
Background technology
Comprising a large amount of parts that rotate in the conventional machinery, for example various power transmission shafts, main shaft, turntable and motor etc. are referred to as revolving body.The pressure that bearing is produced is the same when not rotating revolving body when rotation in ideal conditions, and such revolving body is the revolving body of balance.But the various revolving bodies in the engineering because the error that produces in the inhomogeneous or blank defective of material, processing and the assembling, even just have multiple factor such as asymmetrical geometry during design; Make revolving body when rotated; The centrifugal intertia force that each small particle produces on it can not be cancelled out each other, and centrifugal intertia force affacts on machinery and the basis thereof through bearing, causes vibration; The amplitude of vibration is with relevant with the rigidity of effective mass, effective radius and the supporter of the unbalanced point of the angular speed of object, object; Produced noise, quickened bearing wear, operation shakiness etc.; Have a strong impact on the precision of useful life, fail safe and the equipment of equipment, can damage incidents when serious.For this reason, must carry out equilibrium analysis and compensation, make its balance accuracy grade that reaches permission, or the mechanical oscillation amplitude of generation is fallen in allowed limits revolving body.
The digitlization of homemade dynamic balancing detection and vibration analysis equipment, intellectuality, integrated still very low; Along with people's is to more and more widely deep understanding of the application of dynamic balancing detection and vibration analysis equipment and increasing demand; The advanced technology of learning overseas; Developing intellectual resource dynamic balancing detection and vibration analysis special chip energetically; Catch up with advanced world levels, oneself becomes the direction and the inexorable trend of domestic dynamic balance analysis equipment development to greatly develop dynamic balancing detection and the application of vibration analysis special chip in every field.
In addition, on practical applications, the operational environment of most dynamic-balance measuring systems is more abominable, has a lot of other equipment on every side, and electromagnetic interference and mechanical disturbance possibly exist simultaneously, so higher to the requirements such as anti-interference of measuring system.So the raising level of integrated system reduces system complexity, improve system's operational capability, imperative to the transformation of existing test macro.The spot dynamic balance checkout equipment that some external manufacturers provide generally all adopts the method for acceleration transducer and speed probe; So not only cost is high; And in some occasion inconvenient operation, so a kind of characteristic according to actual machine equipment, and develop a kind of being suitable in Application in NC System; Carrying out the detection system of real-time dynamic balancing monitoring, is very necessary.
Summary of the invention
The present invention is directed to the proposition of above problem; Reflect according to mechanical body compound often characteristic when moving and develop a kind of utilization; Promptly mechanically all vibrations all will be on the characteristics basis of a relation that intercouples; Through adopting fast Fourier transform (FFT) accurately to purify, thereby needing to obtain the amplitude of certain characteristic frequency of analyzing and the dynamic balance analysis device that phase place is carried out equilibrium analysis to characteristic frequency.The technological means that the present invention adopts is following:
A kind of dynamic balance analysis device comprises the front end signal processing unit, and being used for the analog signals that collects is that the uneven rotation of motor causes vibration signal to convert digital quantity to;
It is characterized in that also comprising:
FIFO is used for causing the digital quantity of vibration signal to cushion to the outside uneven rotation of input motor;
Control unit is used to produce enabling signal and the control signal of reading address, write address, enable signal and each correlation module;
The two-port RAM storage element is used for the initial data of outside input is carried out buffer memory, and is used for temporary through the intermediate data behind the butterfly computation;
Display unit, the vibration information that is used for the data processing unit that the data processing unit sends is sent and the data of compensated information show;
Fft processor utilizes Fourier transform to causing the frequency of vibration signal to purify because the motor imbalance is rotated, and the frequency inverted that motor speed is corresponding becomes the uneven rotation of revolving body to cause the amplitude and the phase place of vibration performance frequency;
Data processing unit is used for the complex domain data after the FFT processing are asked computing of mould value and phase calculation, the dynamic balancing vibration data is analyzed the quality and the relative position of output compensation through the mould value of vibration and the relation of eccentric point quality;
The uneven rotation of the motor of said outside input causes vibration signal after the front end signal processing unit processes, to send among the connected FIFO; Said fft processor is connected with FIFO, in that uneven rotation causes that storage is in its two-port RAM storage element that is connected with initial data with the intermediate data of handling in amplitude that vibration signal carries out frequency and the phase transition process to motor; Said data processing unit is connected with the two-port RAM memory cell, is sent on its display unit that is connected behind the quality of obtaining output compensation through calculating and the relative position to show; Said control unit is connected with front end signal processing unit, fft processor, two-port RAM memory cell and data processing unit respectively and is used to read the start-up control of address, write address, enable signal and each correlation module.
Said fft processor comprises address control module, butterfly processing element, twiddle factor table memory cell and inverted order module;
Said address control module is used to produce the read/write address that enable signal, twiddle factor table are searched address and two-port RAM storage element, and the sequential of each unit is controlled;
Said butterfly processing element is used for causing vibration signal to carry out butterfly computation to the uneven rotation of motor of storage two-port RAM storage element;
Said twiddle factor table memory cell; Be used to store the required twiddle factor of butterfly processing element
; Wherein N is a sampling number, and P is the twiddle factor index;
Said inverted order module is used for that the operational data that butterfly processing element is accomplished is carried out inverted sequence and converts positive sequence into, realizes that the frequency spectrum normal sequence outputs in the data processing unit;
Said address control module is connected with the two-port RAM storage element; Be written to the data among the FIFO that is connected with fft processor in the two-port RAM storage element; Said butterfly processing element is connected with twiddle factor table memory cell, address control module and two-port RAM storage element respectively, causes vibration signal to carry out butterfly computation to the uneven rotation of motor that deposits in the two-port RAM storage element; Said address control module is connected with twiddle factor table memory cell; Said two-port RAM storage element is connected with the inverted order module.
The above-mentioned module of respectively forming all is integrated in the on-site programmable gate array FPGA.
This device adopts FFT real-time analysis technology, has greatly improved systemic resolution and analysis speed.Operating rate is fast, and integrated level is high, the sampled point of time-domain signal is carried out fft analysis can reach real-time operation fully, and this is the most important advantage of numerical analysis device.Simultaneously can be applied in the digital control system testee carried out the real-time and dynamic on-line monitoring, help improving the precision of measuring and calculating amount of unbalance, reduce mechanical oscillation, the prolonged mechanical life-span.It can be applied in the portable dynamic balancing checkout equipment to analysis of vibration measurement such as various main shafts, large-scale turntables, and what can also be applied to other needs dynamic balancing detection and application scenarios such as vibration analysis, compensation.The portability that around this principle combines modern electronic product, low-power consumption, low cost, high-performance and characteristic such as highly integrated can be made special chip with this dynamic balancing detection and vibration analysis device.This chip has not only been broken traditional C PU and has been relied on system clock serial executive mode; The a large amount of parallel processing technique and pile line operation modes of hardware used are come optimized Algorithm; DSP and MCU compared with techniques data processing speed are faster with adopting; Resolution, precision are higher, and peripheral circuit is simpler, improves the entire system performance greatly.Satisfy high algorithm process of real-time and control, make the data operation ability stronger, circuit designer just can be accomplished the input of circuit, plant equipment dynamic balancing detection and vibration analysis in a short period of time.When peripheral circuit is done a little change, just can realize different dynamic balancing detections and vibration analysis function with this special chip, so more can show the advantage of the special chip of dynamic balancing detection and vibration analysis.Because it is simple in structure, be convenient to produce and highly versatile, and cost is very cheap is suitable for extensive popularization.
Description of drawings
Fig. 1 is the structured flowchart of the embodiment of device according to the invention;
Fig. 2 is the structured flowchart of fft processor among the device embodiment according to the invention;
Fig. 3 is a butterfly processing element flow graph among the device embodiment according to the invention;
Fig. 4 is an embodiment of the invention flow chart.
Embodiment
This dynamic balance analysis device as shown in Figure 1 comprises the front end signal processing unit, is mainly used in gathering and change (the vibrative signal of the uneven rotation of external representation because the motor imbalance is rotated the vibration signal that produces; The frequency that comprises vibration; Information such as amplitude and phase place), carry out operations such as AD sampling, to reach adjustment signal input range; Convert the analog quantity of vibration signal to digital quantity, guarantee that the FFT signal processing has enough bandwidth.
FIFO is mainly as the buffer cell (promptly causing vibration signal to cushion to the outside uneven rotation of input motor) of outer input data; The data of outside high-speed AD acquisition are temporary in FIFO, and FIFO is completely afterwards disposable by the time delivers to data in the two-port RAM storage element, is used for fft processor and calculates; Control unit: mainly as the controller of each unit co-ordination.Control unit is responsible for producing the enabling signal of reading address, write address, enable signal and each correlation module.
The two-port RAM storage element is used for the initial data of outside input is carried out buffer memory, and is used for keeping in the intermediate data through behind the butterfly computation, and the inputoutput data of each butterfly row operation all will pass through the read-write operation of RAM.Therefore, the frequent read-write operation speed of RAM is bigger to the processing speed influence of FFT.In order to accelerate the arithmetic speed of FFT, need the structure two-port RAM to come the throughput of speeding up data transmission; Present embodiment adopts two two-port RAM memory cell (that is: dual port RAM 1 and dual port RAM 2).Display unit, the vibration information that is used for the data processing unit that the data processing unit sends is sent and the data of compensated information show.
Fft processor utilizes Fourier transform that the time-domain signal that high-speed a/d collects is converted into frequency-region signal; Fft processor combines the requirement of FFT real time implementation and chip design flexibility; Realize distributing rationally of parallel algorithm and hardware configuration; Improved the FFT processing speed, high-speed, the high-resolution that has satisfied that analysis of vibration signal handles, the requirement of high reliability.FFT can accurately be purified to vibration frequency, and can obtain causing the amplitude and the phase place of vibration performance frequency because the revolving body imbalance is revolved (being that the uneven rotation of motor causes vibration signal) transduction.
Data processing unit is used for the complex domain data after the FFT processing are asked computing of mould value and phase calculation, and according under the certain situation of rotating speed, the mould value and the eccentric point quality of vibration are linearly proportional.The proportionality coefficient of the mould value through asking initializes quality and vibration signal; Under the constant situation of rotating speed; Through the mould value and the phase place of measuring vibrations signal once more; Utilize this proportionality coefficient need to confirm the quality of compensation (adding or reduction) M and relative position; Comprise current rotating speed with output, (promptly obtain the amplitude-frequency characteristic and the phase characteristic of vibration signal, the amplitude of fundamental frequency signal and phase place reflect the relative quality of eccentric point and the relation of relative position and vibration frequency for quality that need compensate (adding or reduction) and relative position result.)。
Fft processor as shown in Figure 2 comprises address control module, butterfly processing element, twiddle factor table memory cell and inverted order module:
The address control module is used for producing enable signal, and plays the SECO effect of each unit, and produces correct twiddle factor table and search the address, and the read/write address of RAM, and the sequential of each module is control effectively, and guarantees system's operate as normal.
Said butterfly processing element; Be used for causing vibration signal to carry out butterfly computation to the uneven rotation of motor of storage two-port RAM storage element, said butterfly computation can be divided into DIT-FFT (decimation in time) and DIF-FFT (decimation in frequency) algorithm according to the difference of the mode of extraction.Formation difference according to butterfly computation can be divided into base 2, base 4, base 8 and any factor (2n, n are the integer greater than 1), and split-radix etc.The course of work for clearer expression butterfly processing element; With base-2 loop structures is that example describes that (this also is the optimum instance of device according to the invention; Compare with pipeline organization, arithmetic speed descends, but because it uses a butterfly processor; So the resource that takies is minimum, the arithmetic speed of pipeline organization is the log of this loop structure
2N doubly.), model is as shown in Figure 3: among base-2FFT, N is a sampling number, N=2
M, total M level computing, every grade has N/2 2 FFT butterfly computations, so total (N/2) log of N point FFT
2N butterfly computation.1 base-2 butterfly computation is added with arithmetic element by 1 multiple multiplication unit and 2 and forms.Its formula is following:
Concrete operation process and parametric representation are:
2;, N/2-1; If sequence x (n) length is N, wherein N is the FFT sampling number; Owing to need 256 twiddle factors altogether in 512 each levels of FFT; And putting in order of twiddle factor all is regular governed in each grade; As: in the signal flow graph of DIF-FFT; The twiddle factor of the first order be the partial twiddle factor of
for the twiddle factor of the 9th grade of the twiddle factor of
third level for
visible for
; The twiddle factor of each grade can extract according to different intervals from 256 twiddle factors of the first order, so only need 256 twiddle factors of the storage first order to get final product among the ROM.When calculating is not at the same level, only need adopt corresponding addressing method to get final product according to arrangement regulation, therefore, the address wire width of ROM is also only with 8.
Said twiddle factor table memory cell; The twiddle factor table comes down to a ROM; Be used for storing the needed twiddle factor of each grade FFT computing; In the N point FFT computing flow graph, every grade all has N/2 butterfly, and each butterfly all will multiply by the factor
is called twiddle factor; Wherein N is a sampling number, and p is called the index of twiddle factor.But twiddle factor at different levels and endless form are all different.In order to write calculation procedure, should find out the relation of twiddle factor
and computing progression earlier.In order to improve arithmetic speed; Twiddle factor
is made into the ROM table, is used for storing the needed twiddle factor of each grade FFT computing.
Said inverted order module is used for that the operational data that butterfly processing element is accomplished is carried out inverted sequence and converts positive sequence into, realizes that the frequency spectrum normal sequence outputs in the data processing unit; Because the FFT of DIT form input data x (n) address is in proper order, but owing to strange to x (n) work in calculating process, idol are separated, causing the dateout address no longer is original order.If data address is by the n bit representation, the rule of bit reversal is: n-1 position and the 0th exchange, and n-2 position and the 1st exchange, n-3 position and the 2nd exchange ..., the rest may be inferred just can convert inverted sequence into positive sequence.
Idiographic flow is as shown in Figure 4: at first; Wait for inputted vibration analysis enabling signal; The vibratory output (promptly causing vibration signal to cushion to the outside uneven rotation of input motor) that carries out then being caused by the uneven rotation of rotating object converts analog quantity to digital quantity through front end signal processing unit processes (being the AD sampling), is input among the FIFO (First Input First Output); Carry out metadata cache, whether be ready to control the unlatching of fft processor through judgment data.Data can convert time-domain signal to frequency-region signal through after the fft processor.Send startup fft processor signal by controller; Start FFT home address control module; At first produce the RAM write address; Be written to the data among the FIFO in the dual port RAM 1; The address of reading that produces RAM1 is then sent into butterfly processing element to the data that first order butterfly computation needs; Produce the address of reading of twiddle factor table simultaneously,
is sent to butterfly processing element the required twiddle factor of first order butterfly computation, produces the enabling signal of butterfly processing element simultaneously.After first order butterfly computation finished, address control unit produced the write address of RAM2, is deposited into data among the RAM2.Advanced log
2Behind the butterfly computation of N (wherein N is the FFT sampling number) level, accomplish a FFT computing.Exporting after the data processing, return simultaneously and wait for that vibration analysis begins next time.Data among the buffer RAM2 are exactly the data of the plural form after the FFT computing, through it is asked the computing of mould value and asks bit arithmetic mutually, just can obtain amplitude-frequency characteristic and phase-frequency characteristic behind the FFT.Amplitude-frequency characteristic has been reacted the relative quality of eccentric point and the relation of vibration frequency, and phase-frequency characteristic has been reacted the relative position of eccentric point and the relation of vibration frequency.
Dynamic balancing detection and vibration analysis device can an integrated chip in (FPGA for example.) also special chip can be set, can adopt Miltilayer wiring structure at chip internal, lower core voltage; Abundanter IO pin, capacity can reach about 20k logical block (LES), built-in embedded RAM resource; Inner integrated a plurality of digital phase-locked loops; The hardware multiplier of a plurality of embeddings, in conjunction with building of embedded soft CPU of this chip internal and inner peripheral hardware thereof, all these make this chip demonstrate own distinctive advantage in dynamic balancing detection and vibration analysis field.
The above; Be merely the preferable embodiment of the present invention; But protection scope of the present invention is not limited thereto; Any technical staff who is familiar with the present technique field is equal to replacement or change according to technical scheme of the present invention and inventive concept thereof in the technical scope that the present invention discloses, all should be encompassed within protection scope of the present invention.
Claims (3)
1. a dynamic balance analysis device comprises the front end signal processing unit, and being used for the analog signals that collects is that the uneven rotation of motor causes vibration signal to convert digital quantity to;
It is characterized in that also comprising:
FIFO is used for causing the digital quantity of vibration signal to cushion to the outside uneven rotation of input motor;
Control unit is used to produce enabling signal and the control signal of reading address, write address, enable signal and each correlation module;
The two-port RAM storage element is used for the initial data of outside input is carried out buffer memory, and is used for temporary through the intermediate data behind the butterfly computation;
Display unit, the vibration information that is used for the data processing unit that the data processing unit sends is sent and the data of compensated information show;
Fft processor utilizes Fourier transform to causing the frequency of vibration signal to purify because the motor imbalance is rotated, and the frequency inverted that motor speed is corresponding becomes the uneven rotation of revolving body to cause the amplitude and the phase place of vibration performance frequency;
Data processing unit is used for the complex domain data after the FFT processing are asked computing of mould value and phase calculation, the dynamic balancing vibration data is analyzed the quality and the relative position of output compensation through the mould value of vibration and the relation of eccentric point quality;
The uneven rotation of the motor of said outside input causes vibration signal after the front end signal processing unit processes, to send among the connected FIFO; Said fft processor is connected with FIFO, in that uneven rotation causes that storage is in its two-port RAM storage element that is connected with initial data with the intermediate data of handling in amplitude that vibration signal carries out frequency and the phase transition process to motor; Said data processing unit is connected with the two-port RAM memory cell, is sent on its display unit that is connected behind the quality of obtaining output compensation through calculating and the relative position to show; Said control unit is connected with front end signal processing unit, fft processor, two-port RAM memory cell and data processing unit respectively and is used to read the start-up control of address, write address, enable signal and each correlation module.
2. a kind of dynamic balance analysis device according to claim 1 is characterized in that said fft processor comprises address control module, butterfly processing element, twiddle factor table memory cell and inverted order module;
Said address control module is used to produce the read/write address that enable signal, twiddle factor table are searched address and two-port RAM storage element, and the sequential of each unit is controlled;
Said butterfly processing element is used for causing vibration signal to carry out butterfly computation to the uneven rotation of motor of storage two-port RAM storage element;
Said twiddle factor table memory cell; Be used to store the required twiddle factor of butterfly processing element
; Wherein N is a sampling number, and P is the twiddle factor index;
Said inverted order module is used for that the operational data that butterfly processing element is accomplished is carried out inverted sequence and converts positive sequence into, realizes that the frequency spectrum normal sequence outputs in the data processing unit;
Said address control module is connected with the two-port RAM storage element; Be written to the data among the FIFO that is connected with fft processor in the two-port RAM storage element; Said butterfly processing element is connected with twiddle factor table memory cell, address control module and two-port RAM storage element respectively, causes vibration signal to carry out butterfly computation to the uneven rotation of motor that deposits in the two-port RAM storage element; Said address control module is connected with twiddle factor table memory cell; Said two-port RAM storage element is connected with the inverted order module.
3. a kind of dynamic balance analysis device according to claim 1 and 2 is characterized in that the above-mentioned module of respectively forming all is integrated in the on-site programmable gate array FPGA.
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| CN104483859B (en) * | 2014-11-21 | 2017-02-01 | 杭州电子科技大学 | Multi-CPU (central processing unit) balance correcting machine controller |
| CN114661170A (en) * | 2022-04-29 | 2022-06-24 | 北京烽火万家科技有限公司 | Non-invasive special brain-computer interface device |
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| CN101363766A (en) * | 2008-09-09 | 2009-02-11 | 上海师范大学 | Method for implementing whole cycle sampling for dynamic balancing measurement |
| CN101429877A (en) * | 2008-11-28 | 2009-05-13 | 华北电力大学 | Real-time diagnosis method for angle misalignment fault of steam-electric generating set coupling |
| CN101451898A (en) * | 2009-01-13 | 2009-06-10 | 华北电力大学 | Steam-electric generating set rotor thermal bending unbalance fault real time diagnostic method |
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| CN101363766A (en) * | 2008-09-09 | 2009-02-11 | 上海师范大学 | Method for implementing whole cycle sampling for dynamic balancing measurement |
| CN101429877A (en) * | 2008-11-28 | 2009-05-13 | 华北电力大学 | Real-time diagnosis method for angle misalignment fault of steam-electric generating set coupling |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104483859B (en) * | 2014-11-21 | 2017-02-01 | 杭州电子科技大学 | Multi-CPU (central processing unit) balance correcting machine controller |
| CN114661170A (en) * | 2022-04-29 | 2022-06-24 | 北京烽火万家科技有限公司 | Non-invasive special brain-computer interface device |
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