CN102790008A - Method for forming contact plug - Google Patents
Method for forming contact plug Download PDFInfo
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- CN102790008A CN102790008A CN2011101263477A CN201110126347A CN102790008A CN 102790008 A CN102790008 A CN 102790008A CN 2011101263477 A CN2011101263477 A CN 2011101263477A CN 201110126347 A CN201110126347 A CN 201110126347A CN 102790008 A CN102790008 A CN 102790008A
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Abstract
Disclosed is a method for forming a contact plug. The method comprises that a substrate is provided, the substrate is provided with a source region and a drain region, a gate structure is formed on the substrate, the source region and the drain region are located at positions of the two sides of the gate structure, the gate structure comprises a side wall and a grid, a metal silicide is formed on the source region and the drain region of the substrate, a conducting layer of a predetermined thickness is formed on the metal silicide through an electroless plating method, an interlayer dielectric layer is formed, the conducting layer and the gate structure are covered, a contact hole is formed in the interlayer dielectric layer, the conducting layer is exposed, a conducting material is filled in the contact hole and the contact plug is formed. By the aid of the technical scheme, the problem of communication caused by gaps of two adjacent contact plugs is solved. Besides, the problems that contact resistance is increased due to the loss in metal silicide etching and the contact hole is not opened completely are solved or reduced at least.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the method that forms the contact plug.
Background technology
Fig. 1～Fig. 4 is the cross-sectional view that forms the method for contact plug in the prior art; With reference to figure 1～Fig. 4; The method of the formation contact plug of prior art is: with reference to figure 1; Semiconductor substrate 10 is provided, is formed with source region, drain region and channel region (not shown) in this Semiconductor substrate 10, on this Semiconductor substrate 10, form the grid structure that comprises gate dielectric layer 11, grid 12 and side wall 13.After forming grid structure, usually can be, the surface of drain region and polysilicon gate forms metal silicide (Silicide) 14 in the source region, nickle silicide (NiSi) for example is to reduce the contact resistance of contact plug and source region, drain region and grid.With reference to figure 2, form interlayer dielectric layer 15, cover said grid structure, Semiconductor substrate 10 and metal silicide 14.With reference to figure 3, utilize photoetching process on interlayer dielectric layer 15, to form patterned photoresist layer, define the position of contact hole 17, be that mask etching interlayer dielectric layer 15 forms contact hole 17 with patterned photoresist layer then, expose metal silicide 14.With reference to figure 4, the filled conductive material forms contact plug 18 in contact hole 17, is electrically connected with source region, drain region through metal silicide 14.
Along with development of semiconductor, the characteristic size of device is more and more littler, and the integrated level of device is increasingly high, and the depth-to-width ratio of contact hole 17 is increasing, and the depth-to-width ratio in the space between the neighboring gates structure is also increasing.Because the depth-to-width ratio in the space between the neighboring gates structure is increasing, can cause space between the neighboring gates structure to fill the filling capacity variation of interlayer dielectric layer 15, for the filling capacity that can make interlayer dielectric layer 15 good; Available technology adopting high-aspect-ratio technology; (HARP, high aspectratio process) technology is carried out the deposition of interlayer dielectric layer 15, though the filling capacity for the space with big depth-to-width ratio of HARP technology is better; But; When deposition interlayer dielectric layer 15,, still can produce space 16 in the interlayer dielectric layer 15 between the neighboring gates structure with reference to figure 2; When space 16 is between adjacent contact plug, can cause adjacent plug conducting to influence the performance of device; When space 16 is in the etching scope of interlayer dielectric layer 15; When promptly being in the zone at contact hole 17 place, when etching into the position at 16 places, space, will carry out etching to the interlayer dielectric layer of 16 belows, space; Etch period when the position of having reduced 16 places, space is interlayer dielectric layer; And total etch period is certain, and the over etching that this will cause the metal silicide 14 of 16 belows, space causes the loss of metal silicide 14; Thereby the contact plug 18 and the contact resistance in source region, drain region are increased, influence device performance; In addition,, therefore when etching forms contact hole 17, cause contact hole 17 not open fully easily, cause contact hole 17 not expose metal silicide 14, finally cause device unavailable because the depth-to-width ratio of the contact hole 17 that will form is high.
In the prior art, disclose many formation methods about the contact plug, for example on December 31st, 2006, disclosed application number was 200610156430.8 Chinese patent disclosed " manufacturing comprises the method for the semiconductor device of plug ".Yet, all do not solve above-described technical problem.
Summary of the invention
The problem that the present invention solves is the method that prior art forms the contact plug, in interlayer dielectric layer, forms the space easily and causes conducting of adjacent contact plug and metal silicide loss to cause contact resistance to increase; The depth-to-width ratio height of contact hole causes contact hole not opened fully.
For addressing the above problem, the present invention provides a kind of method that forms the contact plug, comprising:
Substrate is provided; Have source region, drain region in the said substrate, be formed with grid structure in the said substrate, said source region, drain region are positioned at said grid structure substrate on two sides; Said grid structure comprises side wall and grid, is formed with metal silicide on said intrabasement source region and the drain region;
Utilize the method for electroless plating on said metal silicide, to form the conductive layer of predetermined thickness;
Form interlayer dielectric layer, cover said conductive layer and said grid structure;
In said interlayer dielectric layer, form contact hole, expose said conductive layer;
Filled conductive material in said contact hole forms the contact plug.
Optional, said conductive layer is cobalt tungsten phosphorus, cobalt molybdenum phosphorus, nickel or palladium.
Optional, said predetermined thickness is 100 dusts-700 dusts.
Optional, said side wall is a laminated construction, comprises internal layer side wall and outer side wall, said outer side wall is positioned at the said internal layer side wall outside.
Optional, the material of said outer side wall is a silicon nitride, the material of said internal layer side wall is a silica.
Optional, form after the conductive layer of predetermined thickness, form interlayer dielectric layer and also comprise before:
The said outer side wall of etching, removal exceeds the outer side wall of the predetermined altitude of said conductive layer;
The deposition-etch barrier layer covers side wall, grid and conductive layer through etching, and the dopant ion that said source region, drain region are is the p type, and said etching barrier layer has compression; Perhaps, the dopant ion that said source region, drain region are is the n type, and said etching barrier layer has tension stress.
Optional, the material of said etching barrier layer is a silicon nitride.
Optional, said formation interlayer dielectric layer covers said conductive layer and said grid structure comprises:
Utilize the HARP deposition process to form interlayer dielectric layer, cover said conductive layer and said grid structure, and the surface of said interlayer dielectric layer is higher than the surface of said grid;
The said interlayer dielectric layer of planarization makes the surfacing of said interlayer dielectric layer.
Optional, in said interlayer dielectric layer, form contact hole, expose said conductive layer and comprise:
On said interlayer dielectric layer, form amorphous carbon layer, hard mask layer, photoresist layer successively;
Graphical said photoresist layer is the said hard mask layer of mask dry etching, amorphous carbon layer with the photoresist layer after graphical, defines the position of contact hole;
With the amorphous carbon layer after the etching, hard mask layer is mask, and the said interlayer dielectric layer of etching forms contact hole until exposing said conductive layer;
Amorphous carbon layer after the removal etching.
Optional, the electric conducting material of filling in the said contact hole is tungsten or copper.
Optional, said metal silicide is nickle silicide or cobalt silicide.
The present invention also provides the another kind of method that forms the contact plug, comprising:
Substrate is provided; Have source region, drain region in the said substrate, be formed with dummy gate structure in the said substrate, said source region, drain region are positioned at said dummy gate structure substrate on two sides; Said dummy gate structure comprises dummy grid and side wall, is formed with metal silicide on the source region of said substrate and the drain region;
Utilize the method for electroless plating on said metal silicide, to form the conductive layer of predetermined thickness;
Form first interlayer dielectric layer, cover said conductive layer and said dummy gate structure, its surface is surperficial equal with said dummy grid;
Remove said dummy grid, form the dummy grid groove, the filled conductive material forms grid in said dummy grid groove;
Form second interlayer dielectric layer, cover said grid, side wall and first interlayer dielectric layer;
Form contact hole, run through said first interlayer dielectric layer and second interlayer dielectric layer, expose said conductive layer;
Filled conductive material in said contact hole forms the contact plug.
Optional, said conductive layer is cobalt tungsten phosphorus, cobalt molybdenum phosphorus, nickel or palladium.
Optional, said predetermined thickness is 100 dusts-700 dusts.
Optional, said side wall is a laminated construction, comprises internal layer side wall and outer side wall, said outer side wall is positioned at the said internal layer side wall outside.
Optional, the material of said outer side wall is a silicon nitride, the material of said internal layer side wall is a silica.
Optional, form after the conductive layer of predetermined thickness, form first interlayer dielectric layer and also comprise before:
The said outer side wall of etching, removal exceeds the outer side wall of the predetermined altitude of said conductive layer;
The deposition-etch barrier layer covers side wall, dummy grid and conductive layer through etching, and the dopant ion that said source region, drain region are is the p type, and said etching barrier layer has compression; Perhaps, the dopant ion that said source region, drain region are is the n type, and said etching barrier layer has tension stress.
Optional, the material of said etching barrier layer is a silicon nitride.
Optional, said formation first interlayer dielectric layer covers said conductive layer and said dummy gate structure comprises:
Utilize the HARP deposition process to form first interlayer dielectric layer, cover said conductive layer and said dummy gate structure, and the surface of said first interlayer dielectric layer is higher than the surface of said dummy grid;
Said first interlayer dielectric layer of planarization is removed first interlayer dielectric layer exceed dummy grid, and the surface that makes said first interlayer dielectric layer is surperficial equal with dummy grid.
Optional, the method that forms contact hole comprises:
On said second interlayer dielectric layer, form photoresist layer, hard mask layer, amorphous carbon layer;
Graphical said photoresist layer, hard mask layer, amorphous carbon layer define the position of contact hole;
Photoresist layer, hard mask layer, amorphous carbon layer with after graphical are mask, and said first interlayer dielectric layer of etching, second interlayer dielectric layer form contact hole until exposing said conductive layer;
Photoresist layer, hard mask layer, amorphous carbon layer after removing graphically.
Optional, the electric conducting material of filling in the said dummy grid groove is a metal.
Optional, the electric conducting material of filling in the said contact hole is tungsten or copper.
Optional, said metal silicide is nickle silicide or cobalt silicide.
Compared with prior art, the present invention has the following advantages:
The present invention's first technical scheme; Utilize the method for electroless plating on the metal silicide on source region, the drain region, to form the conductive layer of predetermined thickness; The conductive layer of this predetermined thickness reduces the depth-to-width ratio in the space of source region, top, drain region; Therefore can improve the filling capacity of the interlayer dielectric layer of source region, drain region superjacent air space; Avoid or reduce at least the generation of the interlayer dielectric layer internal pore of source region, drain region superjacent air space; Thereby also just can avoid or reduce between the adjacent contact plug problem at least, and can avoid or loss and the problem that the contact resistance that causes increases of metal silicide when reducing the etching interlayer dielectric layer at least and forming contact hole because of the space conducting.And; The conductive layer of this predetermined thickness is with the position bed hedgehopping of contact hole; When in interlayer dielectric layer, forming contact hole, the depth-to-width ratio of contact hole reduces, and can avoid because the depth-to-width ratio height of contact hole when causing etching to form contact hole; Do not expose metal silicide, finally cause the disabled shortcoming of device.
The present invention's second technical scheme; Utilize the method for electroless plating on the metal silicide on source region, the drain region, to form the conductive layer of predetermined thickness; The conductive layer of this predetermined thickness reduces the depth-to-width ratio in the space of source region, top, drain region; Can improve the filling capacity of first interlayer dielectric layer of source region, drain region superjacent air space; Avoid or reduce at least the generation of source region, the drain region superjacent air space first interlayer dielectric layer internal pore; From between the adjacent contact plug because of the problem of space conducting, and can avoid or reduce etching first interlayer dielectric layer at least, loss and the problem that the contact resistance that causes increases of metal silicide when second interlayer dielectric layer forms contact hole.And; The conductive layer of this predetermined thickness is with the position bed hedgehopping of contact hole; When in first interlayer dielectric layer and second interlayer dielectric layer, forming contact hole, the depth-to-width ratio of contact hole reduces, and can avoid because the depth-to-width ratio height of contact hole when causing etching to form contact hole; Do not expose metal silicide, finally cause the disabled shortcoming of device.
Description of drawings
Fig. 1～Fig. 4 is the cross-sectional view that forms the method for contact plug in the prior art;
Fig. 5 is the schematic flow sheet that the formation of the present invention's first specific embodiment contacts the method for plug;
Fig. 6～Figure 11 is the cross-sectional view that the formation of the present invention's first specific embodiment contacts the method for plug;
Figure 12 is the schematic flow sheet that the formation of the present invention's second specific embodiment contacts the method for plug;
Figure 13～Figure 19 is the cross-sectional view that the formation of the present invention's second specific embodiment contacts the method for plug.
Embodiment
The present invention's first technical scheme; Utilize the method for electroless plating on the metal silicide on source region, the drain region, to form the conductive layer of predetermined thickness; The conductive layer of this predetermined thickness reduces the depth-to-width ratio in the space of source region, top, drain region; Therefore can improve the filling capacity of the interlayer dielectric layer of source region, drain region superjacent air space; Avoid or reduce at least the generation of the interlayer dielectric layer internal pore of source region, drain region superjacent air space; Thereby also just can avoid or reduce between the adjacent contact plug problem at least, and can avoid or loss and the problem that the contact resistance that causes increases of metal silicide when reducing the etching interlayer dielectric layer at least and forming contact hole because of the space conducting.And; The conductive layer of this predetermined thickness is with the position bed hedgehopping of contact hole; When in interlayer dielectric layer, forming contact hole, the depth-to-width ratio of contact hole reduces, and can avoid because the depth-to-width ratio height of contact hole when causing etching to form contact hole; Do not expose metal silicide, finally cause the disabled shortcoming of device.
In order to make those skilled in the art can better understand the present invention, and make the present invention clearer, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 5 is the schematic flow sheet that the formation of the present invention's first specific embodiment contacts the method for plug, and with reference to figure 5, the method for the formation of the present invention's first specific embodiment contact plug comprises:
Step S11 provides substrate, has source region, drain region in the said substrate; Be formed with grid structure in the said substrate; Said source region, drain region are positioned at said grid structure substrate on two sides, and said grid structure comprises side wall and grid, are formed with metal silicide on the source region of said substrate and the drain region;
Step S12 utilizes the method for electroless plating on said metal silicide, to form the conductive layer of predetermined thickness;
Step S13 forms interlayer dielectric layer, covers said conductive layer and said grid structure;
Step S14 forms contact hole in said interlayer dielectric layer, expose said conductive layer;
Step S15, filled conductive material in said contact hole forms the contact plug.
Fig. 6～Figure 11 is the cross-sectional view that the formation of the present invention's first specific embodiment contacts the method for plug, specifies the method for the formation contact plug of first technical scheme of the present invention below in conjunction with first specific embodiment, Fig. 5 and Fig. 6～Figure 11.
In conjunction with reference to figure 5 and Fig. 6; Execution in step S11 provides substrate 20, has source region, drain region (not shown) in the said substrate 20; Be formed with grid structure in the said substrate 20; Said source region, drain region are positioned at said grid structure substrate on two sides 20, and said grid structure comprises side wall 24 and grid 23, is formed with metal silicide 22 on the source region of said substrate 20 and the drain region.
The material of substrate 20 can be the silicon or the SiGe of monocrystalline or non crystalline structure; It also can be silicon-on-insulator (SOI); The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.In substrate 20, be formed with the isolation trench structure (not shown), adjacent active area is isolated each other.Also has the well region (not shown) in the substrate 20.
In this first embodiment, be gate dielectric layer 21 between grid 23 and the substrate 20, the material of this gate dielectric layer 21 can well known to a person skilled in the art material for silica etc.Forming after the grid structure, is mask with the grid structure, and being mixed in the active area regions in the substrate 20, zone, drain region forms source region, drain region; Wherein, the type of the ion of doping is confirmed according to the transistorized type that forms, if form the PMOS transistor; Doped p type impurity then, B (boron) for example is if form nmos pass transistor; Then Doped n-type impurity, for example P (phosphorus).It between source region and the drain region channel region.
Form after source region and the drain region, in order to be reduced in the contact resistance in the contact plug that forms on source region, the drain region and source region, drain region, formation metal silicide 22 on source region and drain region, metal silicide 22 is nickle silicide or cobalt silicide among this embodiment.
In the present invention, side wall 24 can also can be laminated construction for single layer structure, and in this first embodiment, side wall 24 is a laminated construction, comprises internal layer side wall 241 and outer side wall 242, and said outer side wall 242 is positioned at said internal layer side wall 241 outsides.The material of said outer side wall 242 is a silicon nitride, and the material of said internal layer side wall 241 is a silica.
In conjunction with reference to figure 5 and Fig. 7, execution in step S12 utilizes the method for electroless plating on said metal silicide 22, to form the conductive layer 25 of predetermined thickness.Need not feed electric current and be based on the plating that reduction chemically realizes and be commonly referred to electroless plating.Electroless plating has following characteristics: 1, need supply power unlike the metallide that kind, and no matter plating piece why shape all can obtain uniform film; 2, can obtain to meet the film of instructions for use through adjustment plating condition.Characteristics based on electroless plating method; The present invention has formed the conductive layer 25 of predetermined thickness on metal silicide 22; Because the metal silicide 22 on source region, the drain region is not outside being exposed to fully, to that is to say, on the metal silicide that exposes 22, has formed the conductive layer 25 of predetermined thickness.
In this first embodiment, conductive layer 25 is cobalt tungsten phosphorus Co (W, P), cobalt molybdenum phosphorus Co (Mo, P), nickel (Ni) or palladium (Pd).The predetermined thickness of conductive layer 25 is 100 dusts-700 dusts.
With reference to figure 8, in this first embodiment, form after the conductive layer 25 of predetermined thickness, the said outer side wall 242 of etching, removal exceeds the outer side wall 242 of the predetermined altitude of said conductive layer 25; The deposition-etch barrier layer 26 afterwards; Cover said grid structure and conductive layer 25; Promptly cover side wall (comprising internal layer side wall 241 and outer side wall 242), grid 23 and conductive layer 25 through etching, this etching barrier layer 26 has stress, to improve the mobility of charge carrier rate; In said source region, when the drain region dopant ion that is is the p type, said etching barrier layer 26 has compression; In said source region, when the drain region dopant ion that is is the n type, said etching barrier layer 26 has tension stress.The material of said etching barrier layer 26 is a silicon nitride.
In this first embodiment, remove the outer side wall 242 that exceeds conductive layer 25, in other embodiments, also can be for only removing the part of the outer side wall 242 that exceeds conductive layer 25.Utilize dry etching to remove the outer side wall 242 of predetermined altitude; And in the dry etching; Other structures (comprising internal layer side wall 241, grid 23 and metal silicide 25) to outside outer side wall 242 and the outer side wall 242 have high selectivity; When guaranteeing etching skin side wall 242, can not cause damage to other structures.
In conjunction with reference to figure 5 and Fig. 9, execution in step S13 forms interlayer dielectric layer 27, covers said conductive layer 25 and said grid structure.In this first specific embodiment, owing to formed etching barrier layer 26, and outer side wall 242 has been carried out etching, therefore, interlayer dielectric layer 27 covers etching barrier layer 26.Certainly, if outer side wall 242 is not carried out etching and forms etching barrier layer, 27 of interlayer dielectric layers directly cover conductive layer 25 and grid structure.In this first embodiment, utilize HARP (highaspect ratio process) deposition process to form interlayer dielectric layer 27, cover said etching barrier layer 26; Afterwards, need the said interlayer dielectric layer 27 of planarization, make the surfacing of said interlayer dielectric layer 27.In this first embodiment, the material of interlayer dielectric layer 27 is a silica, and the gas that uses in the HARP technology comprises O
3And TEOS (tetraethyl orthosilicate).Certainly, the material of interlayer dielectric layer 27 is not limited to silica, also can be low-k materials and ultralow k material, and wherein low-k materials can be SiOF, SiCOH, SiO, SiCO, SiCON, and ultralow k material can be black diamond.
Because; Conductive layer 25 is with the position bed hedgehopping of the interlayer dielectric layer 27 of source region, top, drain region; Therefore, the depth-to-width ratio of the interlayer dielectric layer 27 above source region, drain region reduces, when utilizing HARP technology to form interlayer dielectric layer 27; The space can be avoided forming in the interlayer dielectric layer 27 of source region, top, drain region, interstitial quantity and probability can be reduced at least.Thereby also just can avoid or reduce between the adjacent contact plug problem (space is formed on the problem that produces between the adjacent contact plug) at least, and can avoid or loss and the problem that the contact resistance that causes increases (space is formed on the problem that produces in the regional extent of contact hole) of metal silicide when reducing the etching interlayer dielectric layer at least and forming contact hole because of the space conducting.
In conjunction with reference to figure 5 and Figure 10, execution in step S14 forms contact hole 28 in said interlayer dielectric layer 27, expose said conductive layer 25.In this first embodiment; Owing to also comprised formation etching barrier layer 26, so contact hole 28 also runs through etching barrier layer 26 to expose conductive layer 25, that is to say; In interlayer dielectric layer 27, etching barrier layer 26, form contact hole 28, expose said conductive layer 25.Wherein, In said interlayer dielectric layer 27, etching barrier layer 26, form contact hole 28; Exposing said conductive layer 25 comprises: on said interlayer dielectric layer 27, form amorphous carbon layer, hard mask layer, photoresist layer successively; That is to say that amorphous carbon layer is formed on the interlayer dielectric layer 27, hard mask layer is formed on the amorphous carbon layer, and photoresist layer is formed on the hard mask layer; Graphical said photoresist layer is mask dry etching hard mask layer, amorphous carbon layer with the photoresist layer after graphical, defines the position of contact hole 28; With the amorphous carbon layer after the said etching, hard mask layer is mask, and the said interlayer dielectric layer of dry etching, etching barrier layer form contact hole 28 until exposing said conductive layer 25; At last, the amorphous carbon layer after the said etching is removed in ashing.Wherein, the method for graphical said photoresist layer for the exposure, developing process, utilize the graphical photoresist layer of exposure imaging technology after; Photoresist layer with after graphical is a mask; Dry etching hard mask layer, amorphous carbon layer successively, wherein, photoresist layer is removed in this dry etching process; When forming contact hole 28; With the agraphitic carbon after the etching, hard mask layer is that mask dry etching interlayer dielectric layer forms contact hole 28, and the hard mask layer after the etching is consumed in dry etching forms the process of contact hole 28, need not once to remove the step of hard mask layer in the technology afterwards again.In the process that forms contact hole 28; Do not use traditional photoetching, etching technics; But formed photoresist layer, hard mask layer, amorphous carbon layer three-decker, graphically this three-decker defines the position of contact hole, and does the mask etching interlayer dielectric layer with this three-decker.Adopt this kind method, can avoid because the characteristic size of device is more and more littler, the thickness of photoresist layer is unsuitable blocked up, only does the too thin problem that can damage understructure of mask lithography glue-line with photoresist layer.Wherein the material of hard mask layer can be SiON.
In conjunction with reference to figure 5 and Figure 11, execution in step S15, filled conductive material in said contact hole forms contact plug 29.In this first embodiment, the electric conducting material of filling in the contact hole is tungsten or copper, and its fill method is a physical vapour deposition (PVD), also can be for electroplating.
Need to prove, in first embodiment, form before the interlayer dielectric layer 27, form after the conductive layer 25, outer side wall 242 has been carried out etching, and formed have stress etching barrier layer 26 to improve the mobility of charge carrier rate.Also can after forming conductive layer 25, directly form interlayer dielectric layer 27, outer side wall 242 not carried out etching, also not form etching barrier layer 26.
The above is the method for the formation contact plug of first embodiment of the invention, and it is in preceding grid technique, to form the contact plug.
The present invention's second technical scheme; Utilize the method for electroless plating on the metal silicide on source region, the drain region, to form the conductive layer of predetermined thickness; The conductive layer of this predetermined thickness reduces the depth-to-width ratio in the space of source region, top, drain region; Can improve the filling capacity of first interlayer dielectric layer of source region, drain region superjacent air space; Avoid or reduce at least the generation of source region, the drain region superjacent air space first interlayer dielectric layer internal pore; From between the adjacent contact plug because of the problem of space conducting, and can avoid or reduce etching first interlayer dielectric layer at least, loss and the problem that the contact resistance that causes increases of metal silicide when second interlayer dielectric layer forms contact hole.And; The conductive layer of this predetermined thickness is with the position bed hedgehopping of contact hole; When in first interlayer dielectric layer and second interlayer dielectric layer, forming contact hole, the depth-to-width ratio of contact hole reduces, and can avoid because the depth-to-width ratio height of contact hole when causing etching to form contact hole; Do not expose metal silicide, finally cause the disabled shortcoming of device.
Figure 12 is for the schematic flow sheet of the method for the formation contact plug of the present invention's second specific embodiment, and with reference to Figure 12, the method for the formation of the present invention's second specific embodiment contact plug comprises:
Step S21; Substrate is provided; Have source region, drain region in the said substrate, be formed with dummy gate structure in the said substrate, said source region, drain region are positioned at said dummy gate structure substrate on two sides; Said dummy gate structure comprises dummy grid and side wall, is formed with metal silicide on the source region of said substrate and the drain region;
Step S22 utilizes the method for electroless plating on said metal silicide, to form the conductive layer of predetermined thickness;
Step S23 forms first interlayer dielectric layer, covers said conductive layer and said dummy gate structure, and its surface is surperficial equal with said dummy grid;
Step S24 removes said dummy grid, forms the dummy grid groove, and the filled conductive material forms grid in said dummy grid groove;
Step S25 forms second interlayer dielectric layer, covers said grid, side wall and first interlayer dielectric layer;
Step S26 forms contact hole, runs through said first interlayer dielectric layer and second interlayer dielectric layer, exposes said conductive layer;
Step S27, filled conductive material in said contact hole forms the contact plug.
Figure 13～Figure 19 is the method for the formation contact plug of second embodiment of the invention, and it is in the grid technique of back, to form the contact plug.
In conjunction with reference to Figure 12 and Figure 13; Execution in step S21 provides substrate 30, has source region, drain region (not shown) in the said substrate 30; Be formed with dummy gate structure in the said substrate 30; Said source region, drain region are positioned at said dummy gate structure substrate on two sides, and said dummy gate structure comprises side wall 34 and dummy grid 33, is formed with metal silicide 32 on the source region of said substrate 30 and the drain region.
The material of substrate 30 is identical with first embodiment, and this does not do and gives unnecessary details.And between dummy grid 33 and substrate 30, also be formed with gate dielectric layer 31, the material require of gate dielectric layer 31 is selected according to the needs of reality.
Forming after the dummy gate structure, is mask with the dummy gate structure, and being mixed in the active area regions in the substrate 30, zone, drain region forms source region, drain region; Wherein, the type of the ion of doping is confirmed according to the transistorized type that forms, if form the PMOS transistor; Doped p type impurity then, B (boron) for example is if form nmos pass transistor; Then Doped n-type impurity, for example P (phosphorus).It between source region and the drain region channel region.
Form after source region and the drain region, in order to be reduced in the contact resistance in the contact plug that forms on source region, the drain region and source region, drain region, formation metal silicide 32 on source region and drain region, metal silicide 32 is nickle silicide or cobalt silicide among this embodiment.
The structure of side wall 34 can also can be laminated construction for single layer structure, and among this second embodiment, for laminated construction comprises internal layer side wall 341 and outer side wall 342, identical with first embodiment, this does not do and gives unnecessary details.
In conjunction with reference to figure 5 and Figure 14, execution in step S22 utilizes the method for electroless plating on said metal silicide 32, to form the conductive layer 35 of predetermined thickness.This step is identical with step S12 among first embodiment, does not detail at this, sees also the description of first embodiment.
In conjunction with reference to Figure 12 and Figure 15, execution in step S23 forms first interlayer dielectric layer 36, covers said conductive layer 35 and said dummy gate structure, and its surface is surperficial equal with said dummy grid 33.Utilize the HARP deposition process to form first interlayer dielectric layer 36, cover said conductive layer 35 and said dummy gate structure, and the surface of said first interlayer dielectric layer 36 is higher than the surface of said dummy grid 33; Said first interlayer dielectric layer 36 of planarization, the surface that makes said first interlayer dielectric layer 36 is surperficial equal with dummy grid 33.Need to prove that " equal " here also do not mean that dielectric layer 36 is equal fully with the surface of dummy grid 33 between ground floor, and certain error can be arranged.The interlayer dielectric layer is identical among the material of first interlayer dielectric layer 36 and first embodiment, and this does not do and gives unnecessary details.
In conjunction with reference to Figure 12 and Figure 16, Figure 15, execution in step S24 removes said dummy grid 33, forms the dummy grid groove, and the filled conductive material forms grid 37 in said dummy grid groove.The method of removing dummy grid 33 can also can be wet etching for dry etching, and is different according to the material of dummy grid 33, selects the corresponding technology of removing.The electric conducting material of filling in the dummy grid groove is a metal, and its fill method is physical vapour deposition (PVD) or electroplates.The type of wherein, filling metal is confirmed according to the transistorized type that forms.
In conjunction with reference to Figure 12 and Figure 17, execution in step S25 forms second interlayer dielectric layer 38, covers said grid 37, side wall 34 and first interlayer dielectric layer 36.The material of second interlayer dielectric layer 38 can be identical with the material of first interlayer dielectric layer 36, also can be different.The method that forms second interlayer dielectric layer 38 is chemical vapour deposition (CVD).
Because; Conductive layer 35 is with the position bed hedgehopping of first interlayer dielectric layer 36 of source region, top, drain region; Therefore, the depth-to-width ratio of first interlayer dielectric layer 36 above source region, drain region reduces, when utilizing HARP technology to form first interlayer dielectric layer 36; The space can be avoided forming in first interlayer dielectric layer 36 of source region, top, drain region, interstitial quantity and probability can be reduced at least.Thereby also just can avoid or reduce between the adjacent contact plug problem (space is formed on the problem that produces between the adjacent contact plug) at least because of the space conducting, and can avoid or reduce etching first interlayer dielectric layer 36 at least, loss and the problem that the contact resistance that causes increases (space is formed on the problem that produces in the regional extent of contact hole) of metal silicide 32 when second interlayer dielectric layer 38 forms contact holes.
In conjunction with reference to Figure 12 and Figure 18, execution in step S26 forms contact hole 39, runs through said first interlayer dielectric layer 36 and second interlayer dielectric layer 38, exposes said conductive layer 35.The method that forms first contact hole 39 is identical with first embodiment, and this does not do and gives unnecessary details.
In conjunction with reference to Figure 12 and Figure 19, execution in step S27, filled conductive material in said contact hole forms contact plug 40.The electric conducting material of filling in the said contact hole is tungsten or copper.
Need to prove, in a second embodiment, form after the conductive layer 35, directly form first interlayer dielectric layer 36.Also can with similar first embodiment, form after the conductive layer 35, form before first interlayer dielectric layer 36, outer side wall 342 is carried out etching, remove the outer side wall 342 of the predetermined altitude that exceeds said conductive layer 35; The deposition-etch barrier layer covers said dummy gate structure and conductive layer afterwards, and this etching barrier layer has stress, and to improve the mobility of charge carrier rate, in said source region, when the drain region dopant ion that is is the p type, said etching barrier layer has compression; In said source region, when the drain region dopant ion that is is the n type, said etching barrier layer has tension stress.The material of said etching barrier layer is a silicon nitride.The description of detailed method can be referring to first embodiment.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (23)
1. a method that forms the contact plug is characterized in that, comprising:
Substrate is provided; Have source region, drain region in the said substrate, be formed with grid structure in the said substrate, said source region, drain region are positioned at said grid structure substrate on two sides; Said grid structure comprises side wall and grid, is formed with metal silicide on said intrabasement source region and the drain region;
Utilize the method for electroless plating on said metal silicide, to form the conductive layer of predetermined thickness;
Form interlayer dielectric layer, cover said conductive layer and said grid structure;
In said interlayer dielectric layer, form contact hole, expose said conductive layer;
Filled conductive material in said contact hole forms the contact plug.
2. the method for formation contact plug as claimed in claim 1 is characterized in that said conductive layer is cobalt tungsten phosphorus, cobalt molybdenum phosphorus, nickel or palladium.
3. the method for formation contact plug as claimed in claim 1 is characterized in that said predetermined thickness is 100 dusts-700 dusts.
4. the method for formation contact plug as claimed in claim 1 is characterized in that said side wall is a laminated construction, comprises internal layer side wall and outer side wall, and said outer side wall is positioned at the said internal layer side wall outside.
5. the method for formation contact plug as claimed in claim 4 is characterized in that the material of said outer side wall is a silicon nitride, and the material of said internal layer side wall is a silica.
6. the method for formation contact plug as claimed in claim 4 is characterized in that, forms after the conductive layer of predetermined thickness, forms interlayer dielectric layer and also comprises before:
The said outer side wall of etching, removal exceeds the outer side wall of the predetermined altitude of said conductive layer;
The deposition-etch barrier layer covers side wall, grid and conductive layer through etching, and the dopant ion that said source region, drain region are is the p type, and said etching barrier layer has compression; Perhaps, the dopant ion that said source region, drain region are is the n type, and said etching barrier layer has tension stress.
7. the method for formation contact plug as claimed in claim 6 is characterized in that the material of said etching barrier layer is a silicon nitride.
8. the method for formation as claimed in claim 1 contact plug is characterized in that, said formation interlayer dielectric layer covers said conductive layer and said grid structure comprises:
Utilize the HARP deposition process to form interlayer dielectric layer, cover said conductive layer and said grid structure, and the surface of said interlayer dielectric layer is higher than the surface of said grid;
The said interlayer dielectric layer of planarization makes the surfacing of said interlayer dielectric layer.
9. the method for formation contact plug as claimed in claim 1 is characterized in that, in said interlayer dielectric layer, forms contact hole, exposes said conductive layer and comprises:
On said interlayer dielectric layer, form amorphous carbon layer, hard mask layer, photoresist layer successively;
Graphical said photoresist layer is the said hard mask layer of mask dry etching, amorphous carbon layer with the photoresist layer after graphical, defines the position of contact hole;
With the amorphous carbon layer after the etching, hard mask layer is mask, and the said interlayer dielectric layer of etching forms contact hole until exposing said conductive layer;
Amorphous carbon layer after the removal etching.
10. the method for formation contact plug as claimed in claim 1 is characterized in that the electric conducting material of filling in the said contact hole is tungsten or copper.
11. the method for formation contact plug as claimed in claim 1 is characterized in that said metal silicide is nickle silicide or cobalt silicide.
12. a method that forms the contact plug is characterized in that, comprising:
Substrate is provided; Have source region, drain region in the said substrate, be formed with dummy gate structure in the said substrate, said source region, drain region are positioned at said dummy gate structure substrate on two sides; Said dummy gate structure comprises dummy grid and side wall, is formed with metal silicide on the source region of said substrate and the drain region;
Utilize the method for electroless plating on said metal silicide, to form the conductive layer of predetermined thickness;
Form first interlayer dielectric layer, cover said conductive layer and said dummy gate structure, its surface is surperficial equal with said dummy grid;
Remove said dummy grid, form the dummy grid groove, the filled conductive material forms grid in said dummy grid groove;
Form second interlayer dielectric layer, cover said grid, side wall and first interlayer dielectric layer;
Form contact hole, run through said first interlayer dielectric layer and second interlayer dielectric layer, expose said conductive layer;
Filled conductive material in said contact hole forms the contact plug.
13. the method for formation contact plug as claimed in claim 12 is characterized in that said conductive layer is cobalt tungsten phosphorus, cobalt molybdenum phosphorus, nickel or palladium.
14. the method for formation contact plug as claimed in claim 12 is characterized in that said predetermined thickness is 100 dusts-700 dusts.
15. the method for formation contact plug as claimed in claim 12 is characterized in that said side wall is a laminated construction, comprises internal layer side wall and outer side wall, said outer side wall is positioned at the said internal layer side wall outside.
16. the method for formation contact plug as claimed in claim 15 is characterized in that the material of said outer side wall is a silicon nitride, the material of said internal layer side wall is a silica.
17. the method for formation contact plug as claimed in claim 15 is characterized in that, forms after the conductive layer of predetermined thickness, forms first interlayer dielectric layer and also comprises before:
The said outer side wall of etching, removal exceeds the outer side wall of the predetermined altitude of said conductive layer;
The deposition-etch barrier layer covers side wall, dummy grid and conductive layer through etching, and the dopant ion that said source region, drain region are is the p type, and said etching barrier layer has compression; Perhaps, the dopant ion that said source region, drain region are is the n type, and said etching barrier layer has tension stress.
18. the method for formation contact plug as claimed in claim 17 is characterized in that the material of said etching barrier layer is a silicon nitride.
19. the method for formation as claimed in claim 12 contact plug is characterized in that, said formation first interlayer dielectric layer covers said conductive layer and said dummy gate structure comprises:
Utilize the HARP deposition process to form first interlayer dielectric layer, cover said conductive layer and said dummy gate structure, and the surface of said first interlayer dielectric layer is higher than the surface of said dummy grid;
Said first interlayer dielectric layer of planarization is removed first interlayer dielectric layer exceed dummy grid, and the surface that makes said first interlayer dielectric layer is surperficial equal with dummy grid.
20. the method for formation contact plug as claimed in claim 12 is characterized in that the method that forms contact hole comprises:
On said second interlayer dielectric layer, form photoresist layer, hard mask layer, amorphous carbon layer;
Graphical said photoresist layer, hard mask layer, amorphous carbon layer define the position of contact hole;
Photoresist layer, hard mask layer, amorphous carbon layer with after graphical are mask, and said first interlayer dielectric layer of etching, second interlayer dielectric layer form contact hole until exposing said conductive layer;
Photoresist layer, hard mask layer, amorphous carbon layer after removing graphically.
21. the method for formation contact plug as claimed in claim 12 is characterized in that the electric conducting material of filling in the said dummy grid groove is a metal.
22. the method for formation contact plug as claimed in claim 12 is characterized in that the electric conducting material of filling in the said contact hole is tungsten or copper.
23. the method for formation contact plug as claimed in claim 12 is characterized in that said metal silicide is nickle silicide or cobalt silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101263477A CN102790008A (en) | 2011-05-16 | 2011-05-16 | Method for forming contact plug |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101263477A CN102790008A (en) | 2011-05-16 | 2011-05-16 | Method for forming contact plug |
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| CN1319881A (en) * | 2000-03-09 | 2001-10-31 | 三星电子株式会社 | Method for forming self-aligning contact welding disc in metal inlay grid technology |
| CN1497737A (en) * | 2002-10-15 | 2004-05-19 | ��ʽ���綫֥ | Semiconductor device and its manufacturing method |
| US20040121604A1 (en) * | 2002-12-18 | 2004-06-24 | Chun-Feng Nieh | Method of etching a low-k dielectric layer |
| KR100524808B1 (en) * | 2003-12-16 | 2005-11-01 | 주식회사 하이닉스반도체 | Method for fabrication of dielectric layer using harp |
| CN101711427A (en) * | 2007-04-12 | 2010-05-19 | 先进微装置公司 | Strain hardening N-type semiconductor N device and be used for the method that this semiconductor device is made |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1319881A (en) * | 2000-03-09 | 2001-10-31 | 三星电子株式会社 | Method for forming self-aligning contact welding disc in metal inlay grid technology |
| CN1497737A (en) * | 2002-10-15 | 2004-05-19 | ��ʽ���綫֥ | Semiconductor device and its manufacturing method |
| US20040121604A1 (en) * | 2002-12-18 | 2004-06-24 | Chun-Feng Nieh | Method of etching a low-k dielectric layer |
| KR100524808B1 (en) * | 2003-12-16 | 2005-11-01 | 주식회사 하이닉스반도체 | Method for fabrication of dielectric layer using harp |
| CN101711427A (en) * | 2007-04-12 | 2010-05-19 | 先进微装置公司 | Strain hardening N-type semiconductor N device and be used for the method that this semiconductor device is made |
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Application publication date: 20121121 |