CN102779787A - Preparation method of III-nitride semiconductor devices - Google Patents
Preparation method of III-nitride semiconductor devices Download PDFInfo
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- CN102779787A CN102779787A CN2012102519771A CN201210251977A CN102779787A CN 102779787 A CN102779787 A CN 102779787A CN 2012102519771 A CN2012102519771 A CN 2012102519771A CN 201210251977 A CN201210251977 A CN 201210251977A CN 102779787 A CN102779787 A CN 102779787A
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Abstract
The invention discloses a preparation method of III-nitride semiconductor devices. The method includes the steps: A) forming an III-nitride layer on a substrate by means of epitaxy; B) forming a plurality of grooves on the III-nitride layer which is divided into multiple independent regions by the grooves; and C) micromachining the multiple independent regions and the substrate in the regions to form one or more semiconductor devices. By the preparation method, warping caused by the problem of thermal mismatch and the problem of mismatch of crystal lattices among the substrate and III-nitrides can be solved to guarantee the high-quality wafer micromachining process, and device yield can be greatly increased.
Description
Technical field
The present invention relates to a kind of preparation method of III nitride semiconductor devices.
Background technology
As everyone knows, always run into the problem of epitaxial material and backing material lattice mismatch in the semiconductor epitaxial growth.Therefore, in the coupling epitaxial process of III group-III nitride and substrate, can be certain arch between III group-III nitride and the substrate; This arch can't be distinguished through naked eyes; But through drawing under the devices such as laser-bounce appearance, crystal lattice difference is big more, and the radian of arch is also just big more.Cause because arch is the physical attribute of himself, thereby be unavoidable.
But in the following process process, this arch can be brought very large problem, for example locatees inaccurate and influences the precision of whole process flow, thereby the micro-machined uniformity of wafer is reduced greatly.Therefore, how reducing the warpage brought by lattice tightness difference, is those skilled in the art's technical barriers anxious to be solved.
Summary of the invention
To the problems referred to above, main purpose of the present invention provides a kind of preparation method of III nitride semiconductor devices, has solved the manufacturing deficiency that is caused by the crystal lattice difference between III group-III nitride and the substrate.
In order to solve an above-mentioned difficult problem, the scheme that the present invention takes is a kind of preparation method of III nitride semiconductor devices, and it may further comprise the steps:
A) extension goes out the III group iii nitride layer on substrate;
B) on the III group iii nitride layer, form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval;
C) to a plurality of independently interval and be positioned at interval substrate and carry out little a plurality of semiconductor device that are processed to form.
Preferably, at step B) in, the minimum point of said groove and the distance of said substrate are between 0-3 μ m.
Preferably, at step B) in, said a plurality of groove parts be positioned at substrate.
Preferably, in steps A) in, adopt the MOVCD method to put that extension goes out the III group iii nitride layer on substrate.
Preferably, at step B) in, adopt etching method on the III group iii nitride layer, to form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval.
Preferably, at step B) in, adopt the method for laser on the III group iii nitride layer, to form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval.
Preferably, at step C) in little processing comprise in photoetching, etching, metal-coated membrane, the plating dielectric insulating film one or more.
Preferably, it also comprises a step D), the semiconductor device of a plurality of apportions is carried out the etching scribing, with its separation.
Preferably, described substrate is processed by among sapphire, Si or the SiC one or more.
The present invention adopts above method, can solve lattice mismatch problem and thermal mismatch problem between substrate and the III group-III nitride and the warpage that causes, thereby guarantee high-quality wafer micro fabrication, improves the yields of device greatly.
Description of drawings
Fig. 1 is the structural representation of substrate.
Fig. 2 goes out the structural representation of III group iii nitride layer for extension on substrate.
Fig. 3 is the front view when on the III group iii nitride layer, offering a plurality of groove.
Fig. 4 is for offering the front view before the following process behind a plurality of grooves on the III group iii nitride layer.
Fig. 5 is the vertical view after forming a plurality of grooves on the III group iii nitride layer.
In the accompanying drawing: 1, substrate; 2, III group iii nitride layer; 21, interval; 22, groove.
Embodiment
Below in conjunction with Figure of description preferred embodiment of the present invention is set forth in detail, thereby protection scope of the present invention is made more explicit defining so that advantage of the present invention and characteristic can be easier to those skilled in the art will recognize that.
In the first embodiment of the present invention: a kind of preparation method of III nitride semiconductor devices, it may further comprise the steps:
(A) as attaching shown in Fig. 1 and 2, extension goes out the III group iii nitride layer on substrate;
(B) on the III group iii nitride layer, form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval;
(C) to a plurality of independently interval and be positioned at interval substrate and carry out little semiconductor device that is processed to form a plurality of apportions.
In step (A), as attach shown in Fig. 1 and 2, adopt the MOVCD method to put that extension goes out the III group iii nitride layer on substrate.The III group iii nitride layer is made up of the III group-III nitride, and the III group-III nitride comprises AlN, GaN and InN etc.Metal organic chemical vapor deposition (MOCVD) is as the crystal growth source material with hydride of the organic compound of III family, II family element and V, VI family element etc.; With the pyrolysis mode at the enterprising promoting the circulation of qi phase epitaxy of substrate, the thin layer monocrystal material of grow various III-V family, II-VI compound semiconductor and their multivariate solid solution.Metal organic chemical vapor deposition system (MOCVD) utilizes a kind of chemical vapor deposition (CVD) technology of metallo-organic compound as the source material, and its principle is for utilizing Metalorganic chemical vapor deposition method metal-organic chemical vapor deposition.MOCVD utilizes vapor-phase reactant, or the NH3 of the organic metal of predecessor precursor and III family and V family, reacts on base material substrate surface, passes to the technology of base material substrate surface solid deposited thing.Further, substrate is processed by among sapphire, Si or the SiC one or more.
At step B) in, as shown in Figure 3, on the III group iii nitride layer, form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval.
Like Fig. 4 and shown in Figure 5, these intervals are separate, and therefore in operating process after this, the III group iii nitride layer between adjacent region can be to not causing the effect of power each other, and the tension force of the III group-III nitride in the interval is released.In the present embodiment,, on the III group iii nitride layer, obtain a plurality of separate intervals of arranging side by side thus to a plurality of grooves of horizontal and vertical formation of III group iii nitride layer.
The minimum point of groove and the distance of substrate are between 0-3 μ m.Further, groove as much as possible deeply and near substrate, then interior active force discharges manyly between adjacent region.Further, these grooves separate the III group iii nitride layer between adjacent region and the going deep in the substrate of part fully, and part is positioned at substrate at least.Structure thus, the active force between adjacent region is just littler.
The method that obtains these grooves can be etching.Etching (etching) is that material is used chemical reaction or physical shock effect and the technology that removes.Photochemical etching (photochemical etching) is also claimed in etching, refers to through after exposure plate-making, developing, and diaphragm that will etching area is removed, and the contact chemical solution reaches the effect of dissolved corrosion when etching, forms the effect of concavo-convex or hollow out moulding.Shown in accompanying drawing 2,
The method that obtains these grooves can also be a laser.But because the build-in attribute of laser, therefore, the border of the groove that obtains is so not smooth.
At step C) in, to a plurality of independently interval and be positioned at interval substrate and carry out little a plurality of semiconductor device that are processed to form.Micro-machined final purpose is that preparation forms semiconductor device on each III group-III nitride interval.
Micro-machined operating procedure can be photoetching, etching, metal-coated membrane, plating dielectric insulating film or other related process.
Further, the preparation method of III nitride semiconductor devices comprises that also one is positioned at step C) after step D), the semiconductor device of a plurality of apportions is carried out the etching scribing it is separated.Thus, obtain a plurality of individual semiconductor device.
The present invention adopts above method, can solve lattice mismatch problem and thermal mismatch problem between substrate and the III group-III nitride and the warpage that causes, thereby guarantee high-quality wafer micro fabrication, improves the yields of device greatly.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (9)
1. the preparation method of an III nitride semiconductor devices is characterized in that, it may further comprise the steps:
A) extension goes out the III group iii nitride layer on substrate;
B) on the III group iii nitride layer, form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval;
C) to a plurality of independently interval and be positioned at interval substrate and carry out little a plurality of semiconductor device that are processed to form.
2. the preparation method of the semiconductor device of III group-III nitride according to claim 1 is characterized in that: at step B) in, the minimum point of said groove and the distance of said substrate are between 0-3 μ m.
3. the preparation method of the semiconductor device of III group-III nitride according to claim 1 is characterized in that: at step B) in, said a plurality of grooves at least part be positioned at substrate.
4. the preparation method of the semiconductor device of III group-III nitride according to claim 1 is characterized in that: in steps A) in, adopt the MOVCD method to put that extension goes out the III group iii nitride layer on substrate.
5. the preparation method of III nitride semiconductor devices according to claim 1; It is characterized in that: at step B) in; Adopt etching method on the III group iii nitride layer, to form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval.
6. the preparation method of III nitride semiconductor devices according to claim 1; It is characterized in that: at step B) in; Adopt the method for laser on the III group iii nitride layer, to form a plurality of grooves, these grooves are divided into the III group iii nitride layer a plurality of independently interval.
7. the preparation method of III nitride semiconductor devices according to claim 1 is characterized in that: at step C) in little processing comprise in photoetching, etching, metal-coated membrane, the plating dielectric insulating film one or more.
8. the preparation method of III nitride semiconductor devices according to claim 1 is characterized in that: it also comprises a step D), the semiconductor device of a plurality of apportions is carried out the etching scribing it is separated.
9. the preparation method of III nitride semiconductor devices according to claim 1 is characterized in that: described substrate is processed by among sapphire, Si or the SiC one or more.
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| CN2012102519771A CN102779787A (en) | 2012-07-20 | 2012-07-20 | Preparation method of III-nitride semiconductor devices |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1675746A (en) * | 2002-07-11 | 2005-09-28 | 爱尔兰国家大学科克学院 | Defect reduction in semiconductor materials |
| CN102136678A (en) * | 2010-01-22 | 2011-07-27 | 三菱电机株式会社 | Method for manufacturing a semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1675746A (en) * | 2002-07-11 | 2005-09-28 | 爱尔兰国家大学科克学院 | Defect reduction in semiconductor materials |
| CN102136678A (en) * | 2010-01-22 | 2011-07-27 | 三菱电机株式会社 | Method for manufacturing a semiconductor device |
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Application publication date: 20121114 |