CN102769508A

CN102769508A - Reliability improvement device

Info

Publication number: CN102769508A
Application number: CN2011101195022A
Authority: CN
Inventors: 李升龙
Original assignee: Himax Media Solutions Inc
Current assignee: Himax Technologies Ltd; Himax Media Solutions Inc
Priority date: 2011-05-06
Filing date: 2011-05-06
Publication date: 2012-11-07

Abstract

The invention discloses a reliability improvement device. Code signals are received, and known signals such as apposition parity signals in the code signals are detected. When the known signals are detected out, pre-stored signals are used for replacing the known signals and feed the same back to a decoder. The code signals are directly fed back to the decoder when the known signals are not detected.

Description

Reliability improves device

Technical field

The present invention relates to a kind of coding, particularly relate to a kind of reliability of digital ground multimedia broadcast (DTMB) system that is applicable to and improve device.

Background technology

Low density parity check code (low-density parity-check; LDPC) be a kind of of forward error correction (FEC) coding; It uses the recursion algorithm; Generally be used in the middle of the communication system, particularly for the channel of additive white Gaussian noise (additive white Gaussian noise), can be in order to improve communication performance.

Digital ground multimedia broadcast (Digital Terrestrial Multimedia Broadcast, be called for short DTMB) system is a kind of in the middle of the various digital television broadcasting systems, and it has just used aforesaid LDPC coding.

Though these communication systems are used the coding such as LDPC,, still can receive various The noise, its performance still has the space of reinforcement.Therefore, novel mechanism need be proposed still, in order to promote communication performance.

Summary of the invention

To foregoing, one of purpose of the embodiment of the invention is to propose the device that a kind of reliability improves, and receives the reliability that bit included through changing, and is able to further promote the coding efficiency of LDPC.

According to the embodiment of the invention, reliability improves device and comprises counter, known signal positioner, look-up table, comparator and multiplexer.Counter is in order to the counting decoded positions.The known signal positioner is according to code rate and modulation type, to confirm the known signal position.Look-up table is in order to store the signal that prestores in advance.Comparator judges whether this decoded positions is identical with this known signal position.When comparator is judged to be when identical, then the multiplexer signal that prestores that will be stored in look-up table is fed to decoder; When comparator is judged to be not simultaneously, then multiplexer is fed to decoder with the code signal that receives.

Description of drawings

Figure 1A shows the calcspar of digital ground multimedia broadcast (DTMB) transmitting system.

Figure 1B shows the packet configuration of original transmission signals.

Fig. 1 C shows the packet configuration of outupt coded signal of the FEC encoder of Figure 1A.

Fig. 2 shows the calcspar of the DTMB receiving system of the embodiment of the invention.

Fig. 3 shows the detailed block diagram of the reliability raising unit of the embodiment of the invention.

Fig. 4 shows the look-up table content of present embodiment.

Fig. 5 shows the LDPC block of the various code rates of present embodiment.

Fig. 6 A to Fig. 6 E shows the look-up table content of various code rates and modulation type combination.

Embodiment

Figure 1A shows the calcspar of digital ground multimedia broadcast (DTMB) transmitting system, consists predominantly of scrambler (scrambler) 102, forward error correction (FEC) encoder 104, sign map (symbol mapping) unit 106, (interleaver) unit 108 that interweaves, frame main body (framebody) processor 110, frame generator 112, signal conversion unit 114 and up-conversion (up-conversion) unit 116.Figure 1B shows the packet configuration of original transmission signals (transport stream) TS, and the beginning of each grouping includes (known) fixing synchronizing signal SYNC, and for example 0,100 0111.FEC encoder 104 receives the scrambled signals of scrambler 102 outputs, and carries out Bose-Chaudhuri-Hocquenghem Code and low-density checksum (low-density parity-check, LDPC) coding.Fig. 1 C shows the packet configuration of the code signal of FEC encoder 104 output, and it includes synchronizing signal SYNC* through scrambling, through the BCH of Bose-Chaudhuri-Hocquenghem Code check bit BCH_PAR and through the LDPC check bit LDC_PAR of LDPC coding.(code rate CR) can be divided into three kinds of pattern: CR 0.4, CR 0.6 and CR 0.8 to the LDPC coding according to code rate.What Fig. 1 C showed is a frame of CR 0.8 pattern, and it comprises four groups of data that four scrambling synchronizing signal SYNC* are formed.As for CR 0.4 pattern, its each frame includes two groups of data, and each frame of CR 0.6 pattern includes three groups of data.

Fig. 2 shows the calcspar of the DTMB receiving system of the embodiment of the invention, and it is that reverse order according to the DTMB transmitting system of Figure 1A carries out reverse process respectively in principle.Though present embodiment with the DTMB system as an example, yet the present invention is also applicable in other similar communication system.In the present embodiment; The DTMB receiving system mainly comprises tuner (tuner) 202, oscillator (OSC) 204, analog-to-digital converter (ADC) 206, carrier wave restorer (carrier recovery) 208, temporal frame skew/timing off-set (timing frame offset/timing offset; TFO/TO) restorer 210, pseudo random number (pseudorandom number; PN) synchronizer 212, fast fourier transformer (FFT) 214, channel estimating DFF (channel estimation decision feedbackequalizer; CEDFE)/frequency-domain equalizer (frequency domain equalizer, FDE) 216, central controller 218, deinterleaving unit (de-interleaver) 220, separate map unit (demapper) 222, reliability improves unit 224, forward error correction (FEC) decoder 226 and descrambler (descrambler) 228.Because being the reverse order according to transmitting system, receiving system carries out reverse process; Therefore; Separate the code signal that the output signal of map unit 222 can be shown in Fig. 1 C figure in principle; And the output signal of descrambler 228 can be shown in Figure 1B transmission signals TS, and fec decoder device 226 comprises LDPC decoding and BCH decoding.

In the present embodiment, reliability improves unit 224 receptions and separates the code signal that map unit 222 is exported, and the known signal in the middle of detecting, for example (scrambling) synchronizing signal.Owing to receive the noise effect of communication channel, can reduce the reliability of the synchronizing signal that is received.In case when detecting synchronizing signal, then use the synchronizing signal of storage in advance to replace the synchronizing signal that is received, be fed to fec decoder device 226 again.For the code signal beyond the synchronizing signal, reliability improves unit 224 can directly be fed to fec decoder device 226 with it.

Note, and LDPC decoding use log-likelihood ratio (log-likelihood ratio LLR) receives bit with expression, the ratio value of this LLR value representation bit " 0 " probability and bit " 1 " probability, therefore, can be in order to represent the reliability of a bit.For example, if represent the LLR value, be that the probability of " 0 " is high more near 31 expression bits more then with [32,31] scope; In like manner, approaching more-32 expression bits are that the probability of " 1 " is high more.That is to say that if receive a bit " 0 ", its LLR value is more near 31, it is high more then to represent to be somebody's turn to do the reliability that receives bit " 0 "; Otherwise then reliability is low more.In like manner, if receive a bit " 1 ", its LLR value is approaching more-32, and then should to receive reliability of bit " 1 " high more in expression; Otherwise then reliability is low more.

Notice that again a kind of recursion (iterative) method is used in the LDPC decoding, belief propagation (beliefpropagation) method for example, its decoding performance depends on the distribution and the bit error rate of LLR value.If some bit that receives has high-reliability, then can be by the process of recursive decoding, in order to improve the reliability of other bit.

To foregoing; The reliability of present embodiment improves unit 224 replaces reception with the synchronizing signal of correct (high-reliability) (low reliability) synchronizing signal; And these (high-reliability) synchronizing signals after being substituted will be in the middle of follow-up recursive decoding process, in order to improve the reliability of other bit.

Fig. 3 shows the detailed block diagram of the reliability raising unit 224 of the embodiment of the invention.In the present embodiment, the synchronizing signal of correct (high-reliability) is stored in the look-up table 2240 in advance.Counter 2241 is controlled by central controller 218, in order to counting LDPC decoded positions.Synchronizing signal position controller 2242 receives code rate CR that central controllers 218 are provided and modulation, and (QAM) type is in order to confirm sync bit for quadrature amplitude modulation for example, quadrature amplitude modulation.When the counting position of counter 2241 and synchronizing signal position controller 2242 determined sync bits are judged to be when identical through comparator 2243; Then multiplexer 2244 synchronizing signal that can let look-up table 2240 prestored is fed to fec decoder device 226, thereby replaces the reception synchronizing signal of understanding map unit 222.When the counting position of counter 2241 and synchronizing signal position controller 2242 determined sync bits are judged to be when inequality through comparator 2243; Then multiplexer 2244 can let and be deposited at register 2245 (first-in first-out register for example, the code signal of separating map unit 222 outputs FIFO) is fed to fec decoder device 226.As previously mentioned, therefore fec decoder device 226 can improve the reliability of other bit because received the correctly synchronizing signal of (high-reliability) from look-up table 2240 in the middle of follow-up recursive decoding process.

Fig. 4 shows look-up table 2240 contents of present embodiment.In the present embodiment, only need be with content stores as shown in Figure 4 in look-up table 2240, promptly applicable to various code rate (as 0.4,0.6,0.8) and various modulation types (for example 4QAM-NR, 4QAM, 16QAM, 32QAM, 64QAM).Fig. 5 shows the LDPC block of the various code rates of present embodiment, and wherein, what each LDPC block left side showed is the synchronizing signal position of beginning.

The look-up table content of Fig. 6 A Fig. 6 various code rates of E illustration and modulation type combination.Fig. 6 A shows the look-up table content of three frames of CR 0.4 and 4QAM.Fig. 6 B shows the look-up table content of three frames of CR 0.6 and 16QAM, and wherein, each frame has two LDPC blocks.Fig. 6 C shows the look-up table content of the frame of CR 0.8 and 64QAM, and wherein, each frame has three LDPC blocks.Fig. 6 D shows the look-up table content of four frames of CR 0.8 and 4QAM-NR.Fig. 6 E shows the look-up table content of two frames of CR 0.8 and 32QAM, and wherein, per two frames have five LDPC blocks.

The above is merely preferred embodiment of the present invention, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being accomplished under the disclosed spirit of invention and changes or modification, all should be included in the following claim.

The primary clustering symbol description

102 scramblers

104 forward error corrections (FEC) encoder

106 sign map unit

108 interleave unit

110 frame main body processors

112 frame generators

114 signal conversion units

116 up-conversion unit

202 tuners

204 oscillators (OSC)

206 analog-to-digital converters (ADC)

208 carrier wave restorers

210 temporal frame skew/timing off-set (TFO/TO) restorers

212 pseudo random numbers (PN) synchronizer

214 fast fourier transformer (FFT)

216 channel estimating DFF/frequency-domain equalizers

218 central controllers

220 deinterleaving unit

222 separate map unit

224 reliabilitys improve the unit

226 forward error corrections (FEC) decoder

228 descrambler

2240 look-up tables

2241 counters

2242 synchronizing signal position controllers

2243 comparators

2244 multiplexers

2245 registers

TS original transmission signal stream

The SYNC synchronizing signal

LDC_PAR LDPC check bit

BCH_PAR BCH check bit

SYNC* scrambling synchronizing signal

The CR code rate

Claims

1. a reliability improves device, comprises:

Input is in order to received encoded signal;

Testing mechanism is in order to detect the known signal in the middle of the said code signal; And

Output when detecting said known signal, then uses the said known signal of Signal permuting that prestores, and is fed to decoder through said output; When not detecting said known signal, then said code signal directly is fed to said decoder through said output,

Wherein said known signal is the coordination signal.

2. reliability as claimed in claim 1 improves device, and wherein said code signal uses forward error correction (FEC) coding, and said forward error correction coding is low-density checksum (LDPC) coding.

3. reliability as claimed in claim 1 improves device, and wherein said code signal receives explains map unit (demapper) by oneself.

4. reliability as claimed in claim 3 improves device, and wherein said decoder and the said map unit of separating are positioned at digital ground multimedia broadcast (DTMB) receiving system.

5. a reliability improves device, comprises:

Counter is in order to the counting decoded positions;

The known signal positioner, it is according to code rate and modulation type, in order to confirm the known signal position;

Look-up table is in order to store the signal that prestores in advance;

Whether comparator is identical with said known signal position in order to judge said decoded positions; And

Multiplexer, when said comparator is judged to be when identical, the said signal that prestores that then said multiplexer will be stored in said look-up table is fed to decoder; When said comparator is judged to be not simultaneously, then said multiplexer is fed to said decoder with the code signal that receives,

Wherein said known signal is the coordination signal.

6. reliability as claimed in claim 5 improves device, and wherein said code signal uses forward error correction (FEC) coding, and said forward error correction coding is low-density checksum (LDPC) coding.

7. reliability as claimed in claim 6 improves device, and wherein said decoder is carried out LDPC decoding and BCH decoding.

8. reliability as claimed in claim 5 improves device, and wherein said code signal receives explains map unit (demapper) by oneself.

9. reliability as claimed in claim 8 improves device, and wherein said code rate and the input of said modulation type are from central processing unit.

10. reliability as claimed in claim 9 improves device, wherein said decoder, saidly separates map unit and said central processing unit is positioned at digital ground multimedia broadcast (DTMB) receiving system.

11. reliability as claimed in claim 5 improves device, wherein said modulation type is quadrature amplitude modulation (QAM) type.

12. reliability as claimed in claim 5 improves device, wherein also comprises register, is used for said code signal and is not fed to as yet before the said decoder, in order to deposit said code signal.