CN102768995A

CN102768995A - Memory device with external chip controller and manufacturing method of memory device

Info

Publication number: CN102768995A
Application number: CN2011101195126A
Authority: CN
Inventors: 陈士弘; 吕函庭; 谢光宇
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2011-05-06
Filing date: 2011-05-06
Publication date: 2012-11-07
Anticipated expiration: 2031-05-06
Also published as: CN102768995B

Abstract

The invention discloses an integrated circuit memory device and a manufacturing method thereof. The method and the device are applicable to low-cost processes, and the device comprises a memory circuit and a peripheral circuit. The memory circuit and the peripheral circuit of the device are positioned on different layers achieved in a laminated structure. A memory circuit layer and a peripheral circuit layer comprise complementary interconnection surfaces, and electrical interconnection can be established by the aid of matching of the complementary interconnection surfaces of the memory circuit and the peripheral circuit. Besides, the memory circuit layer and the peripheral circuit layer can be formed on different substrates respectively on different production lines by means of different processes. By the manufacturing means, the memory circuit layer and the peripheral circuit layer can be manufactured by using independent process equipment and technologies respectively, one process technology is used for manufacturing memory arrays, and the other process technology is used for manufacturing peripheral circuits. Further, the independent circuits can be laminated and bonded together.

Description

Storage arrangement and manufacturing approach thereof with chip outer controller

Technical field

The invention relates to a kind of integrated circuit memory devices (integrated circuit memorydevices) and manufacturing approach thereof.

Background technology

High density memory devices during fabrication, the amount of data storage of per unit area will be a key index on the integrated circuit.Therefore, when storage arrangement critical dimension technology had reached bottleneck, in order to reach every bigger storage density and to reduce every production cost, the mode of general recommendations was with multi-level memory cell lamination.In addition, new memory technology launches, and comprises phase transition storage (phasechange memory), ferromagnetic store (ferromagnetic memory), metal oxide type memory (metal oxide based memory) etc.

Memory technology needs a series of different process steps; It then is manufacturing for less important peripheral circuit; Peripheral circuit for example is address decoder (address decoders), state machine (statemachines), and command decoder (command decoder).Because memory array and peripheral circuit all need the support of manufacturing step, thus possibly compare costliness in order to the production line of execute store device, perhaps with the circuit of making peripheral circuit as compromise.So will cause using the technology of high-order more to make the integrated circuit of storage arrangement, and cause the technology cost to improve more.

Memory performance in integrated circuit promotes, and makes manufacturing cost increasingly high, must propose the integrated circuit memory structure of a low manufacturing cost.

Summary of the invention

In view of this, the invention provides a kind of integrated circuit memory devices, comprise a memory circuitry and a peripheral circuit, can use low-cost this integrated circuit memory devices of making.The memory circuitry and the peripheral circuit that are used for integrated circuit memory devices are to be implemented in different layers in laminated construction.Memory circuitry layer and peripheral circuit layer comprise interconnect surface, can set up the electric connection between memory circuitry and the peripheral circuit through the coupling of interconnect surface.Memory circuitry layer and peripheral circuit layer can utilize different processes to be formed at respectively on the different substrates in different line.Therefore, can use independently technology, a kind of technology is to be used for making memory array, and another kind of technology is in order to make peripheral circuit.Circuit separately can be then by lamination or be packaged together.

In the method for this illustrated manufacturing storage arrangement, comprise forming a memory circuitry that memory circuitry comprises a plurality of memory cell.Memory circuitry has one first interconnect surface, and first interconnect surface comprises first group of interconnect location.Interconnect location in first group of interconnect location is electrically coupled to corresponding memory cell in a plurality of memory cell.The method also comprises formation one peripheral circuit, and peripheral circuit provides an operational store circuit control signal.Peripheral circuit has one second interconnect surface, and second interconnect surface has second group of interconnect location.The method more comprises second interconnect surface of first interconnect surface to the peripheral circuit of connected storage circuit, makes first group of interconnect location in the interconnect location be electrically connected to the interconnect location of corresponding second group of interconnect location.

Comprise a memory circuitry in this described storage arrangement, memory circuitry comprises a plurality of memory cell.Memory circuitry has one first interconnect surface, and first interconnect surface comprises first group of interconnect location.Interconnect location in first group of interconnect location is electrically coupled to corresponding memory cell in a plurality of memory cell.Storage arrangement also comprises a peripheral circuit, and peripheral circuit provides control signal with the operational store circuit.Peripheral circuit has one second interconnect surface, and second interconnect surface has second group of interconnect location.Second interconnect surface of peripheral circuit is connected to first interconnect surface of memory circuitry in an interconnect interface, makes the interconnect location in the group interconnect location of winning be electrically coupled to the interconnect location in corresponding second group of interconnect location.

Content and claim scope graphic, that specify that the others of present technique and advantage will be chatted after can cooperating are understood.

Description of drawings

Fig. 1 illustrates the calcspar of the integrated circuit memory devices of a simplification, and integrated circuit memory devices comprises a memory circuitry and a peripheral circuit, is connected in an interconnect interface in this described memory circuitry and peripheral circuit.

Fig. 2 illustrates the calcspar of the memory circuitry of a simplification, and memory circuitry comprises one first group of memory cell and one second group of memory cell.

Fig. 3 illustrates the sketch map of the part of a typical storage arrangement, and storage arrangement has described interconnect surface.

Fig. 4 illustrates the layout of an embodiment of a memory circuitry, and it has illustrated the relation that is provided with of the lip-deep position that connects that connects.

Fig. 5 illustrates the profile of an embodiment of memory circuitry.

Fig. 6 to Fig. 8 illustrates the manufacturing flow chart of the storage arrangement of the integrated circuit that forms lamination, and integrated circuit memory devices is included in this a described memory circuitry and peripheral circuit.

Fig. 9 illustrates and sees through the intermediary layer sketch map of another embodiment of connected storage circuit to peripheral circuit indirectly.

Figure 10 illustrates the profile of an embodiment of a laminated construction, and this laminated construction comprises a plurality of memories lamination each other.

[main element symbol description]

100: device

110: memory circuitry

130,130-1,130-2: conductor

132,132-1,132-2,132a, 132b, 134,134a, 134b: interconnect location

160: memory array

160-1: first group of memory cell array

160-2: second group of memory cell array

161: column decoder

163: row decoder

165: bus

166: sensing amplifier/data input structure

168: bias voltage is provided with supply voltage

169: state machine

171: the data input

172: data output

174: other circuit

175: peripheral circuit

180,182: interconnect surface

181: interconnect interface

200: memory cell

210: word line

220: bit line

Embodiment

It is detailed in down that embodiments of the invention will cooperate pictorial image 1 to Figure 10 to do.

Fig. 1 illustrates the calcspar of the integrated circuit memory devices 100 of a simplification; Integrated circuit memory devices 100 comprises a memory circuitry 100 and a peripheral circuit 175; In this described memory circuitry and peripheral circuit is that physical property ground separates on the different layers that is arranged at device 100, and sees through an interconnect interface 181 connections each other." connected (joined) " or " connecting (joining) " in this employed vocabulary, the setting that is expression memory circuitry 110 is with attaching, fixing, or is connected to peripheral circuit 175 with the mode of other physical property.Memory circuitry 110 contained in this vocabulary is directly to be pasted to peripheral circuit 175, for example is to see through to engage (bonding).Memory circuitry 110 more contained in this vocabulary is to be configured to see through intermediary layer unit or the element between memory circuitry 110 and peripheral circuit 175, is connected to peripheral circuit 175 indirectly.

Memory circuitry 110 comprises a memory array 160.Word line (not showing) is to arrange along the row (columns) of memory array 160.Bit line (not showing) is to arrange along the row (rows) of memory array 160, in order to read and the memory cell (not showing) of programmable memory array 160." access line (access line) " normally representes bit line, source electrode line in this employed vocabulary, with and/or word line.Memory circuitry 110 can also comprise other circuit, for example is high voltage transistor or driver, when these circuit and memory array are arranged on the identical chip, more performance can be provided.

Memory circuitry 110 comprises an interconnect surface 182, and interconnect surface has one group of interconnect location 132.Interconnect location 132 be with memory circuitry 110 longitudinally the form of electrical interconnects interface define.Fig. 1 illustrates an interconnect surface 182 than the zonule, and interconnect surface 182 can comprise thousands of interconnect location 132.Interconnect location 132 is to see through conductor 130 to be coupled to corresponding access line in the memory array 160, thereby the specific row of memory array 160 or the selection of row are illustrated in down.

Memory array 160 can use various 2D or 3D memory construction to realize, comprises aforesaid mode.It for example is floating grid, charge trap, programming resistors and transformation or the like mutually that memory array 160 can also be utilized access technique; Realize with different types of memory cell; Different types of memory cell comprises different random access memory; Read-only memory, and other nonvolatile memory.In certain embodiments, memory array 160 is to utilize the laminated type thin-film transistor structure to realize, the laminated type thin-film transistor structure for example is like U.S. Patent number the 7th; 473; No. the 7th, 709,334, No. 589 and U.S. Patent number are said; These two pieces of contents that patent disclosed will be incorporated into this by reference.

Peripheral circuit 175 also comprises an interconnect surface 180, and interconnect surface 180 has one group of interconnect location 134.Interconnect location 134 be with peripheral circuit 175 longitudinally the form of electrical interconnects interface define.

Interconnect interface 181 is arranged between interconnect surface 182 and the interconnect surface 180, to electrically connect specific interconnect location 134 to corresponding interconnect location 132.Interconnect interface 181 also can be electrically insulated remaining interconnect location 132 and interconnect location 134.Thus, interconnect interface 181 longitudinally connects other access line of peripheral circuit 175 to memory array 160.

Peripheral circuit 175 provides control signal with operational store circuit 110, and control signal for example is bias voltage signal, clock signal, switch-over control signal etc.Peripheral circuit 175 comprises conductor 162, and conductor 162 sees through

complementary interconnect surface

182 and 180, and interconnect interface 181, is coupled to the word line of memory array 160.Conductor 162 extends to a column decoder 161.Conductor 164 sees through

interconnect surface

182 and 180, interconnect interface 181 and conductor 130, couples the bit line in row decoder 163 to the memory array 160.Position (addresses) to the column decoder 161 and the row decoder 163 of bus 165 are provided.In this embodiment, sensing amplifier and data input structure (data-instructures) 166 see through data/address bus 167 and are coupled to row decoder 163.Sensing amplifier in row decoder 163 and the square 166 can be arranged among the page buffer (page buffer structure), with the operation that allows to read extensively and abreast and write.Be utilized in the input/output end port on the integrated circuit memory devices, can see through the data input structure that Data In-Line road 171 provides data to square 166.In described embodiment; Other circuit 174 is included in peripheral circuit 175; Other circuit for example is the processor of general utility functions or the application circuit of specific function, or a kind of composite module, and module can provide the function of system-on-a-chip (system-on-a-chip) through memory array 160.See through DOL Data Output Line 172, the input/output end port on data to the peripheral circuit 175 of sense amplifying circuits of square 166 can be provided, perhaps to inside or other outside terminal of integrated circuit 175.

The realization of the controller among this embodiment; Be to use bias voltage that state machine (biasarrangement state machine) 169 is set and control the application that bias voltage is provided with supply voltage; It is to see through supply in Voltage Supply Device or the square 168 to provide or produce that bias voltage is provided with supply voltage, and it for example is to read and program voltage that bias voltage is provided with supply voltage.Then, see through interconnect surface 182, interconnect surface 180 and interconnect interface 181, provide the bias voltage setting to provide voltage and other to control signal to memory circuitry 110.Can use the logical circuit of known special purpose to realize controller.In another embodiment, controller comprises general processor, and general processor can be implemented among the peripheral circuit 175, peripheral circuit 175 can computer program with the operation of control device 100.In another embodiment, can combine the logical circuit of special purpose and general processor to combine to realize controller.

Can use various technology to come lamination peripheral circuit 175 and memory circuitry 110, set up the electrical interconnects of peripheral circuit 175 and memory circuitry 110 to see through interconnect interface 180.For instance, conductor material to interconnect surface 182 that can patternedization and interconnect surface 180 both one of, or be applied to interconnect surface 182 and interconnect surface 180 both.The conductor material that uses can be conduction adhesive agent or scolder.Can follow lamination peripheral circuit 175 and memory circuitry 110, make interconnect surface 182, interconnect surface 180 directly mate.In certain embodiments; Can use penetration silicon passage (Through-Silicon-Via; TSV) technology is carried out lamination and engagement step, and penetration silicon passage for example is like the United States Patent (USP) case the 7th, 683 of author for people such as Mr.s Ma; No. 459 said, among this will incorporate this paper by reference into.

In certain embodiments, interconnect interface 181 comprises a intermediary layer between interconnect surface 182 and interconnect surface 180.Intermediary layer can comprise that one has the Semiconductor substrate of metal level, and metal level is configured to the signal of conducting between interconnect surface, and intermediary layer comprises it for example being the structure of TSV technology, in order to contact point and another intermediary layer of the side that couples intermediary layer.Intermediary layer comprises relative both sides, has interconnect location respectively.Conducting element by the conductive path between the two opposite sides begin to extend interconnect location between.In certain embodiments, intermediary layer can comprise the circuit that adds, and for example amplifier, repeater (repeater), electricity are led (inductors), electric capacity and diode, to support signal contact and the impedance matching between stratiform memory and the peripheral circuit.

The separation of the physical property of memory circuitry 110 and peripheral circuit 175; Make and be able to both are made dividually on the technology; One technology is in order to make memory circuitry 110, and another technology is in order to make peripheral circuit 175 (can select whether still to need a technology in order to make intermediary layer).For instance, can use different process to make memory circuitry 110 and peripheral circuit 175 dividually on different substrates in different line.Therefore, can use simple logic process (logic onlyprocesses) to make peripheral circuit 175.Simple logic process for example is to be used for forming static RAM (Static Random Access Memory, technology SRAM) needn't look like relatively complicated traditional memory process and need combine logic/memory process.Present embodiment can be with design a high-effect peripheral circuit 175 than less cost.Likewise, can use the memory process technology to make memory circuitry 110, and need not consider the technology of peripheral circuit 175.

Even if add the cost that uses the required cost of joint technology, memory circuitry 110 and peripheral circuit 175 are made dividually, can reduce the cost net amount of each memory cell considerablely.For instance, suppose memory circuitry 110 and the peripheral circuit 175 identical chip area (diearea) that accounts for, and memory circuitry 110 and peripheral circuit 175 each other technology do not contain common step.Also suppose that memory circuitry 110 and peripheral circuit 175 both each need to form 20 layers material, the needed cost of each layer material cost $50 unit.Under such hypothesis, when memory circuitry 110 and peripheral circuit 175 were made together, the cost of each wafer was near (20*$50+20*$50)/1000, Ye Jiushi $2 unit.Relatively, form memory circuitry 110 and peripheral circuit 175 dividually, the cost of each wafer is near the cost of (20*$50/2000)+(20*$50/2000)+lamination and joint, and Ye Jiushi $1 unit adds the cost of the required cost of joint technology.Therefore, when the required cost Xiao Yu of bonded circuitry $1 unit, make memory circuitry 110 and peripheral circuit 175 dividually, can be lower in the cost of one chip than making memory circuitry 110 and peripheral circuit 175.

Memory circuitry 110 can also make its modularization out of the ordinary with the physical separation of peripheral circuit 175; Modularization for example is that different operating modes can be provided, and the different memory cell on the for example identical storage arrangement 100 is in order to carry out different read or write operations.Different operating modes makes different memory cell that different memory characteristics can be provided.

Fig. 2 illustrates the calcspar of the memory circuitry 110 of a simplification, and memory circuitry 110 comprises one first group of memory cell 160-1 and one second group of memory cell 160-2.As shown in Figure 2, first group of memory cell 160-1 can see through conductor 130-1 and be coupled to an interconnect surface 182-1, and interconnect surface 182-1 has one group of interconnect location 132-1.Second group of memory cell 160-2 can see through conductor 130-2 and be coupled to interconnect surface 182-2, and interconnect surface 182-2 has one group of interconnect location 132-2.Interconnect interface 181 between interconnect surface 182-1, interconnect surface 182-2 and interconnect surface 180 electrically connects specific interconnect location 134 to corresponding interconnect location 132-1 and interconnect location 132-2.

Peripheral circuit 175 produces in order to operate the operation signal of first group of memory cell 160-1 and second group of memory cell 160-2.Operation signal be control logic generation by peripheral circuit 175 with implement either operational mode, operator scheme for example is the read or write operation for first group of memory cell 160-1 and second group of memory cell 160-2.In this embodiment, 175 couples of first group of memory cell 160-1 of peripheral circuit and second group of memory cell 160-2 produce the different operation signal.For instance, 175 couples of first group of memory cell 160-1 of peripheral circuit produce the operation signal that the operation signal that carries out read operation may be different from 175 pairs of first group of memory cell 160-2 generations carrying out of peripheral circuit read operation.For instance, the difference between the operation signal possibly comprise the difference of one or more logic sequence (logic sequences) difference, instruction group (command sets), and the difference of clock signal (timing signals).

Can utilize different operating modes between first group of memory cell 160-1 and the second group of memory cell 160-2, so that different memory characteristics to be provided.For instance, first group of memory cell 160-1 and second group of memory cell 160-2 can have the set-up mode of different types of memory cell, different arrays, the size of different arrays, and/or comprise the material with different qualities.

For instance, first group of memory cell 160-1 can provide arbitrary access and so that the bit line and the word line of shorter length are provided with relatively.So set-up mode can provide high program/erase speed, for example can be applied to random access memory (RAM memory).It is anti-and (NAND) or anti-or (NOR) in the structure that second group of memory cell 160-2 can be arranged at, and have relatively long bit line and word line.So set-up mode can provide good array efficiency, for example can be applied in the flash memory.

See through the independently use of the module of interconnect surface 182-1 and interconnect surface 182-2, can also make and respectively organize memory cell and operate independently of one another.For instance, can carry out read operation, carry out a programming operation simultaneously and organize memory cell in another in one group of memory cell.The independent operation that cell group is carried out can also reduce the consumption of electric power.For instance, can be only electric power be offered the memory cell of the memory characteristics desiring to operate.

In certain embodiments, cell group 161-1 and 161-2 can share peripheral circuit 175 usually.Perhaps, similar module can be used for the part or all of circuit of peripheral circuit 175.For instance, peripheral circuit 175 comprises the sensing amplifier group, and the sensing amplifier group has the different operation characteristic, for example is to have different sensed speed.In when operation, can then one group of given sensing amplifier be connected or be located away from not memory cell on the same group, thereby many different operating modes are provided.

Fig. 3 illustrates the sketch map of the part of a typical laminated type integrated circuit memory devices 100, and storage arrangement 100 has described interconnect interface 181.In Fig. 3, the memory cell 200 in the memory array 160 is silica silicon oxynitride type (SONOS-type) charge trap memory cell.Perhaps, also can use the memory cell of other form and/or other form of memory array to be provided with.

Memory array 160 comprises many word lines 210, and word line 210 is to extend the direction parallel with first direction.As shown in Figure 3, the grid of memory cell 200 is connected to corresponding word line 210.Each word line 210 is to see through corresponding conductor 130 to be coupled to corresponding word line interconnect location 132a, and interconnect location 132a is positioned on the interconnect surface 182.Word line interconnect location 132a sees through interconnect interface 181 and is coupled to corresponding word line interconnect location 134a, and interconnect location 134a is positioned on the interconnect surface 180.Word line interconnect location 134a then sees through conductor 162 and is coupled to column decoder 161 (rowdecoder).See through this structure, column decoder 161 is in response to a bus, and this bus is the bus that applies voltages to the word line 210 of selection.The degree of the voltage that is applied and duration are relevant with performed operation, and the operational example of execution is a read operation or a programming operation in this way.

Memory array 160 can also comprise multiple bit lines 220, and bit line 220 extends the direction parallel with second direction.As shown in Figure 3, the source electrode of memory cell 220 and drain region are connected to corresponding bit line 220.Each bit line 220 sees through corresponding conductor 130 and is coupled to corresponding bit line interconnect location 132b, and bit-line interconnects position 132b is positioned on the interconnect surface 182.Bit-line interconnects position 132b sees through interconnect interface 181 to be coupled to corresponding bit line interconnect location 134b, and bit-line interconnects position 134b is positioned on the interconnect surface 180.Bit-line interconnects position 134b sees through conductor 164 and is coupled to row decoder (column decoder) 163.See through this structure, row decoder 163 is in response to a bus, and this bus is the bus that applies voltages to the bit line 220 of selection.

Fig. 4 illustrates the layout of an embodiment of memory circuitry 130, and wherein, the position 132 that connects on the surface 182 that connects is connected to memory array 160.Fig. 5 illustrates among the embodiment of memory circuitry 130, along X-X ' profile of word line 210.

In described embodiment, bit line 220 is arranged on the word line 210.Contact plunger (for example being 310) is connected to bit line 220 to be arranged on the interconnect location 132, and interconnect location 132 is positioned on the interconnect surface 182.In this embodiment, bit-line interconnects position 132b directly is contacted with corresponding bit line interconnect location 134b, and bit-line interconnects position 134b is positioned on the interconnect surface 180 of peripheral circuit 175.As aforementioned, see through this structure, row decoder 163 is coupled to conductor 164, to provide voltage to the bit line of selecting 220.

Contact plunger (for example being 320) is connected to word line 210 to corresponding conductive extension (for example being 330).Corresponding conductive extension extends the direction of parallel wordlines 210 and is arranged on the bit line 220.Contact plunger (for example being 340) then connects conductive extension to corresponding word line interconnect location 132a, and word line interconnect location 132a is positioned on the interconnect surface 182.As aforementioned, see through this structure, column decoder 161 is in response to the bus of the word line that applies voltages to selection 210.Ground connection can also be coupled to memory circuitry 110 with the similar mode required like being provided with of memory circuitry 110 with other decoder.

As shown in Figure 4, many word line interconnect location 132a are that distributed earth is connected to each word line 210.Same, multiple bit lines link position 132b can be connected to bit line 220.These extra vertical interconnection can be used as subsequent use so that redundant (redundancy) to be provided, to promote fine ratio of product.For instance, when finding wrong position (fail bit), can error bit address (fail bit address) be pointed to these subsequent use bit lines, and then promote the yield when making.

Fig. 6 to Fig. 8 illustrates the manufacturing flow chart of the storage arrangement 100 that forms the laminated type integrated circuit, and integrated circuit memory devices 100 is included in this a described memory circuitry 110 and peripheral circuit 175.

Fig. 6 is illustrated in the result who forms a plurality of memory circuitries 110 on first substrate.For instance, first substrate 400 can comprise polysilicon or other semi-conducting material.Perhaps, first substrate 400 also can comprise the non-semiconductor material, for example is silicon dioxide (SiO ₂), carborundum (SiC), silicon nitride (SiN) or cyclic resin (epoxy).In another embodiment, first substrate 400 can comprise the flexible substrate material, for example is plastic material.In certain embodiments, first substrate comprises can reusable substrate, and the memory circuitry 110 that adds one after the other is formed on the reusable substrate.Though there is thousands of memory circuitry 110 can be formed on first substrate 400, yet, for the purpose of showing only shows two memory circuitries 110 in Fig. 6.

Know like technical field under the present invention, can use standard technology memory circuitry 110 to form memory circuitry.Generally speaking; Memory circuitry can comprise memory cell, access line (for example being word line), bit line and source electrode line, conductor connector (conductive plugs), the semi-conducting material that mixes, advanced person's storage material (advance memory materials); For example phase change materials, ferrimagnet (ferromagnetic materials), high-k material (high-k dielectrics) etc., and other is used for the structure of memory circuitry.In certain embodiments, memory circuitry 110 comprises word line driver and bit-line pre-charge circuit (bit line precharge circuitry).In certain embodiments, part or all of decoder circuit can be formed on the memory circuitry.In other embodiment, for example be aforesaid embodiment, memory circuitry 110 does not comprise decoder circuit.

Can realize memory circuitry 110 with 2 different dimensions or 3 dimension memory constructions, comprise foregoing structure.Memory array 160 can also realize that these different memory cell comprise read-only memory, floating grid and charge trap etc. with various memory cell.In certain embodiments, memory circuitry 110 is to form with the laminated type thin-film transistor technologies, and the laminated type thin-film transistor technologies for example is like U.S. Patent number the 7th; 473; No. the 7th, 709,334, No. 589 and U.S. Patent number are said; In this, in the explanation of front, the content that it disclosed is incorporated among this paper by reference.

Like the formation of memory circuitry partly, a kind of interconnection mode comprises the position of the perforate in the memory circuitry 110 being located at interconnect location 132.Contact plunger can be formed among the perforate, makes contact plunger correspond to the access line in the memory circuitry 110.Then the interconnect location 132 of patterning stack to be being contacted with contact plunger, thereby forms interconnect surface 182.Interconnect surface 182 can comprise thousands of interconnect location 132.Yet, in order to show that clearly Fig. 6 does not illustrate with the dimension of reality, and only illustrates a little interconnect location 132.

Fig. 7 illustrates peripheral circuit 175 and is formed at the result on one second substrate 410.Peripheral circuit 175 is configured to provides control circuit, and control circuit for example is bias voltage signal, clock signal etc., is used for the operation of memory circuitry 110.On production line, can utilize logic process to make peripheral circuit 175 with optimization technology.For instance; Peripheral circuit 175 can comprise that decoder circuit, page buffer, charge pump circuit (charge pumping circuits), controller (for example being state machine), other memory circuitry (for example be the static RAM that is used for high-speed cache, the processor of general objects or the application circuit of specific purposes, and other are functionally supported the known circuit of integrated circuit memory.Can use the aforementioned technology that is same as, be coupled to corresponding contact plunger to form interconnect location 134 in order to manufacturing interconnect location 132.

Fig. 8 illustrates the directly result of the interconnect surface 180 of interconnect surface 182 to the peripheral circuit 175 of connected storage circuit 110.Such connected mode provides specific interconnect location 134 to be electrically connected to corresponding interconnect location 132.This connected mode also provides interconnect location 132 and interconnect location 134 being electrically insulated each other.Thus, peripheral circuit 175 longitudinally is connected to each access line of memory array 160.

Can use various technology to connect peripheral circuit 175 and memory circuitry 110, comprise aforesaid vertical electrical interconnects with foundation.

In this embodiment, no matter have or do not have intermediary layer, memory circuitry 110 can oppositely be arranged on the peripheral circuit 175.Perhaps, no matter have or do not have intermediary layer, peripheral circuit 175 can be arranged on the memory circuitry 110.

Fig. 9 illustrates among another embodiment, and memory circuitry 110 sees through intermediary layer 800 to be connected to peripheral circuit 175 indirectly.In this situation, memory circuitry 110 and peripheral circuit 175 are to see through intermediary layer 800 to connect.

A plurality of memory circuitries 110 are lamination each other also, makes memory circuitry 110 before being connected with peripheral circuit 175, be single device.The profile of one typical laminated construction 900 is to be illustrated among Figure 10.For instance, can utilize the TSV technology to form opening 910 with each memory circuitry 110 that interconnects, opening 910 is fully to run through laminated construction 900.In other embodiments, one or more get in the several layers of laminated construction that can be included in like Figure 10 of memory circuitry layer and peripheral circuit.

In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Those skilled in the art are not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defined.

Claims

1. the manufacturing approach of a storage arrangement comprises:

Form a memory circuitry; This memory circuitry comprises a plurality of memory cell; This memory circuitry has one first interconnect surface; This first interconnect surface has one first group of interconnect location, and a plurality of interconnect location of this first group of interconnect location are electrically coupled to corresponding memory cell in these a plurality of memory cell;

Form a peripheral circuit, this peripheral circuit provides in order to operate the control signal of this memory circuitry, and this peripheral circuit has one second interconnect surface, and this second interconnect surface has one second group of interconnect location; And

This second interconnect surface that connects this first interconnect surface to this peripheral circuit of this memory circuitry.

2. method according to claim 1, wherein this first interconnect surface and this second interconnect surface ways of connecting are arranged on this first interconnect surface for this second interconnect surface.

3. method according to claim 1, wherein:

The step that forms this memory circuitry comprises carries out one first technology to form these a plurality of memory cell on one first substrate; And

The step that forms this peripheral circuit comprises carries out one second technology to form this peripheral circuit on one second substrate, and this second technology and this first technology are inequality.

4. method according to claim 1, wherein:

The step that forms this memory circuitry comprises that this memory circuitry of formation is in one first substrate; And

The step that forms this peripheral circuit comprises this peripheral circuit of formation in one second substrate, and this second substrate and this first substrate are provided with dividually.

5. method according to claim 1, wherein this Connection Step comprises and directly engages this first interconnect surface to this second interconnect surface.

6. method according to claim 1; Wherein this first group of interconnect location is on this first interconnect surface, to be arranged to a pattern; This pattern is set another pattern that forms of this second group of interconnect location that corresponds on this second interconnect surface; Make that these a plurality of interconnect location in this first group of interconnect location are able to be aligned in pairing a plurality of interconnect location in this second group of interconnect location when connecting this first interconnect surface to this second interconnect surface.

7. method according to claim 1, the step that wherein connects this first interconnect surface to this second interconnect surface more comprises:

This first interconnect surface to an intermediary layer that connects this memory circuitry makes that these a plurality of interconnect location in this first group of interconnect location are electrically coupled to corresponding a plurality of conducting elements on this intermediary layer; And

This second interconnect surface that connects this peripheral circuit makes that to this intermediary layer a plurality of interconnect location in this second group of interconnect location are electrically coupled to corresponding a plurality of conducting elements on this intermediary layer.

8. method according to claim 1, wherein:

Form this memory circuitry and comprise with the step that forms this peripheral circuit, form this memory circuitry and this peripheral circuit one of them on a substrate, and remove this memory circuitry and this peripheral circuit this one of them in this substrate; And

The step that connects this first interconnect surface to this second interconnect surface comprises; When remove this memory circuitry and this peripheral circuit this one of them behind this substrate, mate this memory circuitry and this peripheral circuit this one of them to another memory circuitry and another peripheral circuit.

9. method according to claim 1; Wherein this peripheral circuit produces a plurality of first operation signals to operate one first memory cell in these a plurality of memory cell; And this peripheral circuit produces a plurality of second operation signals to operate one second memory cell in these a plurality of memory cell, and these a plurality of first operation signals are different from this a plurality of second operation signals.

10. method according to claim 1, wherein:

This memory circuitry comprises one first array and one second array in this a plurality of memory cell in these a plurality of memory cell, and this first array and this second array have independently access line and different access sequential; And

This peripheral circuit applies different sequential to this first array and this second array.

11. method according to claim 1, wherein this memory circuitry more comprises many access lines, and these a plurality of interconnect location in this first group of interconnect location see through these a plurality of access lines and are electrically coupled to this a plurality of corresponding memory cell.

12. a storage arrangement comprises:

One memory circuitry; Comprise a plurality of memory cell; This memory circuitry has one first interconnect surface, and this first interconnect surface has one first group of interconnect location, and a plurality of interconnect location in this first group of interconnect location are electrically coupled to corresponding memory cell in these a plurality of memory cell; And

One peripheral circuit, in order to provide a plurality of control signals to operate this memory circuitry, this peripheral circuit has one second interconnect surface, and this second interconnect surface has one second group of interconnect location;

Wherein this second interconnect surface of this peripheral circuit is connected to this first interconnect surface of this memory circuitry in an interconnect interface.

13. device according to claim 12, wherein this second interconnect surface is arranged on this first interconnect surface.

14. device according to claim 12, wherein:

The a plurality of memory cell of this of many access lines and this memory circuitry are to be formed on one first substrate by one first technology; And

This peripheral circuit is to be formed on this second substrate by one second technology, and this second technology is different from this first technology.

15. device according to claim 12, wherein this second interconnect surface is directly to be engaged in this first interconnect surface.

16. device according to claim 12; Wherein this first group of interconnect location is on this first interconnect surface, to be arranged to a pattern; This pattern is set another pattern that forms of this second group of interconnect location that corresponds on this second interconnect surface; Make that these a plurality of interconnect location in this first group of interconnect location are able to be aligned in pairing a plurality of interconnect location in this second group of interconnect location when connecting this first interconnect surface to this second interconnect surface.

17. device according to claim 12 more comprises an intermediary layer, this intermediary layer has one first side and one second side, and a plurality of conducting element extends between this first side and this second side, wherein

This of this memory circuitry first interconnect surface is connected to this first side of this intermediary layer, makes these a plurality of interconnect location in this first group of interconnect location be electrically coupled to corresponding a plurality of conducting elements on this first side of this intermediary layer; And

This of this peripheral circuit second connects second side that the surface is connected to this intermediary layer, makes a plurality of interconnect location in this second group of interconnect location be electrically coupled to corresponding a plurality of conducting elements on this second side of this intermediary layer.

18. device according to claim 12; Wherein this peripheral circuit produces a plurality of first operation signals to operate one first memory cell in these a plurality of memory cell; And this peripheral circuit produces a plurality of second operation signals to operate one second memory cell in these a plurality of memory cell, and these a plurality of first operation signals are different from this a plurality of second operation signals.

19. device according to claim 12, wherein:

This memory circuitry comprises one first array of these a plurality of memory cell and one second array of these a plurality of memory cell, and this first array and this second array have independently access line and different access sequential; And

20. device according to claim 12, wherein this memory circuitry more comprises a plurality of access lines, and these a plurality of interconnect location in this first group of interconnect location see through these a plurality of access lines and are electrically coupled to this a plurality of corresponding memory cell.