CN102768987A

CN102768987A - Airspace manufacturing method for damascene process

Info

Publication number: CN102768987A
Application number: CN2012102282751A
Authority: CN
Inventors: 梁学文; 陈玉文; 胡友存; 姬峰; 李磊
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2012-07-04
Filing date: 2012-07-04
Publication date: 2012-11-07

Abstract

The invention provides an airspace manufacturing method for a damascene process. The method comprises the following steps of depositing a first dielectric layer on a substrate, etching the first dielectric layer to form a first groove pattern, and depositing a first isolating layer; removing the first isolating layer at the bottom of the first groove; forming a first copper interconnection line on the first dielectric layer and the first isolating layer; removing the first isolating layer to form a first airspace. The method provided by the invention is simple and easy to perform; the airspace is formed on the side wall of the copper interconnection line, so that a copper interconnection resistor capacitor (RC) delay problem can be effectively improved.

Description

A kind of airspace manufacture method that is used for Damascus technics

Technical field

The present invention relates to a kind of airspace manufacture method, relate in particular to a kind of airspace manufacture method that is used for Damascus technics.

Background technology

Along with the semiconductor integrated circuit characteristic size continue reduce, back segment interconnection RC postpones the influence of the operational effectiveness of integrated circuit remarkable day by day.Postpone in order to reduce back segment interconnection RC, copper-connection replaces the aluminium interconnection becomes main flow technology, and introduces low-k (Low-k) material.Because the desired dielectric constant of air approaches 1, therefore using air also is one of solution that reduces parasitic capacitance between plain conductor as metal interconnected megohmite insulant.Though the technology that many low-k characteristics of utilizing air are applied to integrated circuit comes forth out.But a lot of metal interconnected, and can't obtain enough supports almost completely by built on stilts, cause integrated circuit to receive mechanical force easily and damage.

Therefore, those skilled in the art is devoted to develop a kind of airspace manufacture method that is used for Damascus technics of the integrated circuit that has the airspace and enough support.

Summary of the invention

In view of above-mentioned the problems of the prior art, technical problem to be solved by this invention is that existing technology lacks the airspace manufacture method that has the airspace and enough support.

A kind of airspace manufacture method that is used for Damascus technics provided by the invention may further comprise the steps:

Step 1, deposit first dielectric layer on matrix, etching first dielectric layer is to form first channel patterns, deposit first separator;

Step 2 is removed first separator of first channel bottom;

Step 3 forms first copper interconnecting line on first dielectric layer and first separator;

Step 4 is removed first separator, forms first airspace.

In a preferred embodiments of the present invention, also comprise:

Step 5, deposit second dielectric layer, etching forms second channel patterns, deposit second separator, and remove second separator of second channel bottom;

Step 6 forms first through hole, and forms second copper interconnecting line on second dielectric layer;

Step 7 is removed second separator, forms second airspace.

In another preferred embodiments of the present invention, first dielectric layer in the said step 1 is processed by advanced low-k materials.

In another preferred embodiments of the present invention, first dielectric layer in the said step 1 forms through chemical vapour deposition (CVD).

In another preferred embodiments of the present invention, first separator in the said step 1 is processed by tetraethoxysilane.

In another preferred embodiments of the present invention, first copper interconnecting line in the said step 3 is filled copper formation through deposit first metal barrier with electroplating.

In another preferred embodiments of the present invention, said first metal barrier is processed by among TiN, Ti, TaN, Ta, WN, the W one or more.

In another preferred embodiments of the present invention, remove first separator through wet etching in the said step 4.

In another preferred embodiments of the present invention, the selected solvent of said wet etching is a hydrogen fluoride solution.

In another preferred embodiments of the present invention, form first through hole through photoetching process in the said step 6.

Of the present invention method is simple, in the sidewall formation airspace of copper interconnecting line, can effectively improve copper-connection RC delay issue.

Description of drawings

Fig. 1 is the sketch map that embodiments of the invention form first groove;

Fig. 2 is the sketch map that embodiments of the invention are removed bottom first separator;

Fig. 3 is the sketch map that embodiments of the invention form first metal barrier;

Fig. 4 is the sketch map that embodiments of the invention form first copper interconnecting line;

Fig. 5 is the sketch map that embodiments of the invention form first airspace;

Fig. 6 is the sketch map that embodiments of the invention form second groove;

Fig. 7 is the sketch map that embodiments of the invention are removed bottom second separator;

Fig. 8 is the sketch map that embodiments of the invention form through hole;

Fig. 9 is the sketch map that embodiments of the invention form first through hole;

Figure 10 is the sketch map that embodiments of the invention form second metal barrier;

Figure 11 is the sketch map that embodiments of the invention form second copper interconnecting line;

Figure 12 is the sketch map that embodiments of the invention form second airspace.

Embodiment

Below will combine accompanying drawing that the present invention is done concrete explaination.

A kind of airspace manufacture method that is used for Damascus technics of embodiments of the invention may further comprise the steps:

Step 1, as shown in fig. 1, first dielectric layer of on a matrix 1, processing 2 (like SiOCH) through CVD (Chemical Vapor Deposition, chemical vapour deposition (CVD)) deposit advanced low-k materials; Form first groove, 3 figures through single Damascus etching technics; Deposit first separator 4 (only surrounding structure is caused the not even material that destroys of precocity of less destruction when one or more layers is prone to remove and remove through the CVD deposit, as TEOS etc.).

Step 2 as shown in Figure 2, is removed first separator of first groove, 3 bottoms.

Step 3, as shown in Figure 3, deposit first metal barrier 5 (physical vapor deposition (PVD) or CVD or ald (ALD) deposit TiN, Ti, TaN, Ta, WN, W etc. one or more); Electroplate and fill metallic copper; And as shown in Figure 4, cmp (CMP) is removed metallic copper on first dielectric layer 2, forms first copper interconnecting line 6.

Step 4 as shown in Figure 5, is removed first separator 4, forms first airspace 7.

Step 5, as shown in Figure 6, at first copper interconnecting line, 6 CVD barrier layer (NDC) and low-k second dielectric layer 8 (SiOCH); Adopt full groove preferential (Full Trench First, dual damascene etching technics FTF) forms second groove 9; Deposit second separator 10 (one or more layers only causes the not even material that destroys of precocity of less destruction to surrounding structure when being prone to remove and remove the CVD deposit, as TEOS etc.).

And as shown in Figure 7, remove second separator of second channel bottom 9.

Step 6 as shown in Figure 8, forms the pattern of through hole through photoetching process on photoresist 11; As shown in Figure 9, on second dielectric layer 8, form first through hole 12 (Via) and remove photoresist through etching technics.

As shown in Figure 10, deposit second metal barrier 13 (PVD or CVD or ALD deposit TiN, Ti, TaN, Ta, WN, W etc. one or more); Electroplate and fill metallic copper; As shown in Figure 11, cmp (CMP) is removed metallic copper on second dielectric layer 8, forms second copper interconnecting line 14.

Step 7 adopts wet-etching technique, removes second separator 10, forms second airspace 15 (air gap).Selected solvent will make second separator 10 and on every side metal barrier, copper, second dielectric layer 8 etc. that higher selection ratio is arranged, like the hydrogen fluoride solution (DHF) of dilution.

Embodiments of the invention can be on second airspace CVD barrier layer (NDC) and low-k the 3rd dielectric layer (SiOCH), repeat the second metal level manufacturing process and form the 3rd airspace; Even more multi-layer air is at interval.

More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.

Claims

1. an airspace manufacture method that is used for Damascus technics is characterized in that, may further comprise the steps:

Step 2 is removed first separator of first channel bottom;

Step 4 is removed first separator, forms first airspace.

2. the method for claim 1 is characterized in that, also comprises:

Step 7 is removed second separator, forms second air gap.

3. the method for claim 1 is characterized in that, first dielectric layer in the said step 1 is processed by advanced low-k materials.

4. the method for claim 1 is characterized in that, first dielectric layer in the said step 1 forms through chemical vapour deposition (CVD).

5. the method for claim 1 is characterized in that, first separator in the said step 1 is processed by tetraethoxysilane.

6. the method for claim 1 is characterized in that, first copper interconnecting line in the said step 3 is filled copper formation through deposit first metal barrier with electroplating.

7. method as claimed in claim 6 is characterized in that, said first metal barrier is processed by among TiN, Ti, TaN, Ta, WN, the W one or more.

8. the method for claim 1 is characterized in that, removes first separator through wet etching in the said step 4.

9. method as claimed in claim 8 is characterized in that, the selected solvent of said wet etching is a hydrogen fluoride solution.

10. method as claimed in claim 2 is characterized in that, forms first through hole through photoetching process in the said step 6.