CN102760397A - Drive circuit - Google Patents
Drive circuit Download PDFInfo
- Publication number
- CN102760397A CN102760397A CN2011101157618A CN201110115761A CN102760397A CN 102760397 A CN102760397 A CN 102760397A CN 2011101157618 A CN2011101157618 A CN 2011101157618A CN 201110115761 A CN201110115761 A CN 201110115761A CN 102760397 A CN102760397 A CN 102760397A
- Authority
- CN
- China
- Prior art keywords
- electric crystal
- utmost point
- signal
- couples
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a drive circuit, which comprises a plurality of shifting registers which are serially connected, and each shifting register comprises multiple transistors and multiple capacitors. The drive circuit has the advantages of simple structure and low noise output, and is capable of reducing oscillation amplitude of a signal source for restraining the drifting of a critical voltage, and thus prolonging the effective operation time of the circuit.
Description
Technical field
The present invention is about a kind of driving circuit, in particular to a kind of degree of stability and driving circuit of effective running time of membrane transistor (TFT) that promotes output waveform.
Background technology
In recent years, for reducing the cost of panel, the gate drive circuit of active LCD adopts the membrane transistor technical design to become the trend of main flow gradually.Yet; The drift that the amorphous silicon membrane transistor element can produce critical voltage because long use or high forward bias apply; Cause the current driving capability of membrane transistor (Thin-Film Transistor is hereinafter to be referred as TFT) significantly to reduce, make the output waveform distortion of driving circuit; And then have influence on the degree of stability of driving circuit, and cause the display quality of picture to descend.
In addition; Because the signal source that gate drive circuit provided is periodic alternating voltage signal, therefore, when voltage signal is changed; If output node is the state of suspension joint (floating); Then be easy to generate capacitance coupling effect (capacitor coupling effect), make drive wire institute output waveform that fluctuation take place and let image display quality descend, even cause the situation of not action to take place.
In view of traditional method does not have the degree of stability and the effective running time of TFT of effective lifting output waveform, so need the driving circuit that proposes a kind of novelty badly, can be used for promoting the degree of stability and the effective running time of TFT of output waveform.
Summary of the invention
One of the present invention purpose is to provide one drive circuit, and it has simple architecture and the low noise of output, can be used for promoting the degree of stability of output waveform and the fiduciary level of TFT.
Another object of the present invention is to, by the voltage swing that reduces signal source, the drift of membrane transistor critical voltage also is suppressed simultaneously, guarantees to prolong the operational use time of circuit.
The present invention provides a kind of driving circuit, and it comprises: a plurality of shift registers and the electric capacity of serial connection.Each shift register also comprises in a plurality of shift registers of this serial connection: first electric crystal, and it comprises first utmost point, second utmost point and gate, wherein first utmost point of this first electric crystal couples with the gate of this first electric crystal mutually; Second electric crystal, it comprises first utmost point, second utmost point and gate, wherein the gate of this second electric crystal couples first utmost point coupled with first signal of second utmost point and this second electric crystal of this first electric crystal; The 3rd electric crystal, it comprises first utmost point, second utmost point and gate, wherein the gate of the 3rd electric crystal couples second utmost point of this second electric crystal and first utmost point of the 3rd electric crystal couples secondary signal; The 4th electric crystal, it comprises first utmost point, second utmost point and gate, and wherein second utmost point of the 4th electric crystal couples the 3rd signal, and first utmost point that the gate of the 4th electric crystal couples the 4th signal and the 4th electric crystal couples second utmost point of this second electric crystal; The 5th electric crystal, it comprises first utmost point, second utmost point and gate, and wherein the gate of the 5th electric crystal couples the 4th signal, and first utmost point of the 5th electric crystal couples second utmost point of the 3rd electric crystal and second utmost point of the 5th electric crystal couples the 3rd signal; The 6th electric crystal, it comprises first utmost point, second utmost point and gate, wherein first utmost point of the 6th electric crystal couples second utmost point of this first electric crystal and second utmost point of the 6th electric crystal couples the 3rd signal.This electric capacity comprises first end and second end, and wherein first end of this electric capacity second end that couples first utmost point and this electric capacity of the 6th electric crystal couples first utmost point of the 5th electric crystal.
Like described driving circuit; It also comprises: the 7th electric crystal; It comprises first utmost point, second utmost point and gate; Wherein the gate of the 7th electric crystal couples the 4th signal, and second utmost point that first utmost point of the 7th electric crystal couples second utmost point and the 7th electric crystal of this second electric crystal couples second end of this electric capacity.
Like described driving circuit, this first utmost point of this first electric crystal also receives the output signal of being seen off by previous shift register.
Like described driving circuit, this gate of the 6th electric crystal also receives the output signal of being seen off by a back shift register.
Like described driving circuit, this first signal and this secondary signal are the positive direct-current source, and the 3rd signal is negative DC source/ground connection, and accurate position greater than this secondary signal, the position of this first signal is accurate.
Like described driving circuit; Odd bits shift register in these a plurality of shift registers; The 4th signal that it received is a clock signal, and the even bit shift register in these a plurality of shift registers, the 4th signal that it received is this clock signal of anti-phase.
Like described driving circuit, this shift register circuit is arranged on the glass substrate.
Like described driving circuit, this first to the 6th electric crystal is amorphous silicon membrane electric crystal or NMOS electric crystal.
Like described driving circuit, the 7th electric crystal is amorphous silicon membrane electric crystal or NMOS electric crystal.
Can further be understood by following description of drawings and embodiment detailed description in advantage of the present invention and spirit.
Description of drawings
Fig. 1 is the one drive circuit 1 that shows according to one embodiment of the invention.
Fig. 2 shows according to shift register 15 of the present invention.
Fig. 3 is the sequential chart of display operation shift register 15 of the present invention.
Embodiment
Below will be with reference to the graphic the present invention of description who encloses for reaching employed technological means of purpose and effect, and below graphic cited embodiment be merely aid illustration, understand in order to the juror, but that the technological means of this case is not limited to is cited graphic.
Fig. 1 is the inside structure that shows LCD 1; Comprise: membrane transistor display panels 11, data driving circuit 12, driving circuit 13 and time schedule controller 14, wherein time schedule controller 14 is in order to receive a plurality of shift registers 15 that control signal and driving circuit 13 comprise serial connection.Is traditional electronic installation about membrane transistor display panels 11, data driving circuit 12 with time schedule controller 14, therefore, will repeat no more in this.
Fig. 2 shows that it comprises according to shift register 15 of the present invention: the first electric crystal Q1, and this first electric crystal Q1 comprises first utmost point, second utmost point and gate, wherein first utmost point of the first electric crystal Q1 couples with gate mutually; The second electric crystal Q2, it comprises first utmost point, second utmost point and gate, wherein this gate of this second electric crystal Q2 couples this second utmost point of this first electric crystal and this first utmost point coupled with first signal V of this second electric crystal Q2
DD1The 3rd electric crystal Q3, it comprises first utmost point, second utmost point and gate, wherein the gate of the 3rd electric crystal Q3 couples second utmost point of the second electric crystal Q2 and first utmost point of the 3rd electric crystal couples secondary signal V
DD2The 4th electric crystal Q4; It comprises first utmost point, second utmost point and gate; Wherein this gate of the 4th electric crystal Q4 couples the 4th signal CLK, and first utmost point of the 4th electric crystal Q4 couples second utmost point of the second electric crystal Q2 and second utmost point of the 4th electric crystal Q4 couples the 3rd signal V
SSThe 5th electric crystal Q5; It comprises first utmost point, second utmost point and gate; Wherein the gate of the 5th electric crystal Q5 couples the 4th signal CLK, and first utmost point of the 5th electric crystal Q5 couples this second utmost point of the 3rd electric crystal Q3 and second utmost point of the 5th electric crystal Q5 couples the 3rd signal VSS; The 6th electric crystal Q6, it comprises first utmost point, second utmost point and gate, wherein first utmost point of the 6th electric crystal Q6 couples second utmost point of the first electric crystal Q1 and second utmost point of the 6th electric crystal Q6 couples the 3rd signal V
SSAnd capacitor C 1, it comprises first end and second end, wherein first end of capacitor C 1 second end that couples first utmost point and this capacitor C 1 of the 6th electric crystal Q6 couples first utmost point of the 5th electric crystal Q5.Above-mentioned shift register 15 also comprises: the 7th electric crystal Q7; The 7th electric crystal Q7 comprises first utmost point, second utmost point and gate; Wherein the gate of the 7th electric crystal Q7 couples the 4th signal CLK, and first utmost point of the 7th electric crystal Q7 couples second end of second utmost point coupling capacitance C1 of second utmost point and the 7th electric crystal Q7 of the second electric crystal Q2.What need explanation is that first utmost point of the first electric crystal Q1 also receives the output signal OUT (n-1) that is seen off by previous shift register, and the gate of the 6th electric crystal Q6 also receives the output signal OUT (n+1) that is seen off by a back shift register.In addition, first and second signal V
DD1, V
DD2Be the positive direct-current source, and the 3rd signal V
SSBe negative DC source/ground connection, and the first signal V
DD1The position accurate greater than secondary signal V
DD2The accurate and a plurality of shift registers 15 in position in the odd bits shift register; The 4th signal CLK that it received is a clock pulse signal; And the even bit shift register in these a plurality of shift registers, the 4th signal that it received is this clock signal of anti-phase.In addition, shift register circuit 15 is arranged on the glass substrate (not shown), and the electric crystal that is arranged in the shift register circuit 15 can be amorphous silicon membrane electric crystal or NMOS electric crystal.
Fig. 3 is the sequential chart of display operation shift register 15 of the present invention.Please consult Fig. 1 simultaneously.At first, in this embodiment, shift register 15 of the present invention is the odd bits shift register in the driving circuit 1, and predeterminable V
DD2With V
SSVoltage be individually 20 volts (Voltage), and V
DD1For less than V
DD2Arbitrary power supply and CLK signal be 5 volts (VH).When in the time T of the 4th signal CLK
1The time, the first electric crystal Q1 receives the output signal OUT of previous shift register
(n-1), in order to driving the second electric crystal Q2 and the 3rd electric crystal Q3, and export signal OUT in time T 2
(n), this moment, capacitor C 1 was in charged state.Further, shift register 15 of the present invention is through the input signal OUT of previous shift register
(n-1), the first electric crystal Q1, the second electric crystal Q2 and the 3rd electric crystal Q3 in order to the output waveform that draws high (pull up) shift register 15 to noble potential.And when capacitor C 1 is in discharge condition, shift register 15 of the present invention through the 4th electric crystal Q4, the 5th electric crystal Q5 and the 6th electric crystal Q6 in order to drag down (pull down) in a Q
(n)On output waveform to electronegative potential.In addition, the 7th electric crystal Q7 can avoid a G
(n)On have the phenomenon of suspension joint and protect the 4th electric crystal Q4 and the 3rd electric crystal Q3 discharges and recharges when conversion in capacitor C 1, can keep conducting state.In addition, capacitor C 1 of the present invention has capacity coupled effect, and it can guarantee that the second electric crystal Q2 maintains linear zone work when capacitor C 1 charging.Then, in time T
3The time, receive back one and move the output signal OUT that deposits working storage
(n+1), in order to replacement shift register 15.
According to another embodiment of the present invention, shift register 15 of the present invention is the even bit shift register in the driving circuit 1, and predeterminable V
DD2With V
SSVoltage be individually 20 volts (Voltage), and V
DD1For less than V
DD2Arbitrary power supply.When in the 4th signal of anti-phase
Time T
1The time, the first electric crystal Q1 receives the output signal OUT of previous shift register
(n-1), in order to driving the second electric crystal Q2 and the 3rd electric crystal Q3, and in time T
2Output signal output OUT
(n), this moment, capacitor C 1 was in charged state.Further, shift register 15 of the present invention is through the input signal OUT of previous shift register
(n-1), the first electric crystal Q1, the second electric crystal Q2 and the 3rd electric crystal Q3 in order to the output waveform that draws high (pull up) shift register 15 to noble potential.And when capacitor C 1 is in discharge condition, shift register 15 of the present invention through the 4th electric crystal Q4, the 5th electric crystal Q5 and the 6th electric crystal Q6 in order to drag down (pull down) in a Q
(n)On output waveform to electronegative potential.In addition, the 7th electric crystal Q7 can avoid a G
(n)On have the phenomenon of suspension joint and protect the 4th electric crystal Q4 and the 3rd electric crystal Q3 discharges and recharges when conversion in capacitor C 1, can keep conducting state.In addition, capacitor C 1 of the present invention has capacity coupled effect, and it can guarantee that the second electric crystal Q2 maintains linear zone work when capacitor C 1 charging.Then, in time T
3The time, receive back one and move the output signal OUT that deposits working storage
(n+1), in order to replacement shift register 15.
Driving circuit of the present invention has simple architecture and the low noise of output, can be used for promoting the degree of stability of output waveform and the fiduciary level of TFT.Its another benefit of driving circuit of the present invention is that by the voltage swing that reduces signal source, the drift of membrane transistor critical voltage also is suppressed simultaneously, guarantees to prolong the operational use time of circuit.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. driving circuit is characterized in that comprising:
A plurality of shift registers of serial connection, and each shift register also comprises:
First electric crystal, it comprises first utmost point, second utmost point and gate, wherein first utmost point of this first electric crystal couples with the gate of this first electric crystal mutually;
Second electric crystal, it comprises first utmost point, second utmost point and gate, wherein the gate of this second electric crystal couples first utmost point coupled with first signal of second utmost point and this second electric crystal of this first electric crystal;
The 3rd electric crystal, it comprises first utmost point, second utmost point and gate, wherein the gate of the 3rd electric crystal couples second utmost point of this second electric crystal and first utmost point of the 3rd electric crystal couples secondary signal;
The 4th electric crystal, it comprises first utmost point, second utmost point and gate, and wherein second utmost point of the 4th electric crystal couples the 3rd signal, and first utmost point that the gate of the 4th electric crystal couples the 4th signal and the 4th electric crystal couples second utmost point of this second electric crystal;
The 5th electric crystal, it comprises first utmost point, second utmost point and gate, and wherein the gate of the 5th electric crystal couples the 4th signal, and first utmost point of the 5th electric crystal couples second utmost point of the 3rd electric crystal and second utmost point of the 5th electric crystal couples the 3rd signal;
The 6th electric crystal, it comprises first utmost point, second utmost point and gate, wherein first utmost point of the 6th electric crystal couples second utmost point of this first electric crystal and second utmost point of the 6th electric crystal couples the 3rd signal; And
Electric capacity, it comprises first end and second end, wherein this first end of this electric capacity this second end of coupling first utmost point and this electric capacity of the 6th electric crystal couples first utmost point of the 5th electric crystal.
2. like claim 1 a described driving circuit; It is characterized in that also comprising: the 7th electric crystal; It comprises first utmost point, second utmost point and gate; Wherein the gate of the 7th electric crystal couples the 4th signal, and second utmost point that first utmost point of the 7th electric crystal couples second utmost point and the 7th electric crystal of this second electric crystal couples this second end of this electric capacity.
3. like claim 1 a described driving circuit, it is characterized in that: this first utmost point of this first electric crystal also receives the output signal of being seen off by previous shift register.
4. like claim 1 a described driving circuit, it is characterized in that: the gate of the 6th electric crystal also receives the output signal of being seen off by a back shift register.
5. like claim 1 a described driving circuit, it is characterized in that: this first signal and this secondary signal are the positive direct-current source, and the 3rd signal is negative DC source/ground connection, and accurate position greater than this secondary signal, the position of this first signal is accurate.
6. like claim 1 a described driving circuit; It is characterized in that: the odd bits shift register in these a plurality of shift registers; The 4th signal that it received is a clock signal; And the even bit shift register in these a plurality of shift registers, the 4th signal that it received is this clock signal of anti-phase.
7. like claim 1 a described driving circuit, it is characterized in that: this shift register circuit is arranged on the glass substrate.
8. like claim 1 a described driving circuit, it is characterized in that: this first to the 6th electric crystal is amorphous silicon membrane electric crystal or NMOS electric crystal.
9. like claim 2 a described driving circuit, it is characterized in that: the 7th electric crystal is amorphous silicon membrane electric crystal or NMOS electric crystal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110115761.8A CN102760397B (en) | 2011-04-27 | 2011-04-27 | Drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110115761.8A CN102760397B (en) | 2011-04-27 | 2011-04-27 | Drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102760397A true CN102760397A (en) | 2012-10-31 |
| CN102760397B CN102760397B (en) | 2014-12-10 |
Family
ID=47054844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110115761.8A Expired - Fee Related CN102760397B (en) | 2011-04-27 | 2011-04-27 | Drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102760397B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810142A (en) * | 2016-05-20 | 2016-07-27 | 上海天马有机发光显示技术有限公司 | Shift register unit and driving method thereof, shift register circuit and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2343067A (en) * | 1998-10-21 | 2000-04-26 | Lg Philips Lcd Co Ltd | A shift register for driving an LCD pixel row |
| CN101135791A (en) * | 2006-08-31 | 2008-03-05 | 株式会社半导体能源研究所 | Liquid crystal display device |
| WO2009034749A1 (en) * | 2007-09-12 | 2009-03-19 | Sharp Kabushiki Kaisha | Shift register |
| WO2010150574A1 (en) * | 2009-06-25 | 2010-12-29 | シャープ株式会社 | Shift register circuit, display device provided with same, and shift register circuit driving method |
-
2011
- 2011-04-27 CN CN201110115761.8A patent/CN102760397B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2343067A (en) * | 1998-10-21 | 2000-04-26 | Lg Philips Lcd Co Ltd | A shift register for driving an LCD pixel row |
| CN101135791A (en) * | 2006-08-31 | 2008-03-05 | 株式会社半导体能源研究所 | Liquid crystal display device |
| WO2009034749A1 (en) * | 2007-09-12 | 2009-03-19 | Sharp Kabushiki Kaisha | Shift register |
| WO2010150574A1 (en) * | 2009-06-25 | 2010-12-29 | シャープ株式会社 | Shift register circuit, display device provided with same, and shift register circuit driving method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810142A (en) * | 2016-05-20 | 2016-07-27 | 上海天马有机发光显示技术有限公司 | Shift register unit and driving method thereof, shift register circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102760397B (en) | 2014-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11087855B2 (en) | Shift register unit and driving method, gate drive circuit and display device | |
| US10223993B2 (en) | Shift register and driving method thereof, gate driving circuit and display apparatus | |
| KR102348667B1 (en) | Shift register and display apparatus comprising the same | |
| CN102012591B (en) | Shift register unit and liquid crystal display gate drive device | |
| US10019929B2 (en) | Gate drive circuit and display device using the same | |
| US9997112B2 (en) | Display device | |
| KR102024116B1 (en) | A gate driving circuit and a display apparatus using the same | |
| CN101847445B (en) | Shift register and grid line driving device thereof | |
| US9905311B2 (en) | Shift register circuit, drive circuit, and display device | |
| WO2012137728A1 (en) | Scanning signal line drive circuit and display device equipped with same | |
| TWI469150B (en) | Shift register circuit | |
| KR102023641B1 (en) | Shift register and method for driving the same | |
| JP2019532321A (en) | GOA circuit | |
| CN103578402B (en) | Display panel | |
| US10748465B2 (en) | Gate drive circuit, display device and method for driving gate drive circuit | |
| KR102147645B1 (en) | Shift resister | |
| CN105469756A (en) | GOA circuit based on LTPS semiconductor thin-film transistors | |
| US10192474B2 (en) | Controllable voltage source, shift register and unit thereof, and display | |
| CN102097074B (en) | Grid driving circuit | |
| CN104821146A (en) | Grid driving circuit, unit thereof and display device | |
| US10255983B2 (en) | Shift register, unit thereof, and display device | |
| US20140306947A1 (en) | Gate signal line drive circuit and display | |
| TWI407401B (en) | Level shifter, method for generating clock-pulse output signal and corresponding flat display | |
| CN102760397B (en) | Drive circuit | |
| CN101562047B (en) | Shift register and liquid crystal display grate drive device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141210 Termination date: 20150427 |
|
| EXPY | Termination of patent right or utility model |