CN102760083A - Method for controlling operation of multiple processors and system thereof - Google Patents
Method for controlling operation of multiple processors and system thereof Download PDFInfo
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- CN102760083A CN102760083A CN2011101124436A CN201110112443A CN102760083A CN 102760083 A CN102760083 A CN 102760083A CN 2011101124436 A CN2011101124436 A CN 2011101124436A CN 201110112443 A CN201110112443 A CN 201110112443A CN 102760083 A CN102760083 A CN 102760083A
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Abstract
The invention discloses a method for controlling operation of multiple processors and a system thereof, aiming at coordinating the operation sequence of a monitor processor and a plurality of target processors in executing different operation programs. The method for controlling operation of multiple processors comprises the following steps: the monitor processor acquires operation state values of other processors from a buffer block; the monitor processor selects at least one target processor according to the operation state values; the monitor processor dispatches a target processor to execute a corresponding subordinate operation program, and modifies the operation state value of each target processor in the buffer module; and the monitor processor repeats the set operation state values and dispatches other target processors to execute corresponding operation programs thereof until the main operation program is completed.
Description
Technical field
The invention discloses a kind of flow control method and system thereof, be particularly to a kind of running control method and system thereof of multiprocessor.
Background technology
Along with progressing greatly of the processing procedure of integrated circuit, make processor can reach littler volume and also have stronger operation efficiency simultaneously.The development of processor provides single arithmetic capability from the single-processor in past, is evolved to multiprocessor arithmetic capability separately is provided.Then, be changed to the arithmetic capability that single-processor can provide multithreading (threads).At last, be evolved to the computing that multiprocessor can provide multithreading.
In the processing procedure of multiprocessor, need carry out Resource allocation and smoothing to each processor and handle, use and guarantee that each processor does not have idle situation and takes place.Therefore can inquire about inquiry and its load that other processor is grasped through the poll (polling) or the modes such as (interrupt) of interruption between processor.
Existing poll is constantly to inquire other processor by the processor of initiating, and looks at whether other processor has accomplished previous order.If other processor has been accomplished order, the processor of initiation could be seen Next Command again off.Though can guaranteeing each processor, the mode of poll all have separately stroke and resource to use.Because after need waiting for the processor response during poll, the processor of initiation just can send down order together.Therefore the stand-by period of poll can be also more of a specified duration than the time of operation.
For shortening the stand-by period of poll, therefore the someone proposes the mode of Interrupt Process in addition.Interrupt Process is just temporarily called the work that processor is carried out other device.In case interrupt taking place, processor can store the status information of buffer at that time.By the time after interrupting the affairs end, just can restart calculating according to this status information.In other words, the working routine that processor need temporarily stop also transferring to handle the interruption affairs of being correlated with, and last processor also must provide the ability of recovering operate as normal, so that have no progeny in handling, and the program of finishing before the continuation.Handle compared to poll, Interrupt Process can not need be waited for other processor response, so the processor of initiating can send interrupt request to different processors.Though Interrupt Process can reduce the stand-by period, use more hardware resource to come the state of recording processor at the process need of handling interrupt.
Therefore multiprocessor (for example: poll is handled or Interrupt Process) in the processing procedure of sending all can produce waits for too long and expend problem such as hardware resource.
Summary of the invention
In view of above problem, the invention reside in provides a kind of running of multiprocessor control method, coordinated monitoring processor and the sequence of operations of a plurality of target processors at the different operation procedures of execution.
The running control method of the disclosed multiprocessor of the present invention may further comprise the steps: carry out main operation procedure by monitoring processor; Monitoring processor is obtained this operating state value of other target processor from the buffering block; Monitoring processor is selected at least one target processor; Monitoring processor resets the operating state value of other target processor of being selected, makes other target processor carry out corresponding subordinate operation procedure according to new operating state value; The step of monitoring processor repeatedly setting operating state value is till monitoring processor is accomplished this main operation procedure; After monitoring processor is accomplished main operation procedure, monitoring processor will empty the operating state value of other target processor in the buffer blocks.
The running control system that the present invention proposes a kind of multiprocessor in addition comprises: monitoring processor, target processor and buffer blocks.Monitoring processor and target processor are when the program of carrying out separately, and processor can write its state value in the buffer blocks.And monitoring processor is carried out main operation procedure, and from the buffering block, obtains the operating state value of other target processor; Monitoring processor is selected at least one target processor; Monitoring processor resets the operating state value of other target processor of being selected, makes other target processor carry out corresponding subordinate operation procedure according to new operating state value; The step of monitoring processor repeatedly setting operating state value is till monitoring processor is accomplished this main operation procedure; After monitoring processor is accomplished main operation procedure, monitoring processor will empty the operating state value of other target processor in the buffer blocks.
Control method and system thereof that the present invention proposes a kind of multiprocessor carry out the sequence of operations of different operation procedures in order to coordinate a plurality of processors.Each processor of the present invention need not see through the user mode that modes such as interruption, poll obtain other processor.Therefore can reduce the spent time of inquiry in the allocation process of multiprocessor of the present invention, use the operational paradigm that improves processor.
About characteristic of the present invention and real the work, conjunction with figs. is made most preferred embodiment and is specified as follows.
Description of drawings
Fig. 1 is a configuration diagram of the present invention;
Fig. 2 is an operation workflow synoptic diagram of the present invention;
Fig. 3 A is a subordinate operation procedure structural representation of the present invention;
Fig. 3 B is the synoptic diagram of buffer module of the present invention;
Fig. 3 C is an overall architecture running synoptic diagram of the present invention;
Fig. 3 D is the program pointer and the program state value of target processor of the present invention;
Fig. 3 E is the program pointer and the program state value of target processor of the present invention;
Fig. 3 F is the program pointer and the program state value of target processor of the present invention;
Pulse signal synoptic diagram when Fig. 4 is of the present invention the running.
Wherein, Reference numeral:
Control system 100
Label A subordinate operation procedure 131-1
Label B subordinate operation procedure 131-2
Label C subordinate operation procedure 131-3
Embodiment
The present invention can be applied to having IC chip (the integrated circuit of multiprocessor; IC) in; For example: flat computer, personal computer, intelligent mobile phone (Smart Phone) or personal digital assistant (Personal digital assistant, PDA).Please refer to shown in Figure 1ly, it is a configuration diagram of the present invention.Control system 100 of the present invention is made up of with 120 of buffer modules a plurality of processors 110.Each processor 110 is electrically connected to buffer module 120.
Select it in the lump it to be defined as monitoring processor 111 at this processor 110 from running, and the processor that all the other are assigned is a target processor 112.Monitoring processor 111 is in order to send the corresponding operation procedure of other target processor 112 operations.Monitoring processor 111 can be according to the loading demand of main operation procedure or the idle processor 110 and then the quantity of decision target processor 112.Monitoring processor 111 current performed operation procedures are defined as main operation procedure with it.The target processor 112 performed operation procedures that monitored processor 111 is assigned then are defined as subordinate operation procedure 131.
The control method of multiprocessor of the present invention may further comprise the steps, and also please refer to shown in Figure 2ly, and it is an operation workflow synoptic diagram of the present invention:
Step S210: carry out main operation procedure by monitoring processor;
Step S220: monitoring processor is obtained the operating state value of other target processor from the buffering block;
Step S230: monitoring processor is selected at least one target processor;
Step S240: monitoring processor is assigned to the target processor of being selected and is carried out corresponding subordinate operation procedure, and this monitoring processor resets this operating state value of those target processors of being selected;
Step S250: monitoring processor repeats to assign the step of subordinate operation procedure, till monitoring processor is accomplished main operation procedure; And
Step S260: after monitoring processor is accomplished main operation procedure, monitoring processor will empty the operating state value of all target processors in (Flush) buffer blocks.
At first, monitoring processor 111 is carried out main operation procedure.Monitoring processor 111 is obtained the operating state value of other target processor 112 from the buffering block.The target processor 112 that monitoring processor 111 is assigned according to the operating state value decision desire that is obtained.For example, monitoring processor 111 can the option program pointer or the program state value be that the processor of " 0 " is as target processor 112.
Behind monitoring processor 111 select target processors 112, monitoring processor 111 is assigned to the target processor of being selected 112 and is carried out corresponding subordinate operation procedure 131.In this simultaneously, monitoring processor 111 also can reset the operating state value of the target processor 112 selected, uses letting other monitoring processor 111 ban use of these target processors that has been assigned 112.Monitoring processor 111 is carried out corresponding subordinate operation procedure 131 according to the driving target processor 112 that main operation procedure repeats, till monitoring processor 111 is accomplished main operation procedure.
At last, when monitoring processor 111 is accomplished main operation procedure, monitoring processor 111 will empty the operating state value of all target processors 112 in the buffer blocks, use the right to use that discharges target processor 112.Monitoring processor 111 of the present invention is given different target processors 112 with the mode that sees through pipelined (Pipeline) with the appointment of 131 timesharing of each subordinate operation procedure, lets processing that each target processor 112 can be separately subordinate operation procedure 131 under it.
For clearly demonstrating overall operation of the present invention, this with the operation of a monitoring processor 111 and a target processor 112 as explanation, but be not that the quantity of target processor 112 only is confined to this.Suppose to serve as monitoring processor 111, and processor 1 is a target processor 112, and carries out subordinate operation procedures 131 such as Label A, Label B and Label C that please refer to shown in Fig. 3 A, it is subordinate operation procedure 131 structural representations by processor 2.Say that from software angle target processor 112 can the different output valve of output after accomplishing subordinate operation procedure 131 each time.From the angle of hardware, target processor 112 all can produce different pulse signals (Pulse) after accomplishing subordinate operation procedure 131 each time.And monitoring processor 111 (monitoring processor 111 is the PE2 of following pseudo-code, the PE1 of 112 corresponding pseudo-codes of target processor) then moves the pseudo-code of following main operation procedure:
At first, whether unusual fluctuation (becoming 1 by 0 in this example) of the program state value of the monitoring objective processor 112 that repeats by monitoring processor 111 of the execution flow process of main operation procedure.In the pseudo-code of this enforcement aspect, come the sequence of operations of controlled target processor 1121, but be not only to be confined to this for Label A, Label B and Label C with a circulation.The logic control that in the process of assigning target processor 112, can see through other decides the execution sequence of subordinate operation procedure 131.
Whether the program state value that monitoring processor 111 can read A0 field in the buffer module 120 timely changes to 1.When the program state value of A0 field still was 0, then monitoring processor 111 did not assign target processor 112 to carry out Label B subordinate operation procedure 131-2.
When Label A subordinate operation procedure 131-1 is performed, then in buffer module 120, carry out corresponding annotation on the field of corresponding processing device, please cooperate shown in Fig. 3 B and Fig. 3 C, it is respectively the synoptic diagram of buffer module and overall operation.The program pointer of target processor 112 and program state value are set at Label A and 0 respectively in Fig. 3 B; Meaning is that monitoring processor 111 will assign target processor 112 to carry out Label A subordinate operation procedure 131-1, and the operating state value of target processor 112 is set at 0.So, other monitoring processor 111 can be observed this target processor 112 (meaning is former processor 1) from buffer module 120 and is used.So 111 of other monitoring processors can not call former processor 1 (meaning is a target processor 112).After Label A subordinate operation procedure 131-1 accomplishes, will be set at 1 to the program state value, please refer to shown in Fig. 3 D.When the program state value of A0 field was 1, then monitoring processor 111 assigned target processor 112 to carry out Label B subordinate operation procedure 131-2.
Then, monitoring processor 111 can drive target processor 112 and carry out Label B subordinate operation procedure 131-2.Monitoring processor 111 meetings are set at Label B and 0 respectively with the program pointer and the program state value of the target processor 112 of buffer module 120, please refer to Fig. 3 E.111 of monitoring processors read the operating state value of the target processor 112 of buffer module 120 always, and judge whether its operating state value changes.When the program state value of B0 field was 1, then monitoring processor 111 assigned target processor 112 to carry out Label C subordinate operation procedure 131-3.
In like manner, monitoring processor 111 can drive target processor 112 and carry out Label C subordinate operation procedure 131-3.Monitoring processor 111 meetings are set at Label C and 0 respectively with the program pointer and the program state value of the target processor 112 of buffer module 120, please refer to Fig. 3 F.When the program state value of C0 field was 1, then monitoring processor 111 assigned target processor 112 to carry out Label A subordinate operation procedure 131-1.Monitoring processor 111 is after accomplishing Label C subordinate operation procedure 131-3, and monitoring processor 111 can be carried out Label A subordinate operation procedure 131-1 once more according to the circulation of main operation procedure.
Say that just as above-mentioned institute the control system 100 of multiprocessor of the present invention except producing corresponding output valve, also can produce through different subordinate operation procedures and export corresponding pulse signal for hardware when carrying out each subordinate operation procedure 131.Suppose that Label A subordinate operation procedure 131-1 generates 4 pulses, Label B subordinate operation procedure 131-2 generates 2 pulses, Label C subordinate operation procedure 131-3 and generates 6 pulses.Please cooperate shown in Figure 4ly, it is the pulse signal synoptic diagram in when running of the present invention.
Except above-mentioned enforcement aspect, the present invention can be applied in the control system 100 of multiple goal processor 112 in addition.Said as preamble, monitoring processor 111 can assign different target processor 112 to carry out subordinate operation procedure 131 separately in carrying out main operation procedure.
Control method and system thereof that the present invention proposes a kind of multiprocessor carry out the sequence of operations of different operation procedures in order to coordinate a plurality of processors.Each processor of the present invention need not see through the user mode that modes such as interruption, poll obtain other processor.Therefore can reduce the spent time of inquiry in the allocation process of multiprocessor of the present invention, use the operational paradigm that improves processor.
Claims (10)
1. the running control method of a multiprocessor is coordinated a monitoring processor and the sequence of operations of a plurality of target processors at the different operation procedures of execution, it is characterized in that this control method may further comprise the steps:
Carry out a main operation procedure by this monitoring processor;
This monitoring processor is obtained an operating state value of those target processors from a buffer blocks;
This monitoring processor is selected at least one this target processor; And
This monitoring processor is assigned to those target processors and is carried out a corresponding subordinate operation procedure, and this monitoring processor resets this operating state value of those target processors of being selected.
2. the running control method of multiprocessor as claimed in claim 1 is characterized in that, this operating state value comprises an identification sign indicating number, a program pointer, a program state value, at least and writes flag or and read flag.
3. the running control method of multiprocessor as claimed in claim 2 is characterized in that, this monitoring processor is selected those target processors according to this operating state value.
4. the running control method of multiprocessor as claimed in claim 1 is characterized in that, this monitoring processor repeats to assign the step of this subordinate operation procedure, till this monitoring processor is accomplished this main operation procedure.
5. the running control method of multiprocessor as claimed in claim 4 is characterized in that, after this monitoring processor is accomplished this main operation procedure, this monitoring processor will empty this operating state value of those target processors in this buffer blocks.
6. the control system of a multiprocessor is coordinated the sequence of operations that a plurality of processors are carried out different operation procedures, it is characterized in that, this control system comprises:
One buffer blocks is in order to note down an operating state value of those processors;
At least one target processor when each this target processor is carried out a subordinate operation procedure, writes this buffer blocks with this operating state value of this target processor; And
One monitoring processor; In order to carry out a main operation procedure; This monitoring processor is obtained this operating state value of those target processors from this buffer blocks; And select at least one this target processor, this monitoring processor resets this operating state value of those target processors of being selected, makes those target processors carry out corresponding this subordinate operation procedure according to this new operating state value.
7. the control system of multiprocessor as claimed in claim 6 is characterized in that, this operating state value comprises an identification sign indicating number, a program pointer, a program state value, at least and writes flag or and read flag.
8. the control system of multiprocessor as claimed in claim 6 is characterized in that, after this monitoring processor is accomplished this main operation procedure, this monitoring processor will empty this operating state value of those target processors in this buffer blocks.
9. the control system of multiprocessor as claimed in claim 6 is characterized in that, this monitoring processor repeats to assign this subordinate operation procedure, till this monitoring processor is accomplished this main operation procedure.
10. the control system of multiprocessor as claimed in claim 6 is characterized in that, after this monitoring processor is accomplished this main operation procedure, this monitoring processor will empty this operating state value of those target processors in this buffer blocks.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101124436A CN102760083A (en) | 2011-04-26 | 2011-04-26 | Method for controlling operation of multiple processors and system thereof |
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| CN2011101124436A CN102760083A (en) | 2011-04-26 | 2011-04-26 | Method for controlling operation of multiple processors and system thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408334A (en) * | 1992-11-24 | 1995-04-18 | Hitachi, Ltd. | Method and apparatus for having a processor execute a job utilizing an electronic mail system |
| CN1426023A (en) * | 2001-12-04 | 2003-06-25 | 松下电器产业株式会社 | Moving image encoding device and its method using multiple processor |
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- 2011-04-26 CN CN2011101124436A patent/CN102760083A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408334A (en) * | 1992-11-24 | 1995-04-18 | Hitachi, Ltd. | Method and apparatus for having a processor execute a job utilizing an electronic mail system |
| CN1426023A (en) * | 2001-12-04 | 2003-06-25 | 松下电器产业株式会社 | Moving image encoding device and its method using multiple processor |
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Application publication date: 20121031 |