CN102752571A - High-definition video device and implementation method thereof - Google Patents
High-definition video device and implementation method thereof Download PDFInfo
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Abstract
The invention provides a high-definition video device and an implementation method thereof. The device comprises a godson central processing unit (CPU), a north bridge chip, a south bridge chip, a direct memory access (DMA) controller, a video encoding and decoding chip and a video display chip. The method effectively joins a video graphics array (VGA) encoding and decoding task (namely the video encoding and decoding chip directly reads video signals from periphery and encodes and decodes the video signals through the south bridge chip) and a VGA display task (namely the video display chip converts received encoded and decoded data into RGBHV signals) to achieve a high-definition VGA graphics card function in X86 market at present. The video device and the implementation method send and receive commands through the godson CPU only, real video playing tasks are distributed to the video encoding and decoding chip and the video display chip to bear, workload of the godson CPU is lightened to the maximum degree, and operational capability of the godson CPU on other application is strengthened accordingly.
Description
Technical field
The invention belongs to the multimedia field, be specifically related to a kind of high sharpness video device and its implementation.
Background technology
The difficult situation of Chinese high-performance server field centreless has been broken in the appearance of No. 3 serial CPU of Godson, China IT industry band on a new height.But the problem that next faces a sternness is exactly the industrialization problem of CPU, if solve the problem of bad industrialization, it can not practicality be the CPU of conceptual that Godson CPU is still one, can only stop under lab.Because the time that No. 3 serial CPU of Godson emerge is short, so the equal imperfection of various supporting application schemes.The video displaying scheme that lacks high definition is an important problem of restriction Godson CPU development, if Godson CPU does not solve the demonstration problem of high definition, just can't use widely in PC market and personal terminal market.
Godson CPU displaying scheme adopts two kinds mostly at present: the one, and be employed on South Bridge chip PCI bus or the north bridge PCIE bus and articulate Embedded VGA IC; The 2nd, the VGA Presentation Function that relies on north bridge to carry solves.But all there is shortcoming in this mode, does not reach the requirement of high sharpness video function.
The problem of the 1st kind of scheme existence is: the function of embedded VGA IC is very simple, can only realize simple demonstration, can't present high-resolution image, and ten minutes is slow when the film of running game, broadcast 720p and 1080p form;
The problem that the 2nd kind of scheme exists is: it is higher that north bridge carries the price of professional VGA video card, can't adapt to the high-quality requirement of low price in market.Present way can only be explained the binary code of operation north bridge VGA through simulation program, retardation the demonstration time, make the big heavy discount of north bridge VGA Presentation Function.Another reason is exactly that this displaying scheme needs Godson CPU to bear the encoding and decoding task of a part of video; Take the resource of CPU; So Godson CPU also will take into account the encoding and decoding task of video when other program of operation, make the playing fluency of VGA video limited greatly.
Except above-mentioned two kinds of schemes; Can also on PCIE bus, insert the VGA video card that performance is powerful in the market; But its major defect also is Godson CPU when other tasks of operation, does not have enough Godson cpu resources or ability to bear and originally belongs to that part of coding and decoding video task of Godson CPU, so need to accomplish the coding and decoding video task through the other technologies means; Discharge Godson CPU with this, can also be when realizing HD video through other program of Godson CPU operation.
Summary of the invention
To the above-mentioned defective of prior art, one of the object of the invention is to propose a kind of cheap, high sharpness video device that can alleviate Godson CPU live load.
The present invention realizes through following technical scheme:
A kind of high sharpness video device, it comprises Godson CPU, north bridge chips, South Bridge chip, dma controller, coding and decoding video chip and video display chip, wherein,
Said Godson CPU sends order to control its work to dma controller and other chip respectively;
Said coding and decoding video chip directly reads and the encoding and decoding video data through dma controller;
Reaching display after the video data of said video display chip after with encoding and decoding changed plays.
Further, this device comprises:
Memory is used to store the video data after process coding and decoding video chip carries out encoding and decoding.
Further, this device comprises:
Processing unit is used for the video data after the encoding and decoding is put into buffering area, reaches the buffering area threshold values until the buffering capacity of buffering area; With
Allocation units are used to calculate the buffering area threshold values, and carry out corresponding sharing out the work according to the threshold values whether buffering capacity of buffering area reaches buffering area:
Before the buffering capacity of buffering area does not reach said threshold values, for processing unit distributes higher priority;
After the buffering capacity of buffering area reaches said threshold values, reduce the priority of processing unit, and give video display chip more priority.
Further, said north bridge chips is connected with Godson CPU through the HT bus, and said north bridge chips is connected with South Bridge chip through A Link bus.
Further, said north bridge chips is connected with the coding and decoding video chip through the PCIE interface and said South Bridge chip passes through pci interface and is connected with video display chip; Perhaps said north bridge chips is connected with video display chip with the coding and decoding video chip respectively through the PCIE interface; Perhaps said north bridge chips is connected with video display chip through the PCIE interface and said South Bridge chip is connected with the coding and decoding video chip through pci interface.
Further, coding and decoding video chip and video display chip can adopt following arbitrary mode to make up:
Said coding and decoding video chip adopts the BCM70015 chip, it is connected to north bridge chips through the PCIE bus; Said video display chip adopts the SM502 chip, it is connected to South Bridge chip through pci bus;
Said coding and decoding video chip BCM70015 chip, said video display chip adopts the SM750 chip, and the two is connected to north bridge chips through the PCIE bus respectively;
Said coding and decoding video chip adopts the BCM70010 chip, it is connected to South Bridge chip through pci bus; Said video display chip adopts the SM750 chip, it is connected to north bridge chips through the PCIE bus.
Another object of the present invention is to propose a kind of implementation method of high sharpness video, comprise the steps:
1) file identification through Godson CPU recording video data;
2) send coding and decoding video order through Godson CPU to coding and decoding video chip, north bridge chips and South Bridge chip, and command id task ID for this reason;
3) said coding and decoding video chip passes through the direct reading video data of dma controller, and carries out encoding and decoding and handle;
4) said coding and decoding video chip will pass through encoding and decoding processed video data and reach video display chip, transmit this task ID simultaneously;
5) after said video display chip converts video data to the RGBHV signal, reach display and play;
6) after this video playback is accomplished, this task ID is back to Godson CPU through video display chip.
Further, the concrete steps of said step 2 comprise:
Godson CPU sends the coding and decoding video order to coding and decoding video chip, north bridge chips and South Bridge chip respectively, the file identification of corresponding video data is reached the coding and decoding video chip, and be task ID of this coding and decoding video command id.
Further, the concrete steps of said step 3 comprise:
Said Godson CPU sends direct storage access command to dma controller;
Said dma controller control of video codec chip directly reads also encoding and decoding from the video data of peripheral hardware.
Further; In the said step 5; When video display chip is changed video data and reach display and plays, earlier the video data after the encoding and decoding is put into buffering area, whether reach the buffering area threshold values according to the buffering capacity of buffering area and carry out corresponding sharing out the work:
Before the buffering capacity of buffering area does not reach said buffering area threshold values, for processing unit distributes higher priority;
After the buffering capacity of buffering area reaches said buffering area threshold values, reduce the priority of processing unit, and give video display chip more priority.
Beneficial effect of the present invention is:
1) this video-unit and its implementation are to the problem of present Godson CPU high definition scheme existence; Dexterously VGA high definition scheme separated into two parts task: the one, VGA encoding and decoding task: promptly the coding and decoding video chip directly reads the vision signal from peripheral hardware through South Bridge chip, and vision signal is carried out encoding and decoding; The 2nd, VGA shows task: promptly the data transaction of video display chip after with the encoding and decoding that receive is the RGBHV signal.This video-unit and its implementation have realized the high definition VGA video card function on the present X86 market through above-mentioned two-part effective linking; Make the user be no longer dependent on external high-end specialty products, can reach the effect of high sharpness video through free use or the general-purpose chip of licensing.
2) this video-unit and its implementation are only sent through Godson CPU and are received order; And real video playback Task Distribution bears for coding and decoding video chip and video display chip; Farthest alleviated the live load of Godson CPU, thereby strengthened the operational capability of Godson CPU other application.
Description of drawings
Fig. 1 is the structure principle chart of high sharpness video device embodiment one of the present invention;
Fig. 2 is the structure principle chart of high sharpness video device embodiment two of the present invention;
Fig. 3 is the structure principle chart of high sharpness video device embodiment three of the present invention.
Embodiment
Below in conjunction with accompanying drawing high sharpness video device of the present invention and its implementation are done further detailed explanation.
Embodiment one
As shown in Figure 1, the high sharpness video device in this example mainly comprises Godson CPU, South Bridge chip, north bridge chips, coding and decoding video chip, video display chip, dma controller and the memory that is positioned at frame of broken lines.Godson CPU in this example bears the effect of mutual control command, need not carry out the conversion of coding and decoding video and follow-up shows signal.
Said Godson CPU, South Bridge chip, north bridge chips have constituted the Godson platform.Also can have dma controller and memory on this platform, dma controller links to each other with Godson CPU respectively with memory, and north bridge chips is connected with Godson CPU through the HT bus and is connected with South Bridge chip through the A-Link bus.Godson CPU can adopt Godson 3A CPU, Godson 3B CPU or the Godson 3C CPU among No. 3 serial CPU of Godson; North bridge chips can adopt following arbitrary model chip: the RS780 of AMD, RS780C, RS780D, RS780E, RS780G, RS780M, RS780MC, RX781, RS785G or RD790; South Bridge chip can adopt following arbitrary model chip: the SB700 of AMD, SB710, SB750 or SB600.
Said coding and decoding video chip and video display chip have been accomplished the high definition solution.The coding and decoding video chip can adopt Broadcom company the BCM70015 chip, it is connected to north bridge chips through the PCIE bus; Video display chip can adopt SiliconMotion company the SM502 chip, it is connected to South Bridge chip through pci bus.
In order to make this video-unit reach more excellent demonstration and treatment effect, the video-unit in this example can further include:
Processing unit is used for the video data after the encoding and decoding is put into buffering area, reaches the buffering area threshold values until the buffering capacity of buffering area; With
Allocation units are used to calculate the buffering area threshold values, and whether reach the buffering area threshold values according to the buffering capacity of buffering area and carry out following priority work:
Before the buffering capacity of buffering area does not reach said buffering area threshold values, for processing unit distributes higher priority;
After the buffering capacity of buffering area reaches said buffering area threshold values, reduce the priority of processing unit, and give video display chip more priority;
The computing formula of said buffering area threshold values is: C=L-(S*T)
In the formula, C is the buffering area threshold values, and L is a video size, and S is the encoding and decoding speed after the reduction processing unit priority, and T is the video playback time.
As shown in Figure 1, the implementation method of this video-unit comprises the steps:
The first step:, write down the file mark of corresponding video data, but do not read when Godson CPU detects the video data on the peripheral hardware (like hard disk, USB flash disk);
Second step: Godson CPU sends the coding and decoding video order to coding and decoding video chip, north bridge chips and South Bridge chip respectively, the file identification of corresponding video data is reached the coding and decoding video chip, and be task ID of this coding and decoding video command id.Can find out that Godson CPU does not bear the coding and decoding video task, and vacate valuable other application programs of resource operation;
The 3rd step: the coding and decoding video chip is through the video data of DMA (direct memory visit) function encoding and decoding from peripheral hardware; Be that Godson CPU sends direct storage access command to dma controller; Directly read video data by dma controller control of video codec chip from peripheral hardware; And video data is carried out encoding and decoding handle, the video data after the encoding and decoding can be delivered in the memory and preserve;
The 4th step: the video data of coding and decoding video chip after with encoding and decoding reaches video display chip, transmits this task ID simultaneously.
The 5th step: video display chip converts the video data that shows to corresponding RGBHV signal (i.e. redness, green, blueness, row signal, field signal) and issues display and broadcast; When video data being changed and reaching display and playing, earlier the video data after the encoding and decoding is put into buffering area, whether reach the buffering area threshold values according to the buffering capacity of buffering area and carry out corresponding sharing out the work:
Before the buffering capacity of buffering area does not reach said buffering area threshold values, for processing unit distributes higher priority;
After the buffering capacity of buffering area reaches said buffering area threshold values, reduce the priority of processing unit, and give video display chip more priority;
The 6th goes on foot: the signal of Godson CPU video completion is given in the video display chip loopback, and the corresponding register of this task ID is represented the position assignment that task is accomplished, and shows this coding and decoding video task completion.After treating that Godson CPU receives this task ID number, promptly think the playing task of having accomplished this video.
Embodiment two
The structure of the device of high sharpness video described in this example and its implementation are basic identical with embodiment one, and difference is:
As shown in Figure 2, the coding and decoding video chip can adopt Broadcom company the BCM70015 chip, it is connected to north bridge chips through the PCIE bus; Video display chip can adopt SiliconMotion company the SM750 chip, also be connected to north bridge chips through the PCIE bus.
Embodiment three
The structure of the device of high sharpness video described in this example and its implementation are basic identical with embodiment one, and difference is:
As shown in Figure 3, the coding and decoding video chip can adopt Broadcom company the BCM70010 chip, it is connected to South Bridge chip through pci bus; Video display chip can adopt SiliconMotion company the SM750 chip, it is connected to north bridge chips through the PCIE bus.
Should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not to its restriction; In conjunction with the foregoing description the present invention is specified; Under the those of ordinary skill in field be to be understood that: those skilled in the art still can specific embodiments of the invention make amendment or are equal to replacement, but these modifications or change are all among the claim protection range that application is awaited the reply.
Claims (12)
1. a high sharpness video device is characterized in that, this device comprises Godson CPU, north bridge chips, South Bridge chip, dma controller, coding and decoding video chip and video display chip, wherein,
Said Godson CPU sends order to control its work to dma controller and other chip respectively;
Said coding and decoding video chip directly reads and the encoding and decoding video data through dma controller;
Reaching display after the video data of said video display chip after with encoding and decoding changed plays.
2. high sharpness video device as claimed in claim 1 is characterized in that, this device comprises:
Memory is used to store the video data after process coding and decoding video chip carries out encoding and decoding.
3. high sharpness video device as claimed in claim 1 is characterized in that, this device comprises:
Processing unit is used for the video data after the encoding and decoding is put into buffering area, reaches the buffering area threshold values until the buffering capacity of buffering area;
Allocation units are used to calculate the buffering area threshold values, and whether reach the buffering area threshold values according to the buffering capacity of buffering area and carry out corresponding sharing out the work:
Before the buffering capacity of buffering area does not reach said buffering area threshold values, for processing unit distributes higher priority;
After the buffering capacity of buffering area reaches said buffering area threshold values, reduce the priority of processing unit, and give video display chip more priority.
4. like the arbitrary described high sharpness video device of claim 1-3, it is characterized in that: said north bridge chips is connected with Godson CPU through the HT bus, and said north bridge chips is connected with South Bridge chip through A Link bus.
5. like the arbitrary described high sharpness video device of claim 1-3, it is characterized in that: said north bridge chips is connected with the coding and decoding video chip through the PCIE interface and said South Bridge chip is connected with video display chip through pci interface; Perhaps said north bridge chips is connected with video display chip with the coding and decoding video chip respectively through the PCIE interface; Perhaps said north bridge chips is connected with video display chip through the PCIE interface and said South Bridge chip is connected with the coding and decoding video chip through pci interface.
6. the implementation method of a high sharpness video is characterized in that, this method comprises the steps:
1) file identification through Godson CPU recording video data;
2) send coding and decoding video order through Godson CPU to coding and decoding video chip, north bridge chips and South Bridge chip, and command id task ID for this reason;
3) said coding and decoding video chip passes through the direct reading video data of dma controller, and carries out encoding and decoding and handle;
4) said coding and decoding video chip will pass through encoding and decoding processed video data and reach video display chip, transmit this task ID simultaneously;
5) after said video display chip converts video data to the RGBHV signal, reach display and play;
6) after this video playback is accomplished, this task ID is back to Godson CPU through video display chip.
7. implementation method as claimed in claim 6 is characterized in that, the concrete steps of said step 2 comprise:
Godson CPU sends the coding and decoding video order to coding and decoding video chip, north bridge chips and South Bridge chip respectively, the file identification of corresponding video data is reached the coding and decoding video chip, and be task ID of this coding and decoding video command id.
8. implementation method as claimed in claim 6 is characterized in that, the concrete steps of said step 3 comprise:
Said Godson CPU sends direct storage access command to dma controller;
Said dma controller control of video codec chip directly reads also encoding and decoding from the video data of peripheral hardware.
9. implementation method as claimed in claim 6; It is characterized in that; In the said step 5; When video display chip is changed video data and reach display and plays, earlier the video data after the encoding and decoding is put into buffering area, whether reach the buffering area threshold values according to the buffering capacity of buffering area and carry out corresponding sharing out the work:
Before the buffering capacity of buffering area does not reach said buffering area threshold values, for processing unit distributes higher priority;
After the buffering capacity of buffering area reaches said buffering area threshold values, reduce the priority of processing unit, and give video display chip more priority.
10. implementation method as claimed in claim 6 is characterized in that, said coding and decoding video chip adopts the BCM70015 chip, it is connected to north bridge chips through the PCIE bus; Said video display chip adopts the SM502 chip, it is connected to South Bridge chip through pci bus.
11. implementation method as claimed in claim 6 is characterized in that, said coding and decoding video chip BCM70015 chip, and said video display chip adopts the SM750 chip, and the two is connected to north bridge chips through the PCIE bus respectively.
12. implementation method as claimed in claim 6 is characterized in that, said coding and decoding video chip adopts the BCM70010 chip, it is connected to South Bridge chip through pci bus; Said video display chip adopts the SM750 chip, it is connected to north bridge chips through the PCIE bus.
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