CN102751244A - Semiconductor device and forming method of semiconductor device as well as radio frequency identification chip and forming method of radio frequency identification chip - Google Patents
Semiconductor device and forming method of semiconductor device as well as radio frequency identification chip and forming method of radio frequency identification chip Download PDFInfo
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- CN102751244A CN102751244A CN2011100997276A CN201110099727A CN102751244A CN 102751244 A CN102751244 A CN 102751244A CN 2011100997276 A CN2011100997276 A CN 2011100997276A CN 201110099727 A CN201110099727 A CN 201110099727A CN 102751244 A CN102751244 A CN 102751244A
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Abstract
The invention relates to a semiconductor device and a forming method of the semiconductor device as well as a radio frequency identification chip and a forming method of the radio frequency identification chip. The forming method of the semiconductor device comprises the following steps that a first metal layer, an insulating layer and a second metal layer are sequentially formed on a semiconductor substrate, and the semiconductor substrate, the first metal layer, the insulating layer and the second metal layer respectively comprise a capacitance region and a phase change memory region; the insulating layer and the second metal layer in the phase change memory region as well as the partial insulating layer and the partial second metal layer in the capacitance region are removed, and a capacitor comprises the first metal layer in the capacitance region, the rest of insulating layer and the rest of second insulating layer; the partial first metal layer is removed, and the substrate between the capacitance region and the phase change memory region is exposed; and a medium layer is formed and covers the capacitor, the first metal layer in the phase change memory region and the exposed substrate, and a phase change memory is formed in the medium layer. The capacitor and the phase change memory are integrated, so the compatibility of the capacitor and the phase change memory is realized, in addition, the forming process is simple, and the cost is low.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of semiconductor device and forming method thereof, RF identification chip and forming method thereof.
Background technology
In very lagre scale integrated circuit (VLSIC), capacity cell is one of passive component of using always, is usually used in as in the integrated circuits such as radio frequency IC, monolithic microwave IC.Common capacitance structure comprises metal-oxide semiconductor (MOS) (MOS) electric capacity, PN junction electric capacity and metal level-insulating barrier-metal stratotype (MIM, Metal-Insulator-Metal) electric capacity etc.At present, MIM electric capacity has obtained using widely because of it can provide preferably frequency and temperature correlated characteristic.In addition, in semiconductor was made, MIM electric capacity can be formed at interlayer metal and be applied in the copper-connection processing procedure, so reduced degree of difficulty and the complexity of integrating with the CMOS front-end process.
RF identification chip (RFID chip); Be commonly called as electronic tag; Also claim transponder (transponder; Responder); It is through the automatic recognition objective object of radiofrequency signal and obtain related data, is widely used in fields such as logistics, supplies management, the manufacturing and assembling, aviation luggage processing, mail, the processing of fast freight parcel, document tracking, library management animal identification sign, motion timing, gate inhibition's control, electronic entrance ticket, the automatic charge of road, to satisfy the various requirements of people.
The internal structure of RFID chip mainly comprises radio-frequency front-end, AFE(analog front end), digital baseband processing unit and memory cell four parts.Said radio-frequency front-end comprises MIM electric capacity.The memory cell of RFID chip adopts static random access memory (SRAM, Static random access memory) usually in the prior art.Yet along with progressively reducing and the increase of semiconductor technology integrated level of semiconductor technology node; Also need seek new memory and be used as its memory cell, and can make that the production technology of MIM electric capacity is compatible mutually in production technology and the existing RFID production technology of new memory for the RFID chip.
Publication number is that 101042741 one Chinese patent application provides a kind of RFID label, but the problems referred to above are not related to.
Summary of the invention
The problem that the present invention solves is with phase transition storage (PCRAM) replacement SRAM, and through simple technology MIM electric capacity and phase transition storage is integrated at same the semiconductor-based end.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, said semiconductor device comprises electric capacity and phase transition storage, the formation method of said semiconductor device comprises:
The semiconductor-based end is provided, on the said semiconductor-based end, forms the first metal layer, insulating barrier and second metal level successively, the said semiconductor-based end, the first metal layer, insulating barrier and second metal level comprise capacitor regions and phase transition storage zone respectively;
Remove the partial insulative layer and part second metal level of insulating barrier, second metal level and the capacitor regions in phase transition storage zone, said electric capacity comprises the first metal layer and the remaining insulating barrier and second metal level of capacitor regions;
Remove the part the first metal layer, expose the substrate between said capacitor regions and the phase transition storage zone;
Form dielectric layer; Cover said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure; In said dielectric layer, form the bottom electrode and the phase change resistor of phase transition storage, said bottom electrode is electrically connected with the first metal layer in said phase transition storage zone.
Optional; Form dielectric layer; Cover said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure; In said dielectric layer, form the bottom electrode and the phase change resistor of phase transition storage, said bottom electrode is electrically connected with the first metal layer in said phase transition storage zone and comprises:
Form first dielectric layer, cover said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure, in said first dielectric layer, form first embolism that is electrically connected with the first metal layer in said phase transition storage zone;
Form second dielectric layer, cover said first dielectric layer and first embolism, in said second dielectric layer, form the bottom electrode that is electrically connected with said first embolism;
Form the 3rd dielectric layer, cover said second dielectric layer and bottom electrode, in said the 3rd dielectric layer, form the phase change resistor of phase transition storage, said phase change resistor is electrically connected with said bottom electrode.
Optional, said formation first embolism comprises:
On said first dielectric layer, form patterned first photoresist, define the position of first embolism;
With said patterned first photoresist is mask, and said first dielectric layer of etching forms first through hole;
Filled conductive material in said first through hole forms first embolism.
Optional, said formation first embolism comprises:
Form the barrier layer that covers said first dielectric layer;
On said barrier layer, form patterned second photoresist, define the position of first embolism;
With said patterned second photoresist is mask, and the said barrier layer of etching and first dielectric layer form first through hole;
Filled conductive material in said first through hole forms first embolism.
Optional, form said first dielectric layer and comprise:
Deposition forms said first dielectric layer;
Said first dielectric layer is carried out chemico-mechanical polishing, afterwards first dielectric layer after the chemico-mechanical polishing is carried out dull and stereotyped etching.
Optional, said formation bottom electrode comprises:
On said second dielectric layer, form patterned the 3rd photoresist, define the position of bottom electrode;
With said patterned the 3rd photoresist is mask, and said second dielectric layer of etching forms first opening;
The filled conductive material forms bottom electrode in said first opening.
Optional, said formation phase change resistor comprises:
On said the 3rd dielectric layer, form patterned the 4th photoresist, define the position of phase change resistor;
With said patterned the 4th photoresist is mask, and said the 3rd dielectric layer of etching forms second opening;
In said second opening, fill phase-change material, form phase change resistor.
Optional, the material of said phase change resistor is chalcogenide or nitrating chalcogenide.
Optional, also comprise: in said dielectric layer, form second embolism and the 3rd embolism, said second embolism is electrically connected with second metal level of said capacitor regions; Said the 3rd embolism is electrically connected with the first metal layer of said capacitor regions.
Optional, said formation second embolism and the 3rd embolism comprise:
On said the 3rd dielectric layer, form patterned the 5th photoresist, define the position of second embolism and the 3rd embolism;
With said patterned the 5th photoresist is mask, and said the 3rd dielectric layer of etching, second dielectric layer and first dielectric layer form second through hole and third through-hole successively;
Filled conductive material in said second through hole and third through-hole forms second embolism and the 3rd embolism.
Optional, also comprise: form first electrode, second electrode and third electrode, said first electrode is electrically connected with said phase change resistor, and said second electrode is electrically connected with said second embolism, and said third electrode is electrically connected with said the 3rd embolism.
Optional, said formation first electrode, second electrode and third electrode comprise:
Form the passivation layer that covers said the 3rd dielectric layer, second embolism, the 3rd embolism and phase change resistor;
Graphical said passivation layer forms the 3rd opening, the 4th opening, the 5th opening in said passivation layer, said the 3rd opening defines the position of first electrode, the position that the 4th opening defines second electrode, the position that the 5th opening defines third electrode;
Filled conductive material in said the 3rd opening, the 4th opening, the 5th opening forms first electrode, second electrode and third electrode.
For addressing the above problem, the present invention also provides a kind of formation method of radio frequency chip, comprises forming electric capacity and phase transition storage, and the method for said formation electric capacity and phase transition storage is the formation method with above-mentioned described semiconductor device.
For addressing the above problem, the present invention also provides a kind of semiconductor device, comprising:
The semiconductor-based end, comprise capacitor regions and phase transition storage zone;
Be formed on the suprabasil electric capacity of said semiconductor, said electric capacity comprises the first metal layer, insulating barrier and second metal level on the capacitor regions that is formed on said substrate successively;
Be formed on the first metal layer on the phase transition storage zone at the said semiconductor-based end, expose substrate between the first metal layer in the first metal layer of said capacitor regions and said phase transition storage zone;
Cover said electric capacity, the first metal layer in phase transition storage zone and the dielectric layer of the said substrate that exposes;
Be formed on the bottom electrode and the phase change resistor of the phase transition storage in the dielectric layer on the phase transition storage zone at the said semiconductor-based end, said bottom electrode is electrically connected with the first metal layer in said phase transition storage zone.
Optional, also comprising first embolism that is formed in the said dielectric layer, said bottom electrode is electrically connected through said first embolism with the first metal layer in said phase transition storage zone.
Optional, said dielectric layer comprises:
First dielectric layer covers said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure, and said first embolism is formed in said first dielectric layer, and said first embolism is electrically connected with the first metal layer in said phase transition storage zone;
Second dielectric layer covers said first dielectric layer and first embolism, and said bottom electrode is formed in said second dielectric layer, and said bottom electrode is electrically connected with said first embolism;
The 3rd dielectric layer covers said second dielectric layer and bottom electrode, and said phase change resistor is formed in said the 3rd dielectric layer, and said phase change resistor is electrically connected with said bottom electrode.
Optional, also comprising second embolism and the 3rd embolism that are formed in the said dielectric layer, said second embolism is electrically connected with second metal level of said electric capacity, and said the 3rd embolism is electrically connected with the first metal layer of said capacitor regions.
Optional, also comprising first electrode, second electrode and third electrode, said first electrode is electrically connected with said phase change resistor, and said second electrode is electrically connected with said second embolism, and said third electrode is electrically connected with said the 3rd embolism.
For addressing the above problem, the present invention also provides a kind of RF identification chip that comprises above-mentioned semiconductor device.
Compared with prior art, technique scheme has following advantage:
Technical scheme of the present invention is through form the first metal layer, insulating barrier and second metal level successively on the same semiconductor-based end; And the semiconductor-based end, the first metal layer, insulating barrier and second metal level comprise phase transition storage zone and capacitor regions respectively; Remove the partial insulative layer and part second metal level of insulating barrier, second metal level and the capacitor regions in phase transition storage zone; Remove the part the first metal layer, expose the substrate between said capacitor regions and the phase transition storage zone, form MIM electric capacity at capacitor regions; Form phase transition storage at memory area; MIM electric capacity and phase transition storage are integrated, realized the compatibility of the two, and it is simple to form technology.And, because the memory cell size of PCRAM is little, can improve the integrated level of semiconductor device, satisfy the demand that the semiconductor technology node progressively reduces.
In specific embodiment; MIM electric capacity and phase transition storage are MIM electric capacity and the phase transition storage in the RF identification chip; Because the memory cell size of PCRAM is little; Therefore can improve the integrated level of RF identification chip, adopt technical scheme of the present invention to make that the production technology of MIM electric capacity is compatible mutually in production technology and the traditional RF identification chip production technology of phase transition storage, and reduced the cost of manufacturing based on the RF identification chip of phase transition storage.
In the specific embodiment of the invention; Forming first dielectric layer; When first dielectric layer is carried out planarization; First dielectric layer is carried out cmp (CMP) earlier again to carrying out dull and stereotyped etching through first dielectric layer behind the said cmp and since dull and stereotyped etching can accurately control the thickness of the layer that is etched therefore carry out carrying out dull and stereotyped etching behind the cmp earlier can be so that the uniformity of first dielectric layer on thickness be better.And, because dull and stereotyped etching can be controlled the thickness of first dielectric layer accurately, therefore can be under the prerequisite of the formation technology that does not change existing phase transition storage, MIM electric capacity and phase transition storage is integrated, reduced the technology cost to a great extent.The method of in addition, first dielectric layer being carried out carrying out behind the cmp dull and stereotyped etching earlier also can reduce directly carries out in the chemical mechanical planarization process because second metal level that the load effect of cmp causes exposes the technology pollution that causes first dielectric layer.
Description of drawings
Fig. 1 is the flow chart of formation method of the semiconductor device of embodiment of the present invention;
Fig. 2 a～Fig. 2 j is the cross-sectional view of method of the formation semiconductor device of the embodiment of the invention.
Embodiment
Like what mention in the background technology, the memory cell of RFID chip is generally SRAM in the prior art, can't satisfy the demand with the increase of technology integrated level that reduces of semiconductor technology node.Because it is little and its advantage aspect the micro of device feature size is also particularly outstanding that PCRAM has memory cell size; The inventor can combine PCRAM and MIM electric capacity through simple technology through studying intensively discovery; Make and the two compatibility promptly satisfied the demand of semiconductor technology process node and technology integrated level.
In order to make those skilled in the art can better understand the present invention, specify embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 1 is the flow chart of formation method of the semiconductor device of embodiment of the present invention, and with reference to figure 1, the formation method of the semiconductor device of embodiment of the present invention comprises:
S10: the semiconductor-based end is provided, on the said semiconductor-based end, forms the first metal layer, insulating barrier and second metal level successively, the said semiconductor-based end, the first metal layer, insulating barrier and second metal level comprise capacitor regions and phase transition storage zone respectively.
S11: remove the partial insulative layer and part second metal level of insulating barrier, second metal level and the capacitor regions in phase transition storage zone, said electric capacity comprises the first metal layer and the remaining insulating barrier and second metal level of capacitor regions.
S12: remove the part the first metal layer, expose the substrate between said capacitor regions and the phase transition storage zone.
S13: form dielectric layer; Cover said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure; In said dielectric layer, form the bottom electrode and the phase change resistor of phase transition storage, said bottom electrode is electrically connected with the first metal layer in said phase transition storage zone.
Fig. 2 a～Fig. 2 j is the cross-sectional view of the formation method of embodiment of the invention semiconductor device.Below in conjunction with Fig. 1 and Fig. 2 a～Fig. 2 j embodiments of the invention are carried out detailed explanation.
In conjunction with Fig. 1 and Fig. 2 a; Execution in step S10: the semiconductor-based end 100 is provided; On the said semiconductor-based end, form the first metal layer 101, insulating barrier 102 and second metal level 103 successively, the said semiconductor-based end 100, the first metal layer 101, insulating barrier 102 and second metal level 103 comprise capacitor regions M and phase transition storage zone P respectively.
Particularly, in the present embodiment, the material at the said semiconductor-based end 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon, germanium, GaAs, silicon Germanium compound or other semi-conducting materials.The said semiconductor-based end 100 can be to have epitaxial loayer or insulating barrier silicon-on, also can be the structure that on monocrystalline silicon, has device layer (for example transistor), also can have the interconnection layer (not shown) at semiconductor-based the end 100.
The material of said the first metal layer 101 can be a kind of in aluminium, copper, aluminium copper, titanium, titanium nitride, tantalum, the tantalum nitride or their combination in any; Its formation method is physical vapor deposition (PVD) or chemical vapor deposition (CVD); In the present embodiment; The material of said the first metal layer 101 is an aluminium, adopts PVD to form said the first metal layer 101, and thickness is 3500～4500 dusts.
The material of said insulating barrier 102 can also can be the material of low-k for high dielectric constant material, specifically choose any material depend in the actual process the size of the MIM capacitance that will make.In the present embodiment; The material of said insulating barrier 102 is a kind of in silica, silicon nitride or the silicon oxynitride; Using plasma strengthens chemical vapour deposition (CVD) (PECVD, plasma enhanced chemical vapor deposition) and forms said insulating barrier 102, and thickness is 300～500 dusts.
The material of said second metal level 103 can be a kind of in aluminium, copper, aluminium copper, titanium, titanium nitride, tantalum, the tantalum nitride or their combination in any; The formation method is PVD or CVD; In the present embodiment; The material of said second metal level 103 is an aluminium, adopts PVD to form said second metal level 103, and thickness is 1200～1400 dusts.
In conjunction with Fig. 1 and Fig. 2 b; Execution in step S11: remove partial insulative layer 102 and part second metal level 103 of insulating barrier 102, second metal level 103 and the capacitor regions M of phase transition storage zone P, said electric capacity comprises the first metal layer 101 and the remaining insulating barrier 102a and the second metal level 103a of capacitor regions M.
In the present embodiment; Partial insulative layer 102 and part second metal level 103 of removing insulating barrier 102, second metal level 103 and the capacitor regions M of phase transition storage zone P comprise: spin coating photoresist on said second metal level 103, and through forming patterned photoresist (not shown) behind the exposure imaging.With patterned photoresist be mask etching second metal level 103, insulating barrier 102 until exposing the first metal layer 101, remove patterned photoresist afterwards.Said etching can be dry etching method or wet etching method; Adopt dry etching in the present embodiment; Through said dry etching, formed MIM electric capacity, said MIM electric capacity comprises the first metal layer 101, and the remaining insulating barrier 102a and the second metal level 103a of capacitor regions M.
In conjunction with Fig. 1 and Fig. 2 c, execution in step S12: remove part the first metal layer 101, expose the substrate between the P of said capacitor regions M and phase transition storage zone.
In the present embodiment; Remove part the first metal layer 101 and promptly remove the first metal layer 101 of capacitor regions M and P junction, phase change memory zone; Comprise: at the surperficial and remaining insulating barrier 102a of the first metal layer 101, the remaining second metal level 103a, the side spin coating photoresist of the remaining second metal level 103a; Exposure imaging; Forming patterned photoresist (not shown), define the position of opening, is the first metal layer 101 of mask etching capacitor regions and phase change memory junction, zone (being opening part) with said patterned photoresist; To expose the substrate between the P of said capacitor regions M and phase transition storage zone, remove patterned photoresist afterwards.
In conjunction with Fig. 1 and Fig. 2 d～2i; Execution in step S13: form dielectric layer; Cover said electric capacity, the first metal layer 101 of phase transition storage zone P and the substrate of said exposure; In said dielectric layer, form the bottom electrode 204 and phase change resistor 205 of phase transition storage, said bottom electrode 204 is electrically connected with the first metal layer 101 of said phase transition storage zone P.
Form dielectric layer in the present embodiment; Cover said electric capacity, the first metal layer 101 of phase transition storage zone P and the substrate of said exposure; In said dielectric layer, form the bottom electrode 204 and phase change resistor 205 of phase transition storage, said bottom electrode 204 is electrically connected with the first metal layer 101 of said phase transition storage zone P and comprises:
Form first dielectric layer 105; Cover said electric capacity, the first metal layer 101 of phase transition storage zone P and the substrate of said exposure, in said first dielectric layer 105, form first embolism 201 that is electrically connected with the first metal layer 101 of said phase transition storage zone P.
Form second dielectric layer 108, cover said first dielectric layer 105 and first embolism 201, in said second dielectric layer 108, form the bottom electrode 204 that is electrically connected with said first embolism 201.
Form the 3rd dielectric layer 110, cover said second dielectric layer 108 and bottom electrode 204, in said the 3rd dielectric layer 110, form the phase change resistor 205 of phase transition storage, said phase change resistor 205 is electrically connected with said bottom electrode 204.
Particularly, in the present embodiment,, form first dielectric layer 105, cover the first metal layer 101 of said electric capacity and phase transition storage zone P with reference to figure 2d.The material of said first dielectric layer 105 can be high dielectric constant material; The structure of said first dielectric layer 105 can be individual layer or the composite bed that is formed by the multilayer high dielectric constant material; In the present embodiment; Said first dielectric layer 105 is an individual layer, and material is a silex glass of mixing fluorine, and thickness is 10000～20000 dusts.The formation method of said first dielectric layer 105 is PECVD.Be uneven owing to cover the surface of first dielectric layer 105 on the first metal layer 101 of electric capacity and phase transition storage zone P, so need carry out planarization to it.
With reference to figure 2e; Form said first dielectric layer 105 backs in deposition it is carried out planarization; In the present embodiment in order not change the parameter that existing P CRAM forms technology; Making that MIM electric capacity and PCRAM are integrated is more prone to, and the technology cost is low, earlier first dielectric layer 105 is carried out CMP technology;, said first dielectric layer 105 carried out dull and stereotyped etching again after being carried out CMP; Coming accurately to control the thickness of said first dielectric layer 105 so that need not to change the parameter that existing P CRAM forms technology when forming PCRAM through dull and stereotyped etching, and aspect thickness, have good uniformity through first dielectric layer 105 after the dull and stereotyped etching, is 5500～6500 dusts through the thickness of first dielectric layer 105 after CMP and the dull and stereotyped etching.
In addition; Employing carries out carrying out behind the CMP method of dull and stereotyped etching earlier to said first dielectric layer 105; Can also prevent because of the grinding scope of CMP bigger; Be ground to the second metal level 102a of capacitor regions M and make to grind in the process of said first dielectric layer 105, and then cause second metal level to expose and the technology that causes is polluted.
Need to prove; In the present embodiment first dielectric layer is carried out carrying out dull and stereotyped etching behind the CMP earlier and should in other embodiments, also can only not carry out CMP as to qualification of the present invention to first dielectric layer; It is thicker that should deposit when deposition forms first dielectric layer this moment; Guarantee when said first dielectric layer is carried out CMP, to be difficult for being ground to second metal level of capacitor regions, and when follow-up formation PCRAM, need adjust the technological parameter of existing formation PCRAM.
With reference to figure 2f; In said first dielectric layer 105, form first embolism 201; The material of first dielectric layer 105 is a silex glass of mixing fluorine from the above; In order to prevent the diffusion of fluorine atom, thus preferably to above-mentioned through first dielectric layer 105 after CMP and the dull and stereotyped etching on deposited barrier layer 106, the thickness on said barrier layer 106 is 2000～3000 dusts.The spin coating first photoresist (not shown) on said barrier layer 106, exposure imaging forms patterned first photoresist, defines the position of first embolism.
Then; With said patterned first photoresist is mask, and the said barrier layer 106 of etching and first dielectric layer 105 form first through hole successively; Remove said patterned first photoresist afterwards; The filled conductive material forms first embolism 201 in said first through hole, and said electric conducting material can be metal, and the mode through sputter in the present embodiment is filled tungsten in said first through hole.The bottom of said first embolism 201 is electrically connected with said the first metal layer 101 with phase transition storage zone P.
In other embodiments, also can not form barrier layer 106, but direct spin coating photoresist on first dielectric layer 105, exposure imaging forms patterned photoresist to define the position of first embolism, in first dielectric layer 105, forms first embolism.
With reference to figure 2g, form second dielectric layer 108, cover said first dielectric layer 105 and first embolism 201, in said second dielectric layer 108, form the bottom electrode 204 that is electrically connected with said first embolism 201.Be specially: form second dielectric layer 108, on said second dielectric layer 108, form the patterned second photoresist (not shown), define the position of bottom electrode.
In the present embodiment; Owing on said first dielectric layer 105, be formed with barrier layer 106, so on said barrier layer 106, form second dielectric layer 108, said second dielectric layer 108 covers the said barrier layer 106 and first embolism 201; Said second dielectric layer, 108 materials are oxide; Like a kind of or its combination in silica, the silicon oxynitride, the formation method is PECVD, and thickness is 1500～2500 dusts.Spin coating second photoresist on said second dielectric layer 108, exposure imaging form the patterned second photoresist (not shown).With said patterned second photoresist is mask, and said second dielectric layer 108 of etching forms first opening; Remove said patterned second photoresist; The filled conductive material is in said first opening, and said electric conducting material is a polysilicon, forms bottom electrode 204, and the bottom of said bottom electrode 204 is electrically connected with the top of said first embolism 201.
Particularly; With reference to figure 2h, form the 3rd dielectric layer 110, cover said second dielectric layer 108 and bottom electrode 204; The material of the 3rd dielectric layer 110 described in the present embodiment can be oxide; Like a kind of or its combination in silica, the silicon oxynitride, the formation method is PECVD, and thickness is 1500～2500 dusts.On said the 3rd dielectric layer 110, form patterned the 5th photoresist (not shown); Define the position of second embolism 202 and the 3rd embolism 203; With said patterned the 5th photoresist is mask, and said the 3rd dielectric layer 110 of etching, second dielectric layer 108, barrier layer 106 and first dielectric layer 105 form second through hole and third through-holes successively.The bottom-exposed of said second through hole goes out the second metal level 103a of said capacitor regions M; The bottom-exposed of said third through-hole goes out the first metal layer 101 of said capacitor regions M; Remove said patterned the 5th photoresist; Filled conductive material in said second through hole and third through-hole forms second embolism 202 and the 3rd embolism 203.Said electric conducting material can be metal, and the mode through sputter in the present embodiment is in said second through hole, fill tungsten in the third through-hole.
With reference to figure 2i, in said the 3rd dielectric layer 110, form the phase change resistor 205 of phase transition storage, said phase change resistor 205 is electrically connected with said bottom electrode 204.
Particularly, form patterned the 4th photoresist (not shown) on said the 3rd dielectric layer 110, on second embolism 202 and the 3rd embolism 203, defining the position of phase change resistor.With said patterned the 4th photoresist is mask, and said the 3rd dielectric layer 110 of etching forms second opening; Remove said patterned the 4th photoresist; In said second opening, fill phase-change material, form phase change resistor 205.The material of phase change resistor described in the present embodiment is chalcogenide or nitrating chalcogenide.Can know that by Fig. 2 i phase transition storage comprises bottom electrode 204 and phase change resistor 205.
Need to prove; The order that forms second embolism and the 3rd embolism, formation phase change resistor in the specific embodiment of the invention can be exchanged; Also promptly can form second embolism earlier and the 3rd embolism forms phase change resistor again, also can form phase change resistor earlier and form two embolisms and the 3rd embolism again.And a kind of generation type describes before in the present embodiment.
With reference to figure 2j; After the formation method of the semiconductor device of present embodiment also is included in and forms first embolism 201, second embolism 202, the 3rd embolism 203, bottom electrode 204 and phase change resistor 205; Form first electrode 301, second electrode 302 and third electrode 303; Said first electrode 301 is electrically connected with said phase change resistor 205, and said second electrode 302 is electrically connected with said second embolism 202, and said third electrode 303 is electrically connected with said the 3rd embolism 203.
Particularly, form first electrode 301, second electrode 302 and third electrode 303 and comprise, form passivation layer 114; The material of said passivation layer 114 is a high dielectric constant material, like silica, silicon nitride etc.Graphical said passivation layer 114; In said passivation layer 114, form the 3rd opening, the 4th opening, the 5th opening, said the 3rd opening defines the position of first electrode 301, the position that the 4th opening defines second electrode 302, the position that the 5th opening defines third electrode 303.Filled conductive material in said the 3rd opening, the 4th opening, the 5th opening, said electric conducting material is a polysilicon, forms first electrode 301, second electrode 302 and third electrode 303.
So far, through above-mentioned steps MIM electric capacity and phase transition storage are integrated together, and above-mentioned processing step is simple, cost is low.
Present embodiment also provides a kind of formation method of radio frequency chip, comprising: form electric capacity and phase transition storage, the method for said formation electric capacity and phase transition storage is the formation method of above-mentioned described semiconductor device.
Referring to Fig. 2 j, present embodiment also provides a kind of semiconductor device that adopts the formation method formation of above-mentioned semiconductor device, comprising: the semiconductor-based end 100,, the said semiconductor-based end 100, comprise capacitor regions P and phase transition storage zone M; Be formed on the electric capacity at the said semiconductor-based end 100, said electric capacity comprises the first metal layer 101, insulating barrier 102 and second metal level 103 on the capacitor regions M that is formed on said substrate successively; Be formed on the first metal layer 101 on the phase transition storage zone P at the said semiconductor-based end 100, expose substrate between the first metal layer 101 of the first metal layer 101 of said capacitor regions M and the regional P of said phase transition storage; Cover said electric capacity, the first metal layer 101 of phase transition storage zone P and the dielectric layer of the said substrate that exposes; Be formed on the bottom electrode 204 and phase change resistor 205 of the phase transition storage in the dielectric layer on the phase transition storage zone P at the said semiconductor-based end 100, said bottom electrode 204 is electrically connected with the first metal layer 101 of the regional P of said phase transition storage.
In the present embodiment preferably; Said bottom electrode 204 is electrically connected through said first embolism 201 with the first metal layer 101 of said phase transition storage zone P; And also comprise second embolism 202 and the 3rd embolism 203 that are formed in the said dielectric layer; Said second embolism 202 is electrically connected with the second metal level 103a of said capacitor regions; Said the 3rd embolism 203 is electrically connected with the first metal layer 101 of said capacitor regions and first electrode 301, second electrode 302 and third electrode 303; Said first electrode 301 is electrically connected with said phase change resistor 205, and said second electrode 302 is electrically connected with said second embolism 202, and said third electrode 303 is electrically connected with said the 3rd embolism 203.
Present embodiment also provides a kind of RF identification chip that comprises above-mentioned semiconductor device.
The formation method of the semiconductor device of present embodiment; Through on the same semiconductor-based end, forming the first metal layer, insulating barrier and second metal level successively, and the first metal layer, insulating barrier and second metal level comprise storage area and capacitor regions respectively, forms electric capacity at capacitor regions; Form phase transition storage at storage area; MIM electric capacity and phase transition storage are integrated, realized the compatibility of the two, and it is simple to form technology.And, because the memory cell size of PCRAM is little, can improve the integrated level of semiconductor device, satisfy the demand that the semiconductor technology node progressively reduces.
The formation method of the RF identification chip of present embodiment integrates MIM electric capacity and PCRAM, because the memory cell size of PCRAM is little, has therefore improved the integrated level of RF identification chip.Adopt the technical scheme of present embodiment to make that the production technology of MIM electric capacity is compatible mutually in production technology and the traditional RF identification chip production technology of phase transition storage, and reduced and made cost based on the RF identification chip of phase transition storage.
The RF identification chip of present embodiment comprises above-mentioned semiconductor device, and integrated MIM electric capacity and phase transition storage have improved the integrated level of RF identification chip, have satisfied the demand that reduces of semiconductor technology node.And, therefore because that PCRAM has is non-volatile, have extended cycle life, good stability, low in energy consumption, can improve life-span, the stability of RFID chip, reduce its power consumption.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (19)
1. the formation method of a semiconductor device, said semiconductor device comprises electric capacity and phase transition storage, it is characterized in that, comprising:
The semiconductor-based end is provided, on the said semiconductor-based end, forms the first metal layer, insulating barrier and second metal level successively, the said semiconductor-based end, the first metal layer, insulating barrier and second metal level comprise capacitor regions and phase transition storage zone respectively;
Remove the partial insulative layer and part second metal level of insulating barrier, second metal level and the capacitor regions in phase transition storage zone, said electric capacity comprises the first metal layer and the remaining insulating barrier and second metal level of capacitor regions;
Remove the part the first metal layer, expose the substrate between said capacitor regions and the phase transition storage zone;
Form dielectric layer; Cover said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure; In said dielectric layer, form the bottom electrode and the phase change resistor of phase transition storage, said bottom electrode is electrically connected with the first metal layer in said phase transition storage zone.
2. the formation method of semiconductor device as claimed in claim 1; It is characterized in that; Form dielectric layer; Cover said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure, in said dielectric layer, form the bottom electrode and the phase change resistor of phase transition storage, said bottom electrode is electrically connected with the first metal layer in said phase transition storage zone and comprises:
Form first dielectric layer, cover said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure, in said first dielectric layer, form first embolism that is electrically connected with the first metal layer in said phase transition storage zone;
Form second dielectric layer, cover said first dielectric layer and first embolism, in said second dielectric layer, form the bottom electrode that is electrically connected with said first embolism;
Form the 3rd dielectric layer, cover said second dielectric layer and bottom electrode, in said the 3rd dielectric layer, form the phase change resistor of phase transition storage, said phase change resistor is electrically connected with said bottom electrode.
3. the formation method of semiconductor device as claimed in claim 2 is characterized in that, said formation first embolism comprises:
On said first dielectric layer, form patterned first photoresist, define the position of first embolism;
With said patterned first photoresist is mask, and said first dielectric layer of etching forms first through hole;
Filled conductive material in said first through hole forms first embolism.
4. the formation method of semiconductor device as claimed in claim 2 is characterized in that, said formation first embolism comprises:
Form the barrier layer that covers said first dielectric layer;
On said barrier layer, form patterned second photoresist, define the position of first embolism;
With said patterned second photoresist is mask, and the said barrier layer of etching and first dielectric layer form first through hole;
Filled conductive material in said first through hole forms first embolism.
5. the formation method of semiconductor device as claimed in claim 2 is characterized in that, forms said first dielectric layer and comprises:
Deposition forms said first dielectric layer;
Said first dielectric layer is carried out chemico-mechanical polishing, afterwards first dielectric layer after the chemico-mechanical polishing is carried out dull and stereotyped etching.
6. the formation method of semiconductor device as claimed in claim 2 is characterized in that, said formation bottom electrode comprises:
On said second dielectric layer, form patterned the 3rd photoresist, define the position of bottom electrode;
With said patterned the 3rd photoresist is mask, and said second dielectric layer of etching forms first opening;
The filled conductive material forms bottom electrode in said first opening.
7. the formation method of semiconductor device as claimed in claim 2 is characterized in that, said formation phase change resistor comprises:
On said the 3rd dielectric layer, form patterned the 4th photoresist, define the position of phase change resistor;
With said patterned the 4th photoresist is mask, and said the 3rd dielectric layer of etching forms second opening;
In said second opening, fill phase-change material, form phase change resistor.
8. the formation method of semiconductor device as claimed in claim 7 is characterized in that, the material of said phase change resistor is chalcogenide or nitrating chalcogenide.
9. the formation method of semiconductor device as claimed in claim 2 is characterized in that, also comprises: in said dielectric layer, form second embolism and the 3rd embolism, said second embolism is electrically connected with second metal level of said capacitor regions; Said the 3rd embolism is electrically connected with the first metal layer of said capacitor regions.
10. the formation method of semiconductor device as claimed in claim 9 is characterized in that, said formation second embolism and the 3rd embolism comprise:
On said the 3rd dielectric layer, form patterned the 5th photoresist, define the position of second embolism and the 3rd embolism;
With said patterned the 5th photoresist is mask, and said the 3rd dielectric layer of etching, second dielectric layer and first dielectric layer form second through hole and third through-hole successively;
Filled conductive material in said second through hole and third through-hole forms second embolism and the 3rd embolism.
11. the formation method of semiconductor device as claimed in claim 9; It is characterized in that; Also comprise: form first electrode, second electrode and third electrode; Said first electrode is electrically connected with said phase change resistor, and said second electrode is electrically connected with said second embolism, and said third electrode is electrically connected with said the 3rd embolism.
12. the formation method of semiconductor device as claimed in claim 11 is characterized in that, said formation first electrode, second electrode and third electrode comprise:
Form the passivation layer that covers said the 3rd dielectric layer, second embolism, the 3rd embolism and phase change resistor;
Graphical said passivation layer forms the 3rd opening, the 4th opening, the 5th opening in said passivation layer, said the 3rd opening defines the position of first electrode, the position that the 4th opening defines second electrode, the position that the 5th opening defines third electrode;
Filled conductive material in said the 3rd opening, the 4th opening, the 5th opening forms first electrode, second electrode and third electrode.
13. the formation method of a RF identification chip comprises: form electric capacity and phase transition storage, it is characterized in that the method for said formation electric capacity and phase transition storage is the formation method of each described semiconductor device of claim 1～12.
14. a semiconductor device is characterized in that, comprising:
The semiconductor-based end, comprise capacitor regions and phase transition storage zone;
Be formed on the suprabasil electric capacity of said semiconductor, said electric capacity comprises the first metal layer, insulating barrier and second metal level on the capacitor regions that is formed on said substrate successively;
Be formed on the first metal layer on the phase transition storage zone at the said semiconductor-based end, expose substrate between the first metal layer in the first metal layer of said capacitor regions and said phase transition storage zone;
Cover said electric capacity, the first metal layer in phase transition storage zone and the dielectric layer of the said substrate that exposes;
Be formed on the bottom electrode and the phase change resistor of the phase transition storage in the dielectric layer on the phase transition storage zone at the said semiconductor-based end, said bottom electrode is electrically connected with the first metal layer in said phase transition storage zone.
15. semiconductor device as claimed in claim 14 is characterized in that, also comprises first embolism that is formed in the said dielectric layer, said bottom electrode is electrically connected through said first embolism with the first metal layer in said phase transition storage zone.
16. semiconductor device as claimed in claim 15 is characterized in that, said dielectric layer comprises:
First dielectric layer covers said electric capacity, the first metal layer in phase transition storage zone and the substrate of said exposure, and said first embolism is formed in said first dielectric layer, and said first embolism is electrically connected with the first metal layer in said phase transition storage zone;
Second dielectric layer covers said first dielectric layer and first embolism, and said bottom electrode is formed in said second dielectric layer, and said bottom electrode is electrically connected with said first embolism;
The 3rd dielectric layer covers said second dielectric layer and bottom electrode, and said phase change resistor is formed in said the 3rd dielectric layer, and said phase change resistor is electrically connected with said bottom electrode.
17. semiconductor device as claimed in claim 14; It is characterized in that; Also comprise second embolism and the 3rd embolism that are formed in the said dielectric layer, said second embolism is electrically connected with second metal level of said capacitor regions, and said the 3rd embolism is electrically connected with the first metal layer of said capacitor regions.
18. semiconductor device as claimed in claim 17; It is characterized in that, also comprise first electrode, second electrode and third electrode, said first electrode is electrically connected with said phase change resistor; Said second electrode is electrically connected with said second embolism, and said third electrode is electrically connected with said the 3rd embolism.
19. RF identification chip that comprises each described semiconductor device of claim 14～18.
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| US10290543B1 (en) * | 2017-12-20 | 2019-05-14 | MACRONXI International Co., Ltd. | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109920761B (en) * | 2017-12-12 | 2021-02-12 | 旺宏电子股份有限公司 | Method for manufacturing semiconductor element |
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