CN102750207A - Motherboard test method and system - Google Patents

Motherboard test method and system Download PDF

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Publication number
CN102750207A
CN102750207A CN2011100954302A CN201110095430A CN102750207A CN 102750207 A CN102750207 A CN 102750207A CN 2011100954302 A CN2011100954302 A CN 2011100954302A CN 201110095430 A CN201110095430 A CN 201110095430A CN 102750207 A CN102750207 A CN 102750207A
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China
Prior art keywords
test
thread
measured
individual event
test item
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Pending
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CN2011100954302A
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Chinese (zh)
Inventor
唐新桥
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CN2011100954302A priority Critical patent/CN102750207A/en
Priority to TW100114080A priority patent/TW201243585A/en
Publication of CN102750207A publication Critical patent/CN102750207A/en
Pending legal-status Critical Current

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Abstract

The invention relates to a motherboard test method, comprising the following steps of: creation step: creating a management thread and a scheduling thread; management step: managing a single item to be tested in a test item pool by the management thread; and scheduling step: taking the single item to be tested from the test item pool for testing, and monitoring the test operation situation by the scheduling thread. The invention also provides a motherboard test system. According to the motherboard test method and system provided by the invention, the test efficiency can be improved in the motherboard test, and the complexity of an arranged parallel testing process can be reduced when the multi-threaded parallel test is adopted.

Description

Mainboard method of testing and system
Technical field
The present invention relates to a kind of mainboard method of testing and system, relate in particular to a kind of method of testing of mainboard efficiently and system.
Background technology
In the automatic test of server master board, more test individual event is generally all arranged, sequencing during these test individual events tests has at present and adopts single-threaded sequential testing, also has to adopt the multi-threaded parallel test.Single-threaded test has the shortcoming that the test duration is long, testing efficiency is low, therefore in the mainboard test, uses the multithreading coded system comparatively to have superiority to improving testing efficiency.A plurality of test individual events of mainboard are tested synchronously, and this is called parallel testing, its use be exactly the parallel test method of multithreading.And the concurrent testing of multithreading need be considered sharing and race problem of hardware resource, when arranging testing process, requires careful consideration, and is comparatively complicated.
Summary of the invention
In view of above content, be necessary to provide a kind of mainboard method of testing, can carry out the mainboard test efficiently, reduce testing cost, improve testing efficiency.
In view of above content, also be necessary to provide a kind of main board testing system, can carry out the mainboard test efficiently, reduce testing cost, improve testing efficiency.
Said mainboard method of testing is applied in the mainboard test, and this method may further comprise the steps: foundation step: create a management thread and a scheduling thread; Management process: management thread is managed individual event to be measured in the test item pond; The scheduling step: scheduling thread takes out individual event to be measured and tests from the test item pond, and control and measuring ruuning situation.
Said main board testing system runs in the computing machine, and this system comprises: create module: be used to create a management thread and a scheduling thread; Administration module: be used for utilizing management thread that the individual event to be measured of test item pond is managed; Scheduler module: be used for utilizing scheduling thread to take out individual event to be measured from the test item pond and test, and control and measuring ruuning situation.
Compared to prior art, described mainboard method of testing and system can reduce the complexity of arranging the parallel testing flow process in the test of mainboard multi-threaded parallel, improve testing efficiency.
Description of drawings
Fig. 1 is the Organization Chart of main board testing system preferred embodiment of the present invention.
Fig. 2 is the functional block diagram of main board testing system preferred embodiment of the present invention.
Fig. 3 is the process flow diagram of mainboard method of testing of the present invention preferred embodiment.
Fig. 4 is the management sub-process figure of mainboard method of testing of the present invention preferred embodiment.
Fig. 5 is the scheduling sublayer process flow diagram of mainboard method of testing of the present invention preferred embodiment.
The main element symbol description
Main frame 10
Mainboard 20
Main board testing system 30
Database 40
Display 50
Keyboard 60
Mouse 70
Create module 301
Administration module 302
Scheduler module 304
Acquisition module one 305
Judge module one 306
Acquisition module two 307
Judge module two 308
Acquisition module three 309
Monitoring module 310
Judge module three 311
Stop the operation module 312
Following embodiment will combine above-mentioned accompanying drawing to further specify the present invention.
Embodiment
As shown in Figure 1, be the Organization Chart of main board testing system preferred embodiment of the present invention.
Said main board testing system 30 runs in the main frame 10.Said main frame 10 is connected with display 50, keyboard 60, mouse 70.Display 50 is used for the display system test result, and keyboard 60 and mouse 70 are used for the user when checking test result and the interactive operation of main frame 10.Also comprise mainboard 20, database 40 in the said main frame 10.
Mainboard 20 is a mainboard to be measured, and its individual event project to be measured is various, comprises CPU, internal memory, hard disk, CD-ROM drive, South Bridge chip group, north bridge chipset, pci bus etc.The failure cause of each individual event to be measured all might be relevant with hardware; Also maybe be relevant with software, it is not right to grasp quantity sometimes like PCI equipment, possibly be that the PCI slot has problem; It is bad that also possibly to be program support the South Bridge chip group of new edition, cause some equipment grasp less than.Database 40 is used for storing the test data of individual event to be measured at test process.
As shown in Figure 2, be the functional block diagram of main board testing system preferred embodiment of the present invention.
Said main board testing system 30 comprises creates module 301, administration module 302, scheduler module 304.Wherein comprise submodule in the administration module 302: acquisition module 1, judge module 1, acquisition module 2 307, judge module 2 308 comprise submodule in the scheduler module 304: acquisition module 3 309, monitoring module 310, judge module 3 311, module 312 runs abort.
Said establishment module 301 is used to create a management thread.
Said administration module 302 is used for utilizing management thread that the individual event to be measured of test item pond is managed.
Said acquisition module 1 is used to utilize management thread regularly to obtain each hardware resource utilization efficient of main frame 10.Said each hardware resource comprises CPU, internal memory, hard disk etc.
Said judge module 1 is used to judge whether each hardware resource utilization efficient all is lower than its corresponding setting value.If all be lower than its corresponding setting value, then in the test item pond, add individual event to be measured; If not all be lower than its corresponding setting value, then in the test item pond, do not add individual event to be measured.Said test item pond is that the notion of using for reference memory pool forms, and refers to a set of individual event to be measured.
Said acquisition module 2 307 is used for utilizing management thread to obtain the individual event quantity to be measured that the test item pond exists.
Whether the individual event quantity to be measured that said judge module 2 308 is used for judging the test item pond is greater than a preset value.If be not more than this preset value, then trigger one 306 pairs of each hardware resource utilization efficient of judge module and proceed to judge; If greater than this preset value, then in the test item pond, do not add individual event to be measured.
Said establishment module 301 also is used to create a scheduling thread.
Said scheduler module 304 is used for utilizing scheduling thread to take out individual event to be measured from the test item pond testing.
Said acquisition module 3 309 is used for utilizing scheduling thread regularly to take out an individual event to be measured from the test item pond, for a test thread is all created in each individual event to be measured of being taken out, and begins to test corresponding individual event to be measured.
Said monitoring module 310 is used to utilize the test run situation of scheduling thread control and measuring thread.
Said judge module 3 311 is used for the test run situation according to the test thread, judges whether test thread test crash is arranged in the main frame 10; If do not test the thread test crash, then trigger the test run situation continued of 310 pairs of tests of monitoring module thread and monitor;
Stopping operation module 312 is used for then showing error message on display 50, and stopping all test threads if any test thread test crash is arranged.
As shown in Figure 3, be the process flow diagram of mainboard method of testing of the present invention preferred embodiment.
Step S100, said establishment module 301 is created a management thread.
Step S101, said administration module 302 utilize management thread that individual event to be measured in the test item pond is managed, and its concrete management process will be introduced among Fig. 4 in detail.
Step S102, said establishment module 301 is created a scheduling thread.
Step S103, said scheduler module 304 is utilized scheduling thread from the test item pond, to take out individual event to be measured and is tested, and monitors the test run situation of individual event to be measured, and it specifically dispatches step, will introduce in detail among Fig. 5.
Need to prove that the scheduling thread among management thread among the step S101 and the step S103 is synchronous operation, management thread is when individual event to be measured is managed in to the test item pond, and scheduling thread takes out individual event to be measured and tests from the test item pond.
As shown in Figure 4, be the management sub-process figure of mainboard method of testing of the present invention preferred embodiment.
Step S1010, said acquisition module 1 regularly obtains each hardware resource utilization efficient of main frame 10.Said each hardware resource comprises CPU, internal memory, hard disk etc.The time interval of said timing can be set to, but is not limited in one minute.
Step S1011, one 306 pairs of each hardware resource utilization efficient of said judge module are judged, see whether each hardware resource utilization efficient all is lower than its corresponding setting value.If all be lower than its corresponding setting value, then execution in step S1012; If not all be lower than its corresponding setting value, then execution in step S1015.These setting values are provided with according to the personal experience, will hang down a bit (such as 80%) such as CPU because a lot of thread will take CPU, and internal memory, hard disk can height a bit (such as hard disk 90%, internal memory 85% etc.).
Step S1012, said administration module 302 add individual event to be measured in the test item pond.
Step S1013, said acquisition module 2 307 obtain existing individual event quantity to be measured in the test item pond.
Step S1014, existing individual event quantity to be measured is judged in 2 308 pairs of test item ponds of said judge module, sees that whether individual event quantity to be measured is greater than a preset value.If greater than this preset value, execution in step S1015 then; If be not more than this preset value, then execution in step S1011.The setting of said preset value is generally decided according to the actual conditions of mainboard test, and is fast such as some mainboard operation test procedure, just can set a higher value (such as 10).
Step S1015, said administration module 302 suspends each hardware resource utilization efficient of monitoring, in the test item pond, does not add individual event to be measured.
As shown in Figure 5, be the scheduling sublayer process flow diagram of mainboard method of testing of the present invention preferred embodiment.
Step S1030, said acquisition module 3 309 regularly takes out an individual event to be measured from the test item pond.The time interval of said timing can be set to, but is not limited in one minute.
Step S1032, said acquisition module 3 309 are that each individual event to be measured of being taken out is all created a test thread and tested, and each individual event to be measured just has a test thread to test.
Step S1033, the test run situation of said monitoring module 310 control and measuring threads.
Step S1034, the test run result of 3 311 pairs of tests of said judge module thread judge, see if there is test thread test crash.If wherein any test thread test crash, then an execution in step S1035; If do not monitored test thread test crash, then returned execution in step S1033.
Step S1035, said termination operation module 312 shows error message on display 50, and stops all test threads.
Need to prove, when not having individual event to be measured in the test item pond, then stop test.
Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although the present invention is specified with reference to preferred embodiment; Those of ordinary skill in the art is to be understood that; Can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and the scope of technical scheme of the present invention.

Claims (10)

1. a mainboard method of testing is characterized in that, this method may further comprise the steps:
Foundation step: create a management thread and a scheduling thread;
Management process: management thread is managed individual event to be measured in the test item pond;
The scheduling step: scheduling thread takes out individual event to be measured and tests from the test item pond, and control and measuring ruuning situation.
2. mainboard method of testing as claimed in claim 1 is characterized in that said management process comprises the steps:
Obtaining step one: management thread is regularly obtained each hardware resource utilization efficient of main frame;
Determining step one: management thread judges whether each hardware resource utilization efficient all is lower than its corresponding setting value; If all be lower than its corresponding setting value; Then in the test item pond, add individual event to be measured,, then in the test item pond, do not add individual event to be measured if not all be lower than its corresponding setting value;
Obtaining step two: management thread is obtained the individual event quantity to be measured that exists in the test item pond;
Determining step two: whether management thread judges individual event quantity to be measured in the test item pond greater than a preset value, if be not more than this preset value, then returns determining step one, if greater than this preset value, then in the test item pond, does not add individual event to be measured.
3. mainboard method of testing as claimed in claim 1 is characterized in that, said scheduling step comprises the steps:
Obtaining step three: scheduling thread regularly takes out an individual event to be measured from the test item pond, and is that a test of each individual event establishment to be measured thread that is taken out is tested;
Monitoring step: the test run situation of scheduling thread control and measuring thread;
Determining step three: scheduling thread has judged whether test thread test crash according to the test run situation of test thread, if do not test the thread test crash, then returns monitoring step;
Stop operating procedure: if any test thread test crash is arranged, then show error message, and stop all test threads.
4. mainboard method of testing as claimed in claim 1 is characterized in that, said test item pond refers to a set of individual event to be measured.
5. mainboard method of testing as claimed in claim 1 is characterized in that management thread and scheduling thread are synchronous operation, and management thread is when individual event to be measured is managed in to the test item pond, and scheduling thread takes out individual event to be measured and tests from the test item pond.
6. a main board testing system is characterized in that, this system comprises:
Create module: be used to create a management thread and a scheduling thread;
Administration module: be used for utilizing management thread that the individual event to be measured of test item pond is managed;
Scheduler module: be used for utilizing scheduling thread to take out individual event to be measured from the test item pond and test, and control and measuring ruuning situation.
7. main board testing system as claimed in claim 6 is characterized in that, said administration module comprises following submodule:
Acquisition module one: be used to utilize management thread regularly to obtain each hardware resource utilization efficient;
Judge module one: be used to judge whether each hardware resource utilization efficient all is lower than its corresponding setting value; If all be lower than its corresponding setting value; Then in the test item pond, add individual event to be measured,, then in the test item pond, do not add individual event to be measured if not all be lower than its corresponding setting value;
Acquisition module two: be used for utilizing management thread to obtain the individual event quantity to be measured that the test item pond exists;
Judge module two: whether the individual event quantity to be measured that is used for judging the test item pond is greater than a preset value; If be not more than this preset value; Then trigger a pair of each the hardware resource utilization efficient of judge module and proceed to judge,, then in the test item pond, do not add individual event to be measured if greater than this preset value.
8. main board testing system as claimed in claim 6 is characterized in that, said scheduler module comprises following submodule:
Acquisition module three: be used for utilizing scheduling thread regularly to take out an individual event to be measured, and be that a test of the individual event establishment to be measured thread that is taken out is tested from the test item pond;
Monitoring module: the test run situation that is used to utilize scheduling thread control and measuring thread;
Judge module three: be used for having judged whether test thread test crash according to the test run situation of test thread; If do not test the thread test crash, then trigger monitoring module the test run situation continued of test thread is monitored;
Stop the operation module: be used for then showing error message, and stopping all test threads if any test thread test crash is arranged.
9. main board testing system as claimed in claim 6 is characterized in that, said test item pond refers to a set of individual event to be measured.
10. main board testing system as claimed in claim 6 is characterized in that management thread and scheduling thread are synchronous operation, and management thread is when individual event to be measured is managed in to the test item pond, and scheduling thread takes out individual event to be measured and tests from the test item pond.
CN2011100954302A 2011-04-18 2011-04-18 Motherboard test method and system Pending CN102750207A (en)

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CN2011100954302A CN102750207A (en) 2011-04-18 2011-04-18 Motherboard test method and system
TW100114080A TW201243585A (en) 2011-04-18 2011-04-22 Board testing method and system

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109976988A (en) * 2019-03-15 2019-07-05 山东云缦智能科技有限公司 A kind of method and device of dynamic configuration graphical interface
CN112579262A (en) * 2019-09-29 2021-03-30 北京君正集成电路股份有限公司 Multithreading parallel processing method with test item adjustment
CN115640118A (en) * 2022-07-19 2023-01-24 信利光电股份有限公司 Method for improving beat of automation equipment by using thread pool

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070220487A1 (en) * 2006-03-17 2007-09-20 Hon Hai Precision Industry Co., Ltd. System for diagnosing and testing computers
CN101661396A (en) * 2008-08-29 2010-03-03 佛山市顺德区顺达电脑厂有限公司 Testing system and method thereof for quickly obtaining testing programs to test mainboard
CN101865975A (en) * 2009-04-16 2010-10-20 鸿富锦精密工业(深圳)有限公司 Main board testing system and method
CN102014294A (en) * 2010-10-25 2011-04-13 福建新大陆通信科技股份有限公司 Method for realizing high-definition hand-hold multi-functional digital video broadcasting-cable (DVB-C) detector

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070220487A1 (en) * 2006-03-17 2007-09-20 Hon Hai Precision Industry Co., Ltd. System for diagnosing and testing computers
CN101661396A (en) * 2008-08-29 2010-03-03 佛山市顺德区顺达电脑厂有限公司 Testing system and method thereof for quickly obtaining testing programs to test mainboard
CN101865975A (en) * 2009-04-16 2010-10-20 鸿富锦精密工业(深圳)有限公司 Main board testing system and method
CN102014294A (en) * 2010-10-25 2011-04-13 福建新大陆通信科技股份有限公司 Method for realizing high-definition hand-hold multi-functional digital video broadcasting-cable (DVB-C) detector

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109976988A (en) * 2019-03-15 2019-07-05 山东云缦智能科技有限公司 A kind of method and device of dynamic configuration graphical interface
CN112579262A (en) * 2019-09-29 2021-03-30 北京君正集成电路股份有限公司 Multithreading parallel processing method with test item adjustment
CN112579262B (en) * 2019-09-29 2024-02-27 北京君正集成电路股份有限公司 Multithreading parallel processing method with test item adjustment
CN115640118A (en) * 2022-07-19 2023-01-24 信利光电股份有限公司 Method for improving beat of automation equipment by using thread pool

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Application publication date: 20121024