CN1027477C - Digit phase detector - Google Patents

Digit phase detector Download PDF

Info

Publication number
CN1027477C
CN1027477C CN 85101167 CN85101167A CN1027477C CN 1027477 C CN1027477 C CN 1027477C CN 85101167 CN85101167 CN 85101167 CN 85101167 A CN85101167 A CN 85101167A CN 1027477 C CN1027477 C CN 1027477C
Authority
CN
China
Prior art keywords
output
input
change over
over switch
subtracter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 85101167
Other languages
Chinese (zh)
Other versions
CN85101167A (en
Inventor
申克·门埃加特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
German Itt Industry Co ltd
TDK Micronas GmbH
Original Assignee
German Itt Industry Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by German Itt Industry Co ltd filed Critical German Itt Industry Co ltd
Priority to CN 85101167 priority Critical patent/CN1027477C/en
Publication of CN85101167A publication Critical patent/CN85101167A/en
Application granted granted Critical
Publication of CN1027477C publication Critical patent/CN1027477C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Complex Calculations (AREA)

Abstract

The present invention relates to a digital phase detector for processing digital signals of which the word length is greater than 10 bits. The digital phase detector does not need a large-capacity read-only memory to store an arctan value and only needs numbers of separate read-only memories (rm 1... rmn) to store an arctan 2 <r> value, wherein r is equal to 1... n. The digital phase detector is provided with n-1 identical stages (S1... Sn-1), and each stage is composed of an adder (ad), a subtracter (sb), two constant multipliers (m1, m2) of which the factor is 2<r> and three transfer switches (u1, u2, u3). The nth stage comprises a constant multiplier (mn) of which the factor is 2 <r>, a subtracter (sbn) and a transfer switch (un).

Description

Digit phase detector
The present invention relates to a digital phase detector, comprise that one becomes digital signal and the analog to digital converter by a clock signal Synchronization to detected analog signal; One 90 ° digital phase shifter (=Hilbert (Hibert) converter=orthogonal signal generator) adds a digital signal that is used to form orthogonal signalling to it; Adjustment circuit to digital signal and orthogonal signalling, it provides corresponding digital quadrant signal x ', y ', and this quadrant signal is first half-quad that belongs to x '-y ' coordinate system; One provides circuit and the read-only memory from the arctan function of y '/x '.In No. 4090145 patents of United States Patent (USP), this type of principle of device has been described.See that this document the 7th hurdle the 58th walks to the 9th hurdle the 7th row, accompanying drawing and digest.In its Fig. 1 and 5 A/D converter is disclosed, 90 ° of phase-shifters of numeral, phase limited signal x ', y ' generation circuit, the arctan function of the y ' of provider/x '.
In this device, the memory space of required read-only memory depends on the definition that requires analog to digital converter, promptly depends on the figure place of processed numeric word, and requiring has 2 nThe memory space of n bit.
For the processing that comprises the video signal of 6 to 8 bits in each word, then requiring has 2 7To 2 9The read-only memory of individual unit, by the semiconductor technology that has earlier, this requirement is to satisfy easily.Yet, when numeric word comprises more multidigit, for example, may require numeric word to contain 13 to 17 for the digital processing of audio signal, corresponding memory space is 2 14To 2 18Bit, like this, the shared chip area of integrated circuit that comprises digital phase detector will that is to say greatly to satisfying, and with the modern semiconductor technology of opening, is to realize a big like this substrate with rationalization expense.Purpose of the present invention as described in the claim, provides the digital phase detector of a mentioned kind, and it can detect digital signal under the situation that does not require big capacity read-only memory, and particularly the figure place of word is greater than 10 digital signal.
Major advantage of the present invention is obvious.In first kind of solution, only need n 2So little read-only memory space; And in second kind of solution, the space requirement of memory further reduced to first kind 1/4th to 1/2nd between.
Now, by explaining the present invention and its further advantage in greater detail with reference to the attached drawings.
Fig. 1 is the block diagram of first kind of embodiment;
Fig. 2 is the block diagram of second embodiment.
Block diagram 1 expression first kind of embodiment of the present invention, input signal is above-mentioned qualified quadrant signal x ', y ', for example, it can produce with the device that above-mentioned US Patent specification is described.The arc tangent signal of corresponding y '/x ', the angle between x ' and formed vector of y ' and the axis of abscissas in x '-y ' seat system just, it has covered first half-quad of this coordinate system, promptly between 0 ° to 45 °.Because the periodicity of tan also can produce with the adjustment circuit that has earlier for the corresponding output signal dp greater than 45 °.
First kind of solution shown in Figure 1 is made up of n-1 identical level s1, s2, sn-1 and n level sn, and design and other grade of sn level are slightly different.N is maximum figure places of the quadrant signal x ', the y ' that are scheduled to.These same stages s1 ... the composition of each of sn-1 has: adder ad; Subtracter sb; The factor is 2 -rFirst and second constant multiplier m1 and the m2, r equals 1 here ... n-1; The the first, the second and the 3rd electronic commutator u1, u2, u3; And arctan2 -rThe read-only memory rm1 of (arc tangent) promptly only stores arctan2 -rValue must provide a read-only memory that occupies the little substrate area of a correspondence at each grade.
In first order s1, quadrant signal x ' is connected to first input of adder ad, the first constant multiplier m1 and the first switch u1, at s2 ... in each level of sn-1, then the output with the first switch u1 of prime is connected to above-mentioned each input.
In first order s1, with second quadrant signal y ', be connected to the first input end of the second constant multiplier m2 and second switch u2, be connected to the minuend input m of subtracter sb simultaneously, at s2 ... among sn-1 at different levels, then the output with the second switch u2 of prime is connected to above-mentioned each input.The output of the second constant multiplier m2 is connected to second input of adder ad, and simultaneously, the subtrahend input s of subtracter sb is linked in the output of the first constant multiplier m1.The output of adder ad is connected to second input of the first switch u1, and the output of subtracter sb is connected to second input of second switch u2, and the 3rd switch u3 first be input as " 0 ", its second input is connected to the output of read-only memory rm1.One of n input of many inputs adder ma linked in the output of the 3rd switch u3.The subtracter sb of each grade meets the control input end that output sg links at the corresponding levels three switch u1, u2 and u3, selected for use combination to distribute simultaneously, so when symbol when negative, first input of each switch is added to output separately, and work as symbol is timing, and output is separately linked in second input of each switch.
The composition of n level sn has: factor 2 -nConstant multiplier mn, its first input end is connected to the output of the first switch u1 of (n-1) level sn-1; Subtracter sbn, its minuend input m is connected to the output of the second switch u2 of prime sn-1, and its subtrahend input s is connected to the output of constant multiplier mn; Switch un, its first input end are " 0 "; And arctan2 -nRead-only memory rmn, its output is connected to second input of switch un, the output of switch un is connected to many inputs adder ma, and its control input end is connected to the symbol output sg of subtracter sbn.
The main difference of first kind of scheme of second kind of solution shown in Figure 2 and Fig. 1 is from the j+1 level, (j can be the integer between 4 to 8).Read-only storage point rm1 among Fig. 1 has been omitted, and this is because independent variable 2 is arranged -j, corresponding tangent value can replace with the independent variable itself with enough accuracy, therefore in Fig. 2 device, the j level of front in design with the s1 of Fig. 1 ... the sn-1 level is identical, and the subtracter sb of Fig. 1 now is defined as the first subtracter sb1.
Comprise n-j-1 identical unit in second kind of solution shown in Figure 2, rather than n-j-1 such identical level of image pattern 1; It comprises (n-j) unit zn, rather than as the n level of Fig. 1, the device of Fig. 2 also comprises (n-j) level register rg, it and line output link the input of many inputs adder ma.Be different from the adder in Fig. 1 device, it has n input there, therefore must carry out the n-1 sub-addition, and the adder of many inputs here ma has only the j+1 input, need only carry out the j sub-addition, so compared to Figure 1 occupy less chip area.
Unit sj+1 shown in Figure 2 has represented each of this same unit, and its composition has: factor is 2 -r 'Three constant multiplier m3, first input of this multiplier is connected to the output of the first switch u1 of j level sj; The 4th switch u4, its first input is connected to the output of the second switch u2 of j level sj in the j+1 unit, and the first input end of switch u4 is connected to the output of the 4th switch of last unit in the unit of back; The second subtracter sb2, its minuend input m and subtrahend input s are connected respectively to the first input end of the 4th switch u4 and the output of three constant multiplier m3.And the output of subtracter sb2 is connected to second input of the 4th switch, and its symbol output sg is connected to the control input end of the 4th switch u4; Reverser iv, its input are connected to the symbol output sg of the 4th switch u4.Superincumbent factor 2 -r 'In, r ' equals j+1 ... n-1.
Among this scheme, as Fig. 1, as quite related subtracter sb1, sb2, the symbol sg of symbol output when negative, switch u1, u2, u3(are at level s1 ... among the sj) and u4(in all unit) first input end be connected to output, and the symbol sg that works as the symbol output is timing, and second input of these switches is connected to output.
The composition of (o-j) individual unit zn has: factor is 2 -nConstant multiplier mn, its first input end is connected to the output of the first switch u1 of j level sj; Subtracter sbn, its minuend input m and subtrahend input s are connected respectively to output and the constant multiplier mn of the 4th switch u4; Its input of inverter ivn. is connected to the symbol output sg of subtracter sbn.
All inverter iv ... the output of ivn according to their power, be connected to the level input of register rg, and the also line output of register rg is connected to the input of many inputs adder ma.The output of ma provides digit phase detection signal dp, and it is positioned at first half-quad of x '-y ' coordinate system, promptly between 0 ° to 45 °.
In the drawings, inner lead is just represented with simple line, is not considered the concrete enforcement of circuit.Yet this can not hinder understanding, and the parallel of quadrant signal x ', y ' also is possible.In this case, inner lead-in wire is conventional bus, and the number of its also alignment is corresponding to the figure place of processed numeric word.At this moment, adder, subtracter, multiplier and change over switch all are corresponding parallel processing parts.Can select this kind embodiment for use if require high speed signal to handle, its master-plan can be implemented with " pipelining ".
If high conversion speed is not so important, two kinds of embodiments of the present invention can be simplified by the multipath conversion technology, promptly the level and the sum of unit be less than the figure place of quadrant signal x ', y ', and will pass through a unit several times in each processing cycle.
Two kinds of embodiments of the present invention are based on such consideration:
With two replacement u=x '+by '; V=x '-by ', its phase angle dp can define by relational expression dp=arctan u/v+arctanb.If invention is implemented with binary ciruit, then b=2 -rThe present invention also is based on the Recursion Application of above-mentioned relation formula.
The present invention is suitable for making integrated circuit very much, particularly MOS circuit, i.e. insulated-gate type field effect transistor circuit.Concrete application of the present invention is the detection in amplitude modulation (AM) the stereo broadcasting system of a Unite States Standardization, the detection of sound of television signal and the detection of very high frequency(VHF) (VHF) broadcast singal in audio system.The present invention also can be used for the colour signal demodulation of sequential storing and be used in magnetic chart resembling record, in video tape recorder.

Claims (2)

1, digital phase detector comprises:
An analog to digital converter, being used for detected analog signal conversion is digital signal, and synchronous by a clock signal;
One 90 ° digital phase-shifting technique is suitable, and it is added a digital signal that is used to form orthogonal signalling;
One is used for the numeral and the adjustment circuit of orthogonal signalling, and its output has provided the digital quadrant signal that belongs to the correspondence of first half-quad in x '-y ' coordinate system (x ', y ');
With the circuit of the arctan function of the y ' of a provider/x ', and comprise a read-only memory;
It is characterized in that:
The composition of this circuit has: input adder more than (ma), a n level (sn) and n-1 same stages (s1 ... sn-1), n is the maximum number of digits of predetermined quadrant signal (x ', y ');
This n-1 each identical composition is: an adder (ad); A subtracter (sb); Factor is 2 -rFirst and second constant multipliers (m1, m2), r=1 here ... n-1; The the first, the second and the 3rd electronic commutator (u1, u2, u3); With one be used for arctan2 -rRead-only memory 2 (rm1).
In the first order (s1), be connected to the first input end of adder (ad), first constant multiplier (m1) and first change over switch (u1) through a quadrant signal (x '), at other (s2 ... sn-1) at different levels, then the output with first change over switch (u1) of prime is connected to above-mentioned each input;
At the first order (s1), second quadrant signal (y '), be connected to the first input end of second constant multiplier (m2) and second change over switch (u2), and be connected to the minuend input (m) of subtracter (sb), at other (s2 ... sn-1) among at different levels, then the output for second change over switch (u2) of prime is connected to above-mentioned each input;
The output of second constant multiplier (m2) is connected to second input of adder (ad), and the output of first constant multiplier (m1) is connected to the subtrahend input (s) of subtracter (sb);
The output that the output of adder (ad) is connected to the second input subtracter (sb) of first change over switch (u1) is connected to second input of second change over switch (u2);
Digital " 0 " is supplied with the first input end of the 3rd change over switch (u3), second input of the 3rd change over switch (u3) is connected to the output of read-only memory (rm1), and the output of switch (u3) is connected in n input of many inputs adder (ma) one;
The symbol of subtracter (sb) output (sg) is connected to the output that each first input of three change over switches (u1, u2, u3) is connected to this switch, and when symbol be timing, second input of switch is connected to its output;
The composition of n level (sn) has: a factor is 2 -nAdditional constant multiplier (mn), its input is connected to the output of first change over switch (u1) of (n-1) level (sn-1); An additional subtracter (sbn), its minuend input (m) and subtrahend input (s) are connected respectively to the output of the second change over switch u2 of (n-1) level (sn-1) and the output of additional constant multiplier (mn); An additional change over switch (un), its first input end are " 0 "; With one for arctan2 -nRead-only memory (rmn), its output is connected to second input of additional changeover switch (un), the output of switch (un) is connected to many inputs adder (ma), the control input end of switch (un) is connected to the symbol output (sg) of additional subtracter (sbn), and the output of many inputs adder (ma) supplies the digit phase detection signal (dp) of this first half-quad of coordinate system.
2, digital phase detector comprises:
A horizontal number converter, being used for detected analog signal conversion is digital signal, and synchronous by a clock signal;
One 90 ° digital phase shifter adds a digital signal that is used to form orthogonal signalling to it;
One is used for the numeral and the adjustment circuit of orthogonal signalling, and its output has provided the digital quadrant signal (x ', y ') of the correspondence of first half-quad in x '-y ' coordinate system;
With the circuit of the arctan function of the y ' of a provider/x ', and comprise a read-only memory;
It is characterized in that:
The composition of this circuit has: input adder more than (ma); One (n-j) level register (rg); (n-j-1) individual identical unit (sj+1 ...); (n-j) individual unit (zn); Level (the s1 identical with j ... sj), the maximum number of digits of the n quadrant signal (signal x ', y ') that equals to be scheduled to here; J is an integer between 4 and 8;
The composition of each grade has: an adder (ad); First subtracter (sb1); Factor is 2 -rFirst and second constant multipliers (m1, m2), r=1 here ... n-1; The the first, the second and the 3rd electronic commutator (u1, u2, u3); With one be used for arctan2 -rRead-only memory (rm1);
In the first order (s1), first quadrant signal (x ') is connected to the first input end of adder (ad), first constant multiplier (m1) and first change over switch (u1), at other (s2 ... sj) at different levels, then be that the output with first change over switch (u1) of prime is connected to above-mentioned each input;
The output of second constant multiplier (m2) is connected to second input of adder (ad), and the output of first constant multiplier (m1) is connected to the subtrahend input (s) of first subtracter (sb1);
The output of adder (ad) is connected to second input of first change over switch (u1), and the output of first subtracter (sb1) is connected to second input of second change over switch (u2);
Digital " 0 " is given the first input end of the 3rd change over switch (u3), second input of this change over switch (u3) is connected to the output of read-only memory (rm1), and the output of switch (u3) is connected in j+1 the input of many inputs adder (ma) one;
The symbol output (sg) of first subtracter (sb1) is connected to the control input end of three change over switches (u1, u2, u3);
The composition of each unit (sj+1) has: factor is 2 -r 'Three constant multiplier (m3), r '=j+1 here ... n-1, its input is connected to the output of first change over switch (u1) of j level (sj); The 4th change over switch (u4), its first input is connected to the output of second change over switch (u2) of j level (sj) in (j+1) unit, and in other each unit, first input of switch (u4) is connected to the output of the 4th change over switch of last unit; Second subtracter (sb2), its minuend input (m) and subtrahend input (s) are connected respectively to the first input end of the 4th change over switch (u4) and the output of three constant multiplier (m3), and the output of subtracter (sb2) is connected to second input of the 4th change over switch (u4), and its symbol output (sg) is connected to the control input end of the 4th change over switch (u4); An inverter (iv), its input is connected to the symbol output (sg) of the 4th change over switch (u4);
As two subtracter (sb1, when the symbol (sg) of symbol output sb2) is negative, the change over switch that is associated (u1, u2, u3, u4) be connected to the output separately of these switches through an input, and work as symbol is timing, and second input of the change over switch that is associated is connected to the output of these switches;
The composition of the individual unit of first (n-j) (zn) has: a factor is 2 -nAdditional constant multiplier (mn), its input is connected to the output of first change over switch (u1) of j level (sj); An additional subtracter (sbn), its minuend input (m) and subtrahend input (s) are connected to the output of the 4th change over switch (u4) of last unit and the output of additional constant multiplier (mn) respectively; An additional inverter (ivn), its input are connected to the symbol output (sg) of additional subtracter (sbn);
All inverter (iv ... ivn) output, according to their power, be connected to the level input that is associated of register (rg), and the also line output of register (rg) is connected to an input of many inputs adder (ma), and the output of many inputs adder (ma) provides the digit phase detection signal (dp) of first half-quad of this coordinate system.
CN 85101167 1985-04-01 1985-04-01 Digit phase detector Expired - Lifetime CN1027477C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 85101167 CN1027477C (en) 1985-04-01 1985-04-01 Digit phase detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 85101167 CN1027477C (en) 1985-04-01 1985-04-01 Digit phase detector

Publications (2)

Publication Number Publication Date
CN85101167A CN85101167A (en) 1987-01-24
CN1027477C true CN1027477C (en) 1995-01-18

Family

ID=4791660

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 85101167 Expired - Lifetime CN1027477C (en) 1985-04-01 1985-04-01 Digit phase detector

Country Status (1)

Country Link
CN (1) CN1027477C (en)

Also Published As

Publication number Publication date
CN85101167A (en) 1987-01-24

Similar Documents

Publication Publication Date Title
US4482974A (en) Apparatus and method of phase-to-amplitude conversion in a sine function generator
CA1175154A (en) Shift circuit
US4677499A (en) Digital time base corrector
US5138567A (en) Median filter
EP0334357B1 (en) Pulse insertion circuit
US4325075A (en) Digital television video signal storage system
US4910514A (en) D/A converter
US5671166A (en) Barrel shifter for combining pieces of data into a piece of combined data and shifting the combined data
EP0570164B1 (en) Interleaved memory system
GB2215569A (en) Multi-page teletext decoder arrangements
US5787273A (en) Multiple parallel identical finite state machines which share combinatorial logic
CN1027477C (en) Digit phase detector
US5847588A (en) Programmable multiple CCD clock synthesizer
US4130894A (en) Loop organized serial-parallel-serial memory storage system
US4755817A (en) Data transmission system having transmission intervals which are adjustable for data words of various lengths
US4528511A (en) Circuit for digital FM demodulation
US5142487A (en) Numerically controlled oscillator
WO1997031316A1 (en) Demultiplexer for a multi-bitline bus
US5379038A (en) Parallel-serial data converter
EP0350027A3 (en) Sample-hold circuit
EP0201128B1 (en) Integrated electronic multiplex circuit and integrated electronic circuit including such a multiplex circuit
US5333263A (en) Digital image processing apparatus
US4213191A (en) Variable length delay line
JPH0685488B2 (en) Digital phase detector
US3299406A (en) Multiple access delay structures

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CX01 Expiry of patent term