CN102739247B - Frequency synthesizer and frequency synthesis method for converting spurious tone to noise - Google Patents
Frequency synthesizer and frequency synthesis method for converting spurious tone to noise Download PDFInfo
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- CN102739247B CN102739247B CN201110086443.3A CN201110086443A CN102739247B CN 102739247 B CN102739247 B CN 102739247B CN 201110086443 A CN201110086443 A CN 201110086443A CN 102739247 B CN102739247 B CN 102739247B
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Abstract
The invention provides a frequency synthesizer and a frequency synthesis method for converting a spurious tone to noise. One of the advantages of a direct frequency synthesis technology (such as flying-adder architecture) is that the technology produces arbitrarily variable frequencies through the concept of time average frequency. At an output end of the frequency synthesized by direct frequency, a period with a single type is replaced by a period with two types. Different from a traditional frequency with the period with a single type, wherein the frequency energy is focused on the design frequency, a frequency based on time average frequency spreads a part of the energy to the spurious tone that may be harmful in some application. The spurious tone is resulted from the periodic carrysequence of a fraction adder in the frequency synthesizer. The invention provides the method and the device to break the periodicity and to convert the spurious tone to wide band noise.
Description
Technical field
The invention relates to a kind of frequency synthesizer and frequency combining method, and relate to especially a kind of can metoxeny keynote be noise frequency synthesizer and frequency combining method.
Background technology
Frequency synthesizer (frequency synthesizer) can provide the frequency source of accurate stable over a range of frequencies, and it is common in modern electronics such as radio receiver, mobile phone, satellite receiver or global positioning system.Frequency synthesis technique comprises direct-type frequency synthesis (direct frequency synthesis) and indirect type frequency synthesis (indirect synthesis) etc.Wherein, direct-type frequency synthesis technique comprises direct-type digit pulse rate (directdigital pulse rate) and very fast accumulator (flying-adder) framework etc., there is frequency shift speed fast and can produce the advantages such as changeable arbitrarily frequency, but it easily produces too much stray wave (spur), and then cause the frequency spectrum as the output signal of analog-digital converter or digital analog converter that frequency synthesizer is controlled to comprise unnecessary parasitic keynote (spurious tone).
The carry sequence (carrysequence) because of the accumulator regularity in frequency synthesizer is led in fact in the generation of stray wave.Please refer to 1A figure, 1B figure and 1C figure, 1A figure illustrates the schematic diagram of an example of the accumulator of legacy frequencies synthesizer, 1B figure illustrates the accumulation result oscillogram of the accumulator of the legacy frequencies synthesizer of corresponding 1A figure, and 1C figure illustrates the signal spectrum figure of the legacy frequencies synthesizer of corresponding 1A figure and the carry sequence of different fractional arithmetic.In 1A figure, traditional accumulator 05 adopts a control character FREQ, and (comprise that sub-practice r) of the sub-I of integer arithmetic and fractional arithmetic is to produce carry sequence, wherein the sub-r of fractional arithmetic is certain value.Because the sub-r of fractional arithmetic is definite value, therefore accumulation result can be stablized and increase and the carry sequence that produces of traditional accumulator 05 can have regularity as shown in Figure 1B.Observing 1C figure can learn, the stray wave producing because of regular carry sequence, makes the frequency spectrum of carry sequence comprise unnecessary parasitic keynote.In addition the parasitic keynote that, the sub-r of different fractional arithmetics causes is also different.
Please refer to 1D figure and 1E figure, 1D figure illustrates another routine schematic diagram of the accumulator of legacy frequencies synthesizer, and 1E figure illustrates the accumulation result oscillogram of the accumulator of the legacy frequencies synthesizer of corresponding 1D figure.In 1D figure, tradition accumulator 10 adopts interpolation one random number (random number) v (to comprise that sub-practice r) of the sub-I of integer arithmetic and fractional arithmetic is to can break the regularity of carry sequence as shown in 1E figure, and then wish to improve the generation of stray wave and reach the result of passing at random look (dithering) in control character FREQ.
But adding random number has many disadvantages in the practice of control character.The best size and the best adding rate of for example random number all can not determine easily, but need to see through trial and error pricing (try and error) repetitive operation in the hope of optimum value.In addition, in order to make output frequency constant, the ensemble average value of random number is necessary for zero, hereat in circuit design, needs to use signed digital system (signed number system) system, increases system complexity and cost.Further, in the time of high velocity mode of operation, need to use high-speed adder could add random number, expend a large amount of hardware resources.
Summary of the invention
The invention relates to a kind of frequency synthesizer and frequency combining method, is noise by metoxeny keynote, and then is removed the negative effect that parasitic keynote produces for total system.
According to a first aspect of the invention, propose a kind of frequency synthesizer, comprise cumulative unit and a frequency generator.Cumulative unit comprises a mark accumulator, a buffer unit and an integer accumulator.Mark accumulator is in order to do accumulating operation to export a carry sequence based on fractional arithmetic, carry sequence comprises multiple carry digits.Buffer unit writes these carry digits in order to foundation one first random address sequence, and reads these carry digits according to one second random address sequence, and the second random address sequence has nothing to do in the first random address sequence.Integer accumulator does accumulating operation to continue to export a count value in order to these carry digits based on an integer arithmetic and that read.Frequency generator is in order to export a frequency signal according to count value.
According to a second aspect of the invention, propose a kind of frequency combining method, comprise the following steps.Do accumulating operation to export a carry sequence based on fractional arithmetic, carry sequence comprises multiple carry digits.Write these carries according to one first random address sequence and be positioned at a buffer unit, and more read these carry digits according to one second random address sequence from buffer unit, the second random address sequence has nothing to do in the first random address sequence.These carry digits based on an integer arithmetic and that read do accumulating operation to continue to export a count value.Export a frequency signal according to count value.
For above-mentioned and other side of the present invention is had to better understanding, preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below:
Brief description of the drawings
Figure 1A illustrates the schematic diagram of an example of the accumulator of legacy frequencies synthesizer.
Figure 1B illustrates the accumulation result oscillogram of the accumulator of the legacy frequencies synthesizer of corresponding 1A figure.
Fig. 1 C illustrates the signal spectrum figure of the legacy frequencies synthesizer of corresponding 1A figure and the carry sequence of different fractional arithmetic.
Fig. 1 D illustrates another routine schematic diagram of the accumulator of legacy frequencies synthesizer.
Fig. 1 E illustrates the accumulation result oscillogram of the accumulator of the legacy frequencies synthesizer of corresponding 1D figure.
Fig. 2 A illustrates the calcspar according to the frequency synthesizer of preferred embodiment of the present invention.
Fig. 2 B illustrates the schematic diagram according to the cumulative unit of the frequency synthesizer of preferred embodiment of the present invention.
Fig. 3 illustrates the schematic diagram according to an example of the address production electric circuit of preferred embodiment of the present invention.
Fig. 4 A illustrates the signal spectrum figure of legacy frequencies signal.
Fig. 4 B illustrates the signal spectrum figure according to the frequency signal of preferred embodiment of the present invention.
Fig. 5 A illustrates the signal spectrum figure according to the carry sequence of 511 big or small storage elements of correspondence of preferred embodiment of the present invention.
Fig. 5 B illustrates the signal spectrum figure according to the carry sequence of 63 big or small storage elements of correspondence of preferred embodiment of the present invention.
Fig. 6 illustrates the flow chart according to the frequency combining method of preferred embodiment of the present invention.
Embodiment
The present invention proposes a kind of frequency synthesizer and frequency combining method, taking metoxeny keynote (spurious tone) as noise, and then be minimized or remove the negative effect that parasitic keynote produces for total system by randomization evolutionary sequence (carrysequence).
Please refer to 2A figure and 2B figure, 2A figure illustrates the calcspar according to the frequency synthesizer of preferred embodiment of the present invention, and 2B figure illustrates the schematic diagram according to the cumulative unit of the frequency synthesizer of preferred embodiment of the present invention.Frequency synthesizer 100 comprises cumulative unit 110 and a frequency generator (clock generator) 120.Cumulative unit 110 comprises a mark accumulator 112, a buffer unit 114 and an integer accumulator 116.Mark accumulator 112 is in order to do accumulating operation to export a carry sequence C S based on the sub-r of a fractional arithmetic, carry sequence C S is one 1 bit data crossfires, and it sequentially comprises multiple carry digits.Wherein, carry sequence C S now still has regularity based on the sub-r of fractional arithmetic.
Buffer unit 114 is in order to write these carry digits according to one first random address sequence, and to read these carry digits according to one second random address sequence be the carry digit carry_in reading, and the second random address sequence has nothing to do in the first random address sequence.Owing to not having relevance between the first random address sequence and the second random address sequence, therefore write between the order of carry digit of buffer unit 114 and the order of the carry digit read from buffer unit 114 and there is random degree; That is carry digit writes different between the order of reading and the random degree of tool, the regularity of carry sequence C S is broken.Integer accumulator 116 is in order to do accumulating operation to continue to export a count value count based on the sub-I of an integer arithmetic and these carry digits carry_in of reading.Frequency generator 120 is in order to export a frequency signal clk according to count value count.
Not having the first random address sequence of relevance and a second random address sequence can be recorded in a look-up table (not being illustrated in figure) and use when the access for buffer unit 114.In addition, also can produce circuit 118 to provide the first random address sequence and the second random address sequence to buffer unit 114 in included one-over-one address in cumulative unit 110.The implementation method of address production electric circuit 118 does not limit in the present invention, it can utilize is as shown in Figure 3 for example a linear feedback bit shift register (the linear feedback shiftregister of 6 address bits (b[0]～b[5]) size, LFSR) 119 produce the first random address sequence, then can produce incoherent the second random address sequence by bit reversal (bitwise inverse).In addition, if by the link position of contact N by b[4] change to other address bit, can also produce other random address sequence irrelevant with the first random address sequence and the second random address sequence.
In 2B figure, in the time that the accumulating operation of the sub-r of fractional arithmetic does not produce carry, corresponding carry digit is 0, and in the time that the accumulating operation of the sub-r of fractional arithmetic produces carry, corresponding carry digit is 1.In addition, the size of buffer unit 114 is for example (2
p-1) position, P is greater than 1 positive integer.Because traditional memory size is generally 2P position, therefore the size of buffer unit 114 can be chosen for (2
p-1) position, thus, the regularity of the size of buffer unit 114 and carry sequence C S repeats the difficult multiple each other of bit number, will more be conducive to the object of randomization evolutionary sequence of this case.
Hereby lift the sub-r of fractional arithmetic and equal 0.2, and the size of buffer unit 114 to be for example 63 (P equals 6) explain for example.Under above-mentioned supposition, the carry digit b that carry sequence C S is included
1, b
2..., b
m... be sequentially 0,0,0,0,1,0,0,0,0,1 ..., 0,0,0,0,1 ... repeat.First, buffer unit 114 writes carry digit b in a first frequency cycle T 1 according to the first random address sequence
1～b
63, b
1～b
63comprise 12 " 1 " and 51 " 0 ".Then, buffer unit 114 reads according to the second random address sequence the carry digit b being stored in buffer unit 114 in a second frequency cycle T 2
1～b
63.Because 12 " 1 " and 51 " 0 " are by random writing according to the first random address sequence, therefore the original regularity of tool not of the distribution in buffer unit 114, be read out according to incoherent the second random address sequence again afterwards, the queueing discipline of the carry digit of therefore reading is compared to the carry digit b of original arrangement
1, b
2..., b
62, b
63there is especially suitable random degree.
Meanwhile, in order to save frequency period, in second frequency cycle T 2, often read a carry digit after randomization, will sequentially write follow-up carry digit (b
64, b
65..., b
125, b
126).That is buffer unit 114 writes carry digit b according to the second random address sequence in second frequency cycle T 2 simultaneously
64, b
65..., b
125, b
126.Afterwards, based on 63 and 5 multiples each other not, buffer unit 114 reads according to the first random address sequence the carry digit b being stored in buffer unit 114 at one the 3rd frequency period T3
64～b
126, and the carry digit b reading after simultaneously writing according to the first random address sequence
127, b
128..., b
188, b
189.
From the above, incoherent the first random address sequence and the second random address sequence have been enough to make original carry sequence C S to produce suitable random degree and destroy regularity.But if want further to carry high-irregularity, buffer unit can read according to one the 3rd random address sequence the carry digit b being stored in buffer unit 114 at one the 3rd frequency period T3
64～b
126, and the carry digit b reading after simultaneously writing according to the 3rd random address sequence
127, b
128..., b
188, b
189, the 3rd random address sequence has nothing to do in the first random address sequence and the second random address sequence.That is every 63 carry digits change the different random address sequence of employing, the regularity of carry sequence C S will be destroyed up hill and dale.Thus, the count value count that integer accumulator 116 is exported also can not have regularity, therefore can effectively reduce the generation of stray wave.
Please refer to 4A figure and 4B figure, 4A figure illustrates the signal spectrum figure of legacy frequencies signal, and 4B figure illustrates the signal spectrum figure according to the frequency signal of preferred embodiment of the present invention.Relatively 4A figure and 4B figure can learn, after frequency synthesizer randomization evolutionary sequence of the present invention, metoxeny keynote is converted to noise effectively, therefore the negative effect that total system is led because producing in parasitic keynote is minimized or removes.Therefore, frequency synthesizer 100 of the present invention will be more suitable for control example as the electronic installation such as analog-digital converter or digital analog converter.
In addition, please refer to 5A figure and 5B figure, 5A figure illustrates the signal spectrum figure according to the carry sequence of 511 big or small storage elements of correspondence of preferred embodiment of the present invention, and 5B figure illustrates the signal spectrum figure according to the carry sequence of 63 big or small storage elements of correspondence of preferred embodiment of the present invention.Relatively 5A figure and 5B figure can learn, frequency synthesizer of the present invention does not need to adopt huge internal memory effectively metoxeny keynote to be converted to noise effectively, therefore can not waste hardware resource and maintain low cost.
The present invention more proposes a kind of frequency combining method, please refer to the 6th figure, and it illustrates the flow chart according to the frequency combining method of preferred embodiment of the present invention.In step S600, do accumulating operation to export a carry sequence based on fractional arithmetic, carry sequence comprises multiple carry digits.In step S610, write these carries according to one first random address sequence and be positioned at a buffer unit, and more read these carry digits according to one second random address sequence from buffer unit, the second random address sequence has nothing to do in the first random address sequence.In step S620, these carry digits based on an integer arithmetic and that read do accumulating operation to continue to export a count value.In step S630, export a frequency signal according to count value.
The principle system of said frequencies synthetic method has been specified in 2A figure the～the 5B figure and related content thereof, therefore no longer repeat in this.
The disclosed frequency synthesizer of the above embodiment of the present invention and frequency combining method, have multiple advantages, below only enumerates part advantage and be described as follows:
Frequency synthesizer of the present invention and frequency combining method, utilize different random address sequences and be able to randomization evolutionary sequence, and by the evolutionary sequence after randomization effectively metoxeny keynote be noise, and then be minimized or remove the negative effect that parasitic keynote produces for total system.Because frequency synthesizer of the present invention does not need to adopt huge internal memory, therefore can not waste hardware resource and maintain low cost.In addition, do not need additional high-speed adder to add random number, therefore be conducive to high speed operation.
In sum, although the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention when with accompanying claim scope the person of being defined be as the criterion.
Claims (14)
1. a frequency synthesizer, comprising:
One cumulative unit, comprising:
One mark accumulator, in order to do accumulating operation based on fractional arithmetic to export a carry sequence, described carry sequence comprises a plurality of carry digits;
One buffer unit, in order to write described carry digit according to one first random address sequence, and reads described carry digit according to one second random address sequence, and described the second random address sequence has nothing to do in described the first random address sequence; And
One integer accumulator, does accumulating operation to continue to export a count value in order to described carry digit based on an integer arithmetic and that read; And
One frequency generator, in order to export a frequency signal according to described count value.
2. frequency synthesizer as claimed in claim 1, is characterized in that, described the first random address sequence and described the second random address sequential recording are in a look-up table.
3. frequency synthesizer as claimed in claim 1, it is characterized in that, described cumulative unit more comprises an address production electric circuit, and described address production electric circuit utilizes a linear feedback bit shift register to produce described the first random address sequence and described the second random address sequence.
4. frequency synthesizer as claimed in claim 1, is characterized in that, in the time that the accumulating operation of described fractional arithmetic does not produce carry, corresponding carry digit is 0, and in the time that the accumulating operation of fractional arithmetic produces carry, corresponding carry digit is 1.
5. frequency synthesizer as claimed in claim 1, is characterized in that, the size of described buffer unit is (2
p-1) position, P is greater than 1 positive integer.
6. frequency synthesizer as claimed in claim 5, is characterized in that, when described carry digit is b
1, b
2..., b
m... time, described buffer unit writes described carry digit b in a first frequency cycle according to described the first random address sequence
1, b
2..., b
(P-1), described buffer unit reads described carry digit b in a second frequency cycle according to described the second random address sequence
1, b
2..., b
(P-1), and write described carry digit b according to described the second random address sequence simultaneously
p, b
(P+1)..., b
2 (P-1), described buffer unit reads described carry digit b at one the 3rd frequency period according to described the first random address sequence
p, b
(P+1)..., b
2 (P-1).
7. frequency synthesizer as claimed in claim 5, is characterized in that, when described carry digit is b
1, b
2..., b
m... time, described buffer unit writes described carry digit b in a first frequency cycle according to described the first random address sequence
1, b
2..., b
(P-1), described buffer unit reads described carry digit b in a second frequency cycle according to described the second random address sequence
1, b
2..., b
(P-1), and write described carry digit b according to described the second random address sequence simultaneously
p, b
(P+1)..., b
2 (P-1), described buffer unit reads described carry digit b at one the 3rd frequency period according to one the 3rd random address sequence
p, b
(P+1)..., b
2 (P-1), described the 3rd random address sequence has nothing to do in described the first random address sequence and described the second random address sequence.
8. a frequency combining method, comprising:
Do accumulating operation to export a carry sequence based on fractional arithmetic, described carry sequence comprises a plurality of carry digits;
Write described carry according to one first random address sequence and be positioned at a buffer unit, and read described carry digit according to one second random address sequence from described buffer unit, described the second random address sequence has nothing to do in described the first random address sequence;
Described carry digit based on an integer arithmetic and that read does accumulating operation to continue to export a count value; And
Export a frequency signal according to described count value.
9. frequency combining method as claimed in claim 8, is characterized in that, described the first random address sequence and described the second random address sequential recording are in a look-up table.
10. frequency combining method as claimed in claim 8, is characterized in that, more comprises:
Utilize a linear feedback bit shift register to produce described the first random address sequence and described the second random address sequence.
11. frequency combining methods as claimed in claim 8, is characterized in that, in the time that the accumulating operation of described fractional arithmetic does not produce carry, corresponding carry digit is 0, and in the time that the accumulating operation of fractional arithmetic produces carry, corresponding carry digit is 1.
12. frequency combining methods as claimed in claim 8, is characterized in that, the size of described buffer unit is (2
p-1) position, P is greater than 1 positive integer.
13. frequency combining methods as claimed in claim 12, is characterized in that, when described carry digit is b
1, b
2..., b
m... time, described frequency combining method more comprises:
Write described carry digit b in a first frequency cycle according to described the first random address sequence
1, b
2..., b
(P-1)in described buffer unit;
Read described carry digit b according to described the second random address sequence from described buffer unit in a second frequency cycle
1, b
2..., b
(P-1), and write described carry digit b according to described the second random address sequence simultaneously
p, b
(P+1)..., b
2 (P-1)in described buffer unit; And
Read described carry digit b according to described the first random address sequence from described buffer unit at one the 3rd frequency period
p, b
(P+1)..., b
2 (P-1).
14. frequency combining methods as claimed in claim 12, is characterized in that, when described carry digit is b
1, b
2..., b
m... time, described frequency combining method more comprises:
Write described carry digit b in a first frequency cycle according to described the first random address sequence
1, b
2..., b
(P-1)in described buffer unit;
Read described carry digit b according to described the second random address sequence from described buffer unit in a second frequency cycle
1, b
2..., b
(P-1), and write described carry digit b according to described the second random address sequence simultaneously
p, b
(P+1)..., b
2 (P-1)in described buffer unit; And
Read described carry digit b according to one the 3rd random address sequence from described buffer unit at one the 3rd frequency period
p, b
(P+1)..., b
2 (P-1), described the 3rd random address sequence has nothing to do in described the first random address sequence and described the second random address sequence.
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Citations (1)
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|---|---|---|---|---|
| CN1685616A (en) * | 2002-06-20 | 2005-10-19 | 诺基亚有限公司 | Digital delta-sigma modulator in a fractional-N frequency synthesizer |
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|---|---|---|---|---|
| US7564313B2 (en) * | 2004-08-13 | 2009-07-21 | Mediatek Inc. | Phase locked loop for controlling a recording device and method thereof |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1685616A (en) * | 2002-06-20 | 2005-10-19 | 诺基亚有限公司 | Digital delta-sigma modulator in a fractional-N frequency synthesizer |
Non-Patent Citations (3)
| Title |
|---|
| Liming Xiu.A Fast and Power - Area-Efficient Accumulator for Flying-Adder Frequency Synthesizer.《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I:REGULAR PAPERS》.2009,第56卷(第11期),全文. |
| Liming Xiu.A Fast and Power- Area-Efficient Accumulator for Flying-Adder Frequency Synthesizer.《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I:REGULAR PAPERS》.2009,第56卷(第11期),全文. * |
| 吴恩德等.分数N频率综合器的杂散分析.《清华大学学报(自然科学版)》.2004,第44卷(第7期),全文. * |
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