CN102737570B - Control driver of display panel - Google Patents
Control driver of display panel Download PDFInfo
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- CN102737570B CN102737570B CN201110172948.1A CN201110172948A CN102737570B CN 102737570 B CN102737570 B CN 102737570B CN 201110172948 A CN201110172948 A CN 201110172948A CN 102737570 B CN102737570 B CN 102737570B
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Abstract
Provided is a control driver of a display panel, comprising a time sequence control circuit, a data memory unit, a data selection unit and a data line driving circuit. The data memory unit stores image data. The data selection unit is coupled to the data memory unit and selects the image data provided by the data memory unit as display data or produces display data based on instructions and/or test sample provided by an external processor. The data line driving circuit is coupled to the time sequence control circuit and the data selection unit. The data line driving circuit receives the display data from the data selection unit, and outputs relevant gray level voltage based on control signal output by the time sequence control circuit.
Description
Technical field
The present invention relates to a kind of display device, and particularly relate to a kind of control and drive system driving display panel.
Background technology
Please refer to Fig. 1, for the block diagram that the conventional control drive 120 of display panel 140 forms is described.This control and drive system 120 comprises system interface circuit (System Interface Circuit) 122, reservoir control circuit (Memory Control Circuit) 124, image data reservoir (Image Data Memory) 126, sequential control circuit (Timing Control Circuit) 128, data line drive circuit (Data Line Driving Circuit) 132, scan line drive circuit (ScanLine Driving Circuit) 134 and gray scale voltage generation circuit (Grayscale VoltageGenerating Circuit) 136.System interface circuit 122 is couple to outside processor 110, and data line drive circuit 132 and scan line drive circuit 134 are then be couple to display panel 140.
When control and drive system 120 operates in normal manipulation mode (Normal Operation Mode), processor 110 sends display data to reservoir control circuit 124 via system interface circuit 122.Display data are temporary in image data reservoir 126 by reservoir control circuit 124.Processor 110 sends control signal to sequential control circuit 128 via system interface circuit 122.Sequential control circuit 128 sends corresponding control signal to reservoir control circuit 124, data line drive circuit 132 with scan line drive circuit 134 chronologically.Such as, sequential control circuit 128 reads from image data reservoir 126 image data corresponding to same sweep trace image frame via reservoir control circuit 124, and image data is latched the data output end in reservoir control circuit 124.Complete the read operation of described image data at reservoir control circuit 124 after, sequential control circuit 128 is control data line drive circuit 132 and scan line drive circuit 134 further, to be sent to by the image data of the data output end being latched in reservoir control circuit 124 in the picture element of corresponding sweep trace in display panel 140.By that analogy, the image data corresponding to other sweep traces in image frame is sent in the picture element of corresponding sweep trace in display panel 140 by control and drive system 120, shows corresponding image according to this.
Fig. 2 A is the sequential chart (Timing Diagram) of control and drive system 120 shown in key diagram 1 at normal manipulation mode.Comprise multiple output terminal at this hypothesis scan line drive circuit 134, drive the 1st sweep trace G1 of display panel 140, the 2nd sweep trace G 2, the 3rd sweep trace G3 ..., N number of sweep trace GN and other sweep traces respectively.The gate address GA every schedule time change is transmitted from sequential control circuit 128.Scan line drive circuit 134 sequentially drives the sweep trace of display panel 140 according to gate address GA.As shown in Fig. 2 A first half, by a set time, in the time of a namely picture (Frame), N number of lock is divided into drive period T.Based on the control of sequential control circuit 128, scan line drive circuit 134 drives period T sequentially to drive a wherein sweep trace of display panel 140 respectively at different lock.
The display data (Display Data) of the datawire driver (DataLine Driver) in (1) data line drive circuit 132 are comprised in Fig. 2 A Lower Half; (2) latch signal of the data output end controlling reservoir control circuit 124 is transmitted from sequential control circuit 128; (3) the reading pulse in order to control image data reservoir 126 by reservoir control circuit 124 is transmitted from sequential control circuit 128.
When control and drive system 120 operates in test mode of operation (Test Operation Mode), test pattern (Test Pattern) first will be write image data reservoir 126 by system interface circuit 122 and reservoir control circuit 124 by outside processor 110 in advance.After test pattern is write image data reservoir 126, test pattern then reads from image data reservoir 126 via reservoir control circuit 124 by sequential control circuit 128 chronologically, and test pattern is sent to data line drive circuit 132.Test pattern exports by sequential control circuit 128 further control data line drive circuit 132.Output by external testing instrument measurement data line drive circuit 132 judges that whether control and drive system 120 is by test.
Please refer to Fig. 2 B, Fig. 2 B is for control and drive system 120 shown in key diagram 1 is at the process flow diagram of test mode of operation.First, as step S205, outside processor 110 (such as test platform) starts control and drive system 120, and makes control and drive system 120 enter test mode of operation by control signal TE.As step S210, test pattern (Test Pattern) is write image data reservoir 126 through system interface circuit 122 and reservoir control circuit 124 via write paths by outside processor 110 (such as test platform).Then, as step S220, test pattern read from image data reservoir 126 via read-out path, namely test pattern is read out to data line drive circuit 132 from image data reservoir 126 by reservoir control circuit 124.Then, as step S230, by the output of measurement data line drive circuit 132, can judge that whether control and drive system 120 is by test.If not by test, then as step S250, terminate this testing process.But in this way by test, then then carry out step S240 to determine whether last test pattern.If so, then as step S250, this testing process is terminated.If test pattern is not last test pattern at present, then get back to step S210, next test pattern write image data reservoir 126 by the processor 110 of outside, and again to carry out next test procedure, namely carry out step S210 ~ S250 again.
In testing process, for the display timing generator figure (Display TimingDiagram) of control and drive system 120, then as shown in Figure 3.The image data reservoir that this display timing generator figure comprises (1) reservoir control circuit 124 reads enable signal (image data memory read enable signal ofthe memory control circuit 124); (2) row address (Row Address); (3) output (output of the image data memory 126) of image data reservoir 126; (4) the latch enable signal (Latches Enable signal ofthe data output terminals of the memory control circuit 124) of reservoir control circuit 124 data output end; (5) data line of data line drive circuit 132 drives enable signal (Data Line Driving Enablesignal of the data line driving circuit 132); And the data line of (6) data line drive circuit 132 exports (Data Line Output of the data line drivingcircuit 132).
When reservoir control circuit 124 receive sequential control circuit 128 send row address and image data reservoir read the pulse of enable signal time, within a schedule time, the operation of reading data can be completed to image data reservoir 126.Such as shown in Fig. 3, receive the pulse of image data reservoir reading enable signal at reservoir control circuit 124 after, in time interval TR, can read image data reservoir 126 according to row address, and after time interval TR, the display data of correspondence are read from image data reservoir 126, the display data of the N row of such as Fig. 3.And at this moment between in interval TR, the data line that sequential control circuit 128 exports to data line drive circuit 132 drives enable signal to be in logic high state, and data line drive circuit 132 exports the display data of N-1 row.
After time interval TR, reservoir control circuit 124 completes the read operation of N row display data, and now sequential control circuit 128 can transmit and latch enable signal to reservoir control circuit 124.Reservoir control circuit 124 is after receiving the pulse of latching enable signal (Latches Enable), the display data of aforementioned N row can be latched in the data output end of reservoir control circuit 124, and the display data that N arranges are supplied to data line drive circuit 132.Therefore during the data line that data line drive circuit 132 can export at sequential control circuit 128 drives enable signal to be in logic high state, the display data that N arranges are supplied to the data line of display panel 140.By that analogy, reservoir control circuit 124 reads the pulse of enable signal according to image data reservoir, sequentially exports the display data that N+1 arranges N+n-1 row.
For conventional control drive 120, no matter be normal manipulation mode or test mode of operation, all utilize identical transmission channel transmission display data and test pattern.Above-mentioned framework, when carrying out test operation to control and drive system 120, must consider the transfer efficiency at interface and the restrictive condition of transmission channel.These issuable delays significantly will increase the time of test and reduce the efficiency of test.
Such as the control and drive system IC that mobile phone uses, test duration is longer, all the stand-by period is needed when test data, wherein the stand-by period includes the time that test data is write static random access memory (SRAM is equivalent to image data reservoir 126) by a.; B. test data is read the time delivering to source electrode drive circuit (Source Driver is equivalent to data line drive circuit 132) by SRAM.These two actions are all relevant with SRAM access speed.
Summary of the invention
The invention provides a kind of control and drive system of display panel, to improve the testing efficiency of control and drive system.
The embodiment of the present invention proposes a kind of control and drive system of display panel, comprises sequential control circuit, data accumulating unit, data selection unit and data line drive circuit.Sequential control circuit exports control signal.Data accumulating unit stores image data.Data selection unit is coupled to data accumulating unit.Data selection unit selects to export image data that data accumulating unit provides as display data, or the instruction provided according to ppu and/or test pattern produce display data.Data line drive circuit is coupled to sequential control circuit and data selection unit.Data line drive circuit receives the display data from data selection unit, and exports corresponding gray scale voltage according to control signal.
In one embodiment of this invention, when control and drive system operates in normal manipulation mode, the image data that data accumulating unit exports directly reportedly is delivered to data line drive circuit as display by data selection unit.When control and drive system operates in test mode of operation, the instruction that data selection unit provides according to described ppu or test pattern produce display data to data line drive circuit.
In one embodiment of this invention, when control and drive system operates in test mode of operation, the test pattern that described ppu exports is supplied to data line drive circuit as display data by data selection unit.
In one embodiment of this invention, when control and drive system operates in test mode of operation, data selection unit produces corresponding test pattern to data line drive circuit as display data according to this instruction that described ppu exports.
In one embodiment of this invention, when control and drive system operates in test mode of operation, after this instruction is decoded by data selection unit, optionally this test pattern is supplied to the part of data line drive circuit or all passages as display data according to decoded result.
In one embodiment of this invention, above-mentioned data selection unit comprises multiple logical block.The output terminal of each logical block is connected respectively to multiple output-stage circuits wherein one of data line drive circuit.Wherein, these logical blocks select the image data that data accumulating unit provides to export to these output-stage circuits, or the instruction provided according to described ppu or test pattern produce display data to these output-stage circuits.
In one embodiment of this invention, above-mentioned control and drive system also comprises system interface circuit.System interface circuit is coupled to data accumulating unit, data selection unit and sequential control circuit.Wherein, described ppu via the move instruction of system interface circuit or test pattern to data selection unit.
In one embodiment of this invention, above-mentioned data accumulating unit comprises image data reservoir and reservoir control circuit.Image data reservoir stores described image data.Reservoir control circuit is coupled between image data reservoir and data selection unit.
Based on above-mentioned, the image data that the data selection unit that the embodiment of the present invention discloses can select output data accumulating unit to provide is as display data.Or data selection unit the instruction that provides of selection gist ppu or test pattern can produce this display data.Therefore, control and drive system can not need test pattern to write data accumulating unit, does not also need from data accumulating unit read test pattern, and then improves the testing efficiency of control and drive system.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the function block diagram of the conventional control drive that display panel is described.
Fig. 2 A is that control and drive system shown in key diagram 1 is at the sequential chart of normal manipulation mode.
Fig. 2 B is for control and drive system shown in key diagram 1 is at the process flow diagram of test mode of operation.
Fig. 3 is for control and drive system shown in key diagram 1 is at the sequential chart of test mode of operation.
Fig. 4 is the function block diagram that a kind of control and drive system is described according to the embodiment of the present invention.
Fig. 5 is the testing process schematic diagram according to control and drive system shown in embodiment of the present invention key diagram 4.
Fig. 6 is the signal sequence schematic diagram of control and drive system under test mode of operation shown in foundation embodiment of the present invention key diagram 4.
Fig. 7 is the partial circuit block diagram that control and drive system is described according to another embodiment of the present invention.
Fig. 8 A and Fig. 8 B is the signal sequence schematic diagram according to control and drive system test pattern under test mode of operation shown in embodiment of the present invention key diagram 4.
Reference numeral:
110,410: processor
120,400: control and drive system
122,420: system interface circuit
124,422: reservoir control circuit
126,426: image data reservoir
128,424: sequential control circuit
132,432: data line drive circuit
134,434: scan line drive circuit
136,436: gray scale voltage generation circuit
140,440: display panel
428: data selection unit
710
0, 710
1, 710
2, 710
n-1: latch units
720
0, 720
1, 720
2, 720
n-1: logical block
730
0, 730
1, 730
2, 730
n-1: output-stage circuit
G1, G2, G3, GN: sweep trace
GA: gate address
S205 ~ S250, S510 ~ S550: step
TE: control signal
TP: test pattern
Embodiment
Please refer to Fig. 4, for the present invention illustrates the block diagram of the embodiment that display forms.Control and drive system 400 at least comprises system interface circuit (System Interface Circuit) 420, data accumulating unit, sequential control circuit (Timing Control Circuit) 424, data selection unit (Data Selection Unit) 428, data line drive circuit (Data Line DrivingCircuit) 432, scan line drive circuit (Scan Line Driving Circuit) 434 and gray scale voltage generation circuit (Grayscale Voltage Generating Circuit) 436.Above-mentioned data accumulating unit comprises reservoir control circuit (Memory Control Circuit) 422 and image data reservoir (Image Data Memory) 426.System interface circuit 420 is couple to outside processor 410 (or test platform), and data line drive circuit 432 and scan line drive circuit 434 are then be couple to display panel 440 (or test platform).
In the embodiment shown in fig. 4, data selection unit 428 is configured between reservoir control circuit 422 and data line drive circuit 432.The embodiment of data selection unit 428 shown in Fig. 4 can be decoding circuit, duplex circuit, logical circuit or other circuit, and such as Fig. 7 shows wherein a kind of embodiment (being detailed later) of data selection unit 428.
Please refer to Fig. 4, processor 410 is electrically connected to reservoir control circuit 422, data selection unit 428 and sequential control circuit 424, so that transfer instruction (Commands), control signal and image data via system interface circuit 420.System interface circuit 420 is in order to coupling and transmission of confluxing as instruction, control signal or data transmission.
When control and drive system 400 operates in normal manipulation mode (Normal Operation Mode), processor 410 sends image data and multiple control signal to reservoir control circuit 422, sequential control circuit 424 and data selection unit 428 respectively via system interface circuit 420.The image data that ppu 410 provides is temporary in image data reservoir 426 by reservoir control circuit 422.Sequential control circuit 424 carries out various control operation according to described control signal.Such as, sequential control circuit 424 controls reservoir control circuit 422 and is read from image data reservoir 426 by image data, and output latch signal and make reservoir control circuit 422 data output end latch image data, image data is sent to data selection unit 428.When normal manipulation mode, data selection unit 428 based on ppu 410 control signal TE and be in the state of non-activation, data selection unit 428 is directly sent to data line drive circuit 432 by controlling the image data that reservoir control circuit 422 exports.Sequential control circuit 424 further exports control signal so that control data line drive circuit 432 and scan line drive circuit 434.According to the control of sequential control circuit 424, and coordinate the operation of scan line drive circuit 434, image data can be converted to gray scale voltage by data line drive circuit 432, and is sent to by gray scale voltage in the picture element of display panel 440, shows corresponding image according to this.Above-mentioned reservoir control circuit 422 reads the details of operation of image data from image data reservoir 426, and sequential control circuit 424, data line drive circuit 432 and scan line drive circuit 434 drive the details of operation of display panel 440, can with reference to the related description of Fig. 1.
When control and drive system 400 operates in test mode of operation (Test Operation Mode), the testing process of control and drive system 400 will be carried out.In test mode of operation, described processor 410 can be test platform, then the output terminal of control and drive system 400 is electrically connected to the surveying instrument of test platform.Now, data selection unit 428 is in the state of activation based on the control signal TE of processor 410, make data selection unit 428 select to receive test instruction from the processor 410 (such as test platform) of outside and/or be test pattern (Test Patterns) TP, then the test pattern TP of correspondence is sent to data line drive circuit 432 and tests.The visual different test of outside processor 410 designs and adjusts this test pattern TP, to meet customized demand.
The testing process schematic diagram of control and drive system 400, then as shown in Figure 5.First, as step S510, outside processor 410 (such as test platform) starts control and drive system 400, and makes control and drive system 400 enter test mode of operation by control signal TE, to start the transmission channel of test pattern.Then, as step S520, instruction (Commands) and/or test pattern TP are write data selection unit 428 by processor 410.Such as, test pattern TP can be supplied to data line drive circuit 432 by data selection unit 428 by processor 410.In other embodiments, processor 410 can send instruction to data selection unit 428, and produces corresponding test pattern TP to data line drive circuit 432 by data selection unit 428 according to this instruction.In the present embodiment, when control and drive system 400 operates in test mode of operation, after the instruction that ppu 410 provides is decoded by data selection unit 428, optionally test pattern TP is supplied to the part of data line drive circuit 432 or all passages as display data according to decoded result.Such as, processor 410 output order and test pattern TP can be respectively " 00 " and " GTG 0 ".Data selection unit 428 just provides the test pattern TP of " GTG 0 " after instruction " 00 " being decoded to all passages of data line drive circuit 432.Therefore, all output terminals of data line drive circuit 432 all should export the driving voltage of " GTG 0 " ideally.Again such as, processor 410 output order and test pattern TP can be respectively " 01 " and " GTG 255 ".Data selection unit 428 just provides the display data of " GTG 255 ", and the even number passage of data line drive circuit 432 is provided to the display data of " GTG 0 " after instruction " 01 " being decoded to the odd number passage of data line drive circuit 432.
Then step S530, whether the output of measurement data line drive circuit 432 is by test.If not by test, then as step S550, terminate this testing process.But in this way by test, then then processor 410 carries out step S540 to judge whether current test pattern is last test pattern.If current test pattern is last test pattern, then as step S550, terminate this testing process.If current test pattern is not last test pattern, then get back to step S520, namely processor 410 sends next instruction and/or test pattern TP to control and drive system 400, to test for next test pattern.
As mentioned above, in test mode of operation, data selection unit 428 can transmit corresponding test pattern to data line drive circuit 432 according to the instruction of processor 410, and does not need to go accessing image data storage 426 by reservoir control circuit 422.Therefore, above-mentioned testing process does not need to write frequently and read operation image data reservoir 426, makes control and drive system 400 can accelerated test speed.
To the testing process sequential chart (TimingDiagram) of control and drive system 400 under test mode of operation, then as shown in Figure 6.The figure of display timing generator shown in Fig. 6 comprises instruction and/or the test pattern TP of (1) data selection unit 428; (2) data line of data line drive circuit 432 drives enable signal (Data Line Driving Enable); And the data line of (3) data line drive circuit 432 exports (Data Line Output).
Such as shown in Fig. 6, in time interval TC, data selection unit 428 can receive N-1 instruction and/or test pattern TP from the processor 410 of outside, and transmits N-1 corresponding test pattern to data line drive circuit 432.Therefore, data line drive circuit 432 can obtain N-1 test pattern, and tests for N-1 test pattern.At next time interval T
cin, data selection unit 428 receives N number of instruction and/or test pattern TP from processor 410, and transmits corresponding N number of test pattern to data line drive circuit 432.The data line exporting to data line drive circuit 432 at sequential control circuit 424 drives under enable signal is in the high state of logic, and data line drive circuit 432 can export N number of test pattern.Now, test platform can be measured the output of data line drive circuit 432, to test for N number of test pattern (Test Patterns).By that analogy, processor 410 sequentially can send N+1 to N+n-1 instruction and/or test pattern TP, and control and drive system 400 sequentially can carry out for N+1 to N+n-1 test pattern the test showing data accordingly, the display test of different test pattern can be completed according to design.
Please refer to Fig. 7, is the partial circuit block diagram of another embodiment of control and drive system 400 proposed by the invention.Embodiment illustrated in fig. 7 can with reference to the related description of Fig. 4.In the embodiment shown in fig. 7, each data output end each self-configuring latch units of reservoir control circuit 422, such as latch units 710
0, 710
1, 710
2..., 710
n-1.Each passage each self-configuring output-stage circuit (Output Stage Circuit) of data line drive circuit 432, such as output-stage circuit 730
0, 730
1, 730
2..., 730
n-1.Gray scale voltage generation circuit 436 provides multiple gray scale voltage signal to each output-stage circuit 730 of data line drive circuit 432
0~ 730
n-1.These output-stage circuits 730
0~ 730
n-1the gray scale voltage that can output one selected from described multiple gray scale voltage corresponding according to digit data.
Data selection unit 428 is configured between reservoir control circuit 422 and data line drive circuit 432.Each passage in data selection unit 428 each self-configuring logical block, such as logical block 720
0, 720
1, 720
2..., 720
n-1.Each logical block 720
0, 720
1, 720
2..., 720
n-1first input end be connected respectively to described latch units 710
0, 710
1, 710
2..., 710
n-1the wherein output terminal of one, and each logical block 720
0, 720
1, 720
2..., 720
n-1the second input end be connected to outside processor 410 via system interface circuit 420 respectively.Each logical block 720 in data selection unit 428
0, 720
1, 720
2..., 720
n-1output terminal be connected respectively to the output-stage circuit (Output Stage Circuit) 730 of data line drive circuit 432
0, 730
1, 730
2..., 730
n-1wherein one.
When control and drive system 400 operates in normal manipulation mode (Normal Operation Mode), data selection unit 428 is in the state of non-activation.That is, each logical block 720 in data selection unit 428
0, 720
1, 720
2..., 720
n-1separately by latch units 710
0, 710
1, 710
2..., 710
n-1the display data exported directly are sent to each output-stage circuit (Output Stage Circuit) 730 of data line drive circuit 432
0, 730
1, 730
2..., 730
n-1.
When control and drive system 400 operates in test mode of operation (Test Operation Mode), data selection unit 428 is in the state of activation.That is, each logical block 720 in data selection unit 428
0, 720
1, 720
2..., 720
n-1the instruction that receiving processor 410 exports and at least one test pattern TP, and each output-stage circuit (Output Stage Circuit) 730 test pattern being sent to data line drive circuit 432
0, 730
1, 730
2..., 730
n-1, to carry out the test of data line drive circuit.
In the above-mentioned testing process to control and drive system 400, directly can receive instruction and test pattern TP from processor 410, and test pattern is sent to data line drive circuit 432 and test.And the visual different designs of this test pattern and adjusting, to meet customized demand.
Such as, in one embodiment, processor 410 output order and test pattern TP can be respectively " 01 " with " GTG 255 " to logical block 720
0~ 720
n-1.Logical block 720
0~ 720
n-1after instruction " 01 " is decoded, just respectively the odd number output-stage circuit (such as 7301) of data line drive circuit 432 is provided to the display data of " GTG 255 ", and the even number output-stage circuit (such as 730 to data line drive circuit 432
0with 730
2) the display data of " GTG 0 " are provided.Processor 410 output order and test pattern TP can be respectively " 10 " with " GTG 255 " to logical block 720
0~ 720
n-1.Logical block 720
0~ 720
n-1after instruction " 10 " is decoded, just respectively to the even number output-stage circuit (such as 730 of data line drive circuit 432
0with 730
2) the display data of " GTG 255 " are provided, and the odd number output-stage circuit (such as 730 to data line drive circuit 432
1) the display data of " GTG 0 " are provided.Test pattern can as shown in Figure 8 A, each logical block 720 in data selection unit 428
0, 720
1, 720
2..., 720
n-1different gray scale voltages is provided, to test the phenomenon whether be short-circuited between adjacent data passage to the adjacent data passage of data line drive circuit 432.
Such as the display data of eight bits, its gray scale voltage is 0 ~ 255 standard, therefore, as logical block 720
0to output-stage circuit 730
0impose and represent gray scale voltage position standard when being the test data of 0, then logical block 720
1to output-stage circuit 730
1then impose and represent the test data that gray scale voltage position standard is 255, and logical block 720
2to output-stage circuit 730
2then impose and represent the test data that gray scale voltage position standard is 0, logical block 720
3to output-stage circuit 730
3then impose and represent the test data that gray scale voltage position standard is 255, by that analogy.Therefore, when data line drive circuit 432 is good, can at output-stage circuit 730
0output terminal and output-stage circuit 730
2measurement of output end to gray scale voltage position standard be 0 voltage, and at output-stage circuit 730
1the measurement of output end of output terminal to gray scale voltage position standard be 255 voltage.In another cycle, then conversely, when logical block 720
0to output-stage circuit 730
0impose and represent gray scale voltage position standard when being the test data of 255, logical block 720
1to output-stage circuit 730
1then impose and represent the test data that gray scale voltage position standard is 0, and logical block 720
2to output-stage circuit 730
2then impose and represent the test data that gray scale voltage position standard is 255, by that analogy.
Such as, in another embodiment, processor 410 output order and test pattern TP can be respectively " 00 " with " GTG 0 " to logical block 720
0~ 720
n-1.Logical block 720
0~ 720
n-1after instruction " 00 " is decoded, just respectively to output-stage circuit 730
0~ 730
n-1the test data of " GTG 0 " is provided.Test pattern as shown in Figure 8 B, all output-stage circuits 730 in the same cycle to data line drive circuit 432
0~ 730
n-1all carry out identical gray scale voltage test.Therefore, all output-stage circuits 730 ideally
0~ 730
n-1output terminal all should export the driving voltage of " GTG 0 ".At next cycle, processor 410 output order and test pattern TP can be respectively " 00 " with " GTG 1 " to logical block 720
0~ 720
n-1, make logical block 720
0~ 720
n-1respectively to output-stage circuit 730
0~ 730
n-1the test data of " GTG 1 " is provided.Therefore, all output-stage circuits 730 ideally
0~ 730
n-1output terminal all should export the driving voltage of " GTG 1 ".By that analogy, 0th ~ 255 cycles as shown in Figure 8 B, 720
0~ 720
n-1sequentially export the luma data of 0 ~ 255 to output-stage circuit 730
0~ 730
n-1, and output-stage circuit 730
0~ 730
n-1sequentially export the gray scale voltage of 0 ~ 255.So, the test pattern shown in Fig. 8 B can test out individually each output-stage circuit 730
0, 730
1, 730
2, ~ 730
n-1the degree of variation of (i.e. each passage of control and drive system 400), also can test out the numerical digit analogy conversion performance of control and drive system 400 and the driving force to each GTG.
Above-mentioned test structure and testing process, will effectively reduce the test duration and efficiency of carrying out data line drive circuit.
In sum, the data selection unit 428 that discloses of the embodiment of the present invention can the image data that provides of image output data storage 426 as display data.Or the instruction that data selection unit 428 can provide according to ppu 410 and/or test pattern TP produce display data.Therefore in test mode of operation, control and drive system 400 can not need test pattern to write image data reservoir 426, does not also need from image data reservoir 426 read test pattern, and then improves the testing efficiency of control and drive system 400.
Although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention, any person of an ordinary skill in the technical field, when doing a little change and retouching, and does not depart from the spirit and scope of the present invention.
Claims (8)
1. a control and drive system for display panel, comprising:
One sequential control circuit, exports a control signal;
One data accumulating unit, in order to store an image data;
One data selection unit, be coupled to this data accumulating unit, this data selection unit is selected to export this image data of providing of this data accumulating unit as display data, or the instruction provided according to ppu or test pattern produce these display data and do not send a data line drive circuit to by this sequential control circuit and this data accumulating unit; And
This data line drive circuit, is coupled to this sequential control circuit and this data selection unit, and this data line drive circuit receives these display data from this data selection unit, and exports a corresponding gray scale voltage according to this control signal.
2. control and drive system according to claim 1, wherein when this control and drive system operates in a normal manipulation mode, this image data that this data accumulating unit exports directly reportedly is delivered to this data line drive circuit as this display by this data selection unit; When this control and drive system operates in a test mode of operation, this instruction that this data selection unit provides according to described ppu or test pattern produce these display data to this data line drive circuit.
3. control and drive system according to claim 2, when this control and drive system operates in this test mode of operation, this test pattern that described ppu exports by this data selection unit is supplied to this data line drive circuit as these display data.
4. control and drive system according to claim 2, when this control and drive system operates in this test mode of operation, this data selection unit produces corresponding described test pattern to this data line drive circuit as these display data according to this instruction that described ppu exports.
5. control and drive system according to claim 2, when this control and drive system operates in this test mode of operation, after this instruction is decoded by this data selection unit, optionally this test pattern is supplied to the part of this data line drive circuit or all passages as these display data according to decoded result.
6. control and drive system according to claim 1, wherein this data selection unit comprises:
Multiple logical block, the output terminal of logical block described in each is connected respectively to multiple output-stage circuits wherein one of this data line drive circuit,
Wherein said logical block selects this image data that this data accumulating unit provides to export to described output-stage circuit, or this instruction provided according to described ppu or test pattern produce these display data to described output-stage circuit.
7. control and drive system according to claim 1, also comprises:
One system interface circuit, is coupled to this data accumulating unit, this data selection unit and this sequential control circuit,
Wherein said ppu transmits this instruction or test pattern to this data selection unit via this system interface circuit.
8. control and drive system according to claim 1, wherein this data accumulating unit comprises:
One image data reservoir, it stores described image data; And
One reservoir control circuit, is coupled between this image data reservoir and this data selection unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161475255P | 2011-04-14 | 2011-04-14 | |
| US61/475,255 | 2011-04-14 |
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| Publication Number | Publication Date |
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| CN102737570A CN102737570A (en) | 2012-10-17 |
| CN102737570B true CN102737570B (en) | 2015-07-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110172948.1A Expired - Fee Related CN102737570B (en) | 2011-04-14 | 2011-06-24 | Control driver of display panel |
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| Country | Link |
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| CN (1) | CN102737570B (en) |
| TW (1) | TWI506607B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106228923B (en) * | 2016-08-02 | 2019-04-30 | 京东方科技集团股份有限公司 | A kind of driving circuit, driving method and display panel |
| US10777120B2 (en) | 2017-08-08 | 2020-09-15 | Novatek Microelectronics Corp. | Driving apparatus for a display panel and operation method thereof |
| TWI769843B (en) * | 2021-06-02 | 2022-07-01 | 友達光電股份有限公司 | Control circuit and display panel applying the same |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100671698B1 (en) * | 2004-08-05 | 2007-01-18 | 매그나칩 반도체 유한회사 | A Test Circuit for Digital-to-Analog Converter in LCD Driver IC |
| TWI236657B (en) * | 2004-09-01 | 2005-07-21 | Au Optronics Corp | Timing controller with external interface and apparatuses based thereon |
| JP2006153927A (en) * | 2004-11-25 | 2006-06-15 | Sanyo Electric Co Ltd | Display apparatus |
| KR101137856B1 (en) * | 2005-10-25 | 2012-04-20 | 엘지디스플레이 주식회사 | Flat Display Apparatus And Picture Quality Controling Method Thereof |
| KR100896178B1 (en) * | 2006-04-11 | 2009-05-12 | 삼성전자주식회사 | Driver circuit including test pattern generation circuit in liquid crystal display device |
| KR100866952B1 (en) * | 2006-05-09 | 2008-11-05 | 삼성전자주식회사 | Apparatus and method for driving display panel of hold type |
| KR20070118459A (en) * | 2006-06-12 | 2007-12-17 | 삼성전자주식회사 | Display device |
| JP2008083589A (en) * | 2006-09-28 | 2008-04-10 | Optrex Corp | Driving device of display device and display panel |
| KR20080070171A (en) * | 2007-01-25 | 2008-07-30 | 삼성전자주식회사 | Display device and driving method thereof |
-
2011
- 2011-06-01 TW TW100119242A patent/TWI506607B/en not_active IP Right Cessation
- 2011-06-24 CN CN201110172948.1A patent/CN102737570B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
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| TW201241808A (en) | 2012-10-16 |
| CN102737570A (en) | 2012-10-17 |
| TWI506607B (en) | 2015-11-01 |
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