CN102723333A - Non-volatile memory with P+ floating gate electrode and preparation method thereof - Google Patents
Non-volatile memory with P+ floating gate electrode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 140
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 230000004888 barrier function Effects 0.000 claims description 122
- 238000005530 etching Methods 0.000 claims description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 239000007772 electrode material Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 19
- 230000008569 process Effects 0.000 abstract description 15
- 238000002955 isolation Methods 0.000 abstract description 8
- 230000014759 maintenance of location Effects 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 abstract 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 34
- 238000005516 engineering process Methods 0.000 description 7
- 230000005611 electricity Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003834 intracellular effect Effects 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
The invention relates to a non-volatile memory with a P+ floating gate electrode and a preparation method of the non-volatile memory with the P+ floating gate electrode. A memory cell is arranged at the upper part in a semiconductor substrate and comprises a PMOS (P-Channel Metal Oxide Semiconductor) access transistor, a control capacitor and a programming capacitor; a plurality of isolation grooves are arranged at the upper part of the semiconductor substrate, and isolation mediums are arranged in the isolation grooves so as to form field medium regions; the PMOS access transistor, the control capacitor and the programming capacitor in the memory cell are isolated from each other by the field medium regions; a gate dielectric layer is deposited on a first main surface of the semiconductor substrate, and covers the openings of the isolation grooves and the first main surface of the semiconductor substrate; and P+ floating gate electrodes are arranged right above the vertex angles of the isolation grooves on the two sides of the PMOS access transistor and the control capacitor, are positioned on the gate dielectric layer and are corresponding to the vertex angles of the corresponding isolation grooves. According to the non-volatile memory and the preparation method, the non-volatile memory and a CMOS (Complementary Metal Oxide Semiconductor) process are compatible, so that the data retention period is prolonged, and the using reliability of the non-volatile memory is improved.
Description
Technical field
The present invention relates to a kind of non-volatility memory and preparation method thereof; Especially a kind of non-volatility memory and preparation method thereof with P+ floating gate electrode; Specifically a kind ofly can improve non-volatility memory of data retention time and preparation method thereof, belong to the technical field of integrated circuit.
Background technology
Use for SOC(system on a chip) (SoC), it is to be integrated into many functional blocks in the integrated circuit.The most frequently used SOC(system on a chip) comprises the logical block of a microprocessor or microcontroller, static RAM (SRAM) module, non-volatility memory and various specific functions.Yet, the process in traditional non-volatility memory, this uses folded grid or splitting bar memory cell usually, and is incompatible with traditional logic process.
Non-volatility memory (NVM) technology and traditional logic process are different.Non-volatility memory (NVM) technology and traditional logic process lump together, with making technology become a more complicated and expensive combination; Because the typical usage of nonvolatile memory that SoC uses is little at the chip size that is related to integral body, therefore this way is worthless.Simultaneously, because the operation principle of existing non-volatility memory makes that writing data loses easily, the reliability that influence is used.
Summary of the invention
The objective of the invention is to overcome the deficiency that exists in the prior art; Non-volatility memory of a kind of P+ of having floating gate electrode and preparation method thereof is provided; Its compact conformation can be compatible with the CMOS logic process, improves data retention time; Reduce use cost, improve the dependability of non-volatility memory.
According to technical scheme provided by the invention, said non-volatility memory with P+ floating gate electrode comprises semiconductor substrate, and the top in the said semiconductor substrate is provided with some memory body cells that are used to store; Said memory body cell comprises PMOS access transistor, control capacitance and programming electric capacity; Top in the said semiconductor substrate is provided with some isolated grooves, is provided with spacer medium in the said isolated groove to form the field areas of dielectric; The intracellular PMOS access transistor of memory body, control capacitance and programming electric capacity are isolated through the field areas of dielectric each other; Be deposited with gate dielectric layer on first interarea of semiconductor substrate, said gate dielectric layer covers the notch of isolated groove and covers first interarea of semiconductor substrate; Directly over the drift angle of PMOS access transistor, control capacitance both sides isolated groove the P+ floating gate electrode is set all, said P+ floating gate electrode is positioned on the gate dielectric layer, and corresponding with the drift angle of corresponding isolated groove.
Said P+ floating gate electrode is the conductive polycrystalline silicon of P conduction type.
Directly over the drift angle of said programming electric capacity both sides isolated groove the P+ floating gate electrode is set, said P+ floating gate electrode is corresponding with the drift angle of programming electric capacity both sides isolated groove.
The material of said semiconductor substrate comprises silicon, and semiconductor substrate is P conduction type substrate or N conduction type substrate; When said semiconductor substrate was P conduction type substrate, said PMOS access transistor, control capacitance and programming electric capacity were isolated with the P-type conduction type of substrate through the 3rd N type zone of zone of the 2nd N type in the P-type conduction type of substrate and top, the 2nd N type zone.
Said gate dielectric layer is provided with floating gate electrode; Said floating gate electrode covers and runs through the gate dielectric layer of PMOS access transistor, control capacitance and programming electric capacity top correspondence; The both sides of floating gate electrode are deposited with the lateral protection layer, and the lateral protection layer covers the sidewall of floating gate electrode; The PMOS access transistor comprises N type zone and is positioned at the P type source area and the P type drain region of said N type zone internal upper part that control capacitance comprises the second p type island region territory and is positioned at a P type doped region and the 2nd P type doped region of the said second p type island region territory internal upper part; Programming electric capacity comprises the 3rd p type island region territory and is positioned at the 5th P type doped region and the 6th P type doped region of said the 3rd p type island region territory internal upper part; The one P type doped region, the 2nd P type doped region, the 5th P type doped region, the 6th P type doped region, P type source area and P type drain region are corresponding with the floating gate electrode of top, and contact with corresponding gate dielectric layer and field areas of dielectric respectively.
The material of said gate dielectric layer comprises silicon dioxide; Said lateral protection layer is silicon nitride or silicon dioxide.
The material of said floating gate electrode comprises the conductive polycrystalline silicon of N conduction type.
A kind of non-volatility memory preparation method with P+ floating gate electrode, the preparation method of said non-volatility memory comprises the steps:
A, semiconductor substrate is provided, said semiconductor substrate comprises first interarea and second interarea;
B, on first interarea of semiconductor substrate, carry out required barrier layer deposition, barrier etch and the autoregistration ion injects; In semiconductor substrate, to form required N type zone, the 3rd N type zone, the second p type island region territory and the 3rd p type island region territory; The one N type zone is positioned between the second p type island region territory and the 3rd p type island region territory, and the 3rd N type zone is positioned at the outside in the second p type island region territory and the 3rd p type island region territory;
C, in above-mentioned semiconductor substrate, carry out etching groove; In semiconductor substrate, to form required isolated groove; And spacer medium is set in isolated groove; In semiconductor substrate, forming the field areas of dielectric, said field areas of dielectric from first interarea to extending below, and make the 3rd N type zone, the second p type island region territory, a N type is regional and top the 3rd p type island region territory isolates each other;
D, on the first corresponding interarea of above-mentioned semiconductor substrate the deposit gate dielectric layer, said gate dielectric layer covers first interarea of semiconductor substrate;
E, on first interarea of above-mentioned semiconductor substrate the deposit floating gate electrode, said floating gate electrode be covered on the gate dielectric layer and run through the second p type island region territory, N type zone and gate dielectric layer that top, the 3rd p type island region territory is corresponding on;
F, on above-mentioned gate dielectric layer deposit the 4th barrier layer, and optionally shelter and etching the 4th barrier layer, to remove N type zone, corresponding the 4th barrier layer that covers floating gate electrode in the second p type island region territory and top, the 3rd p type island region territory;
G, the p type impurity ion is injected in autoregistration above above-mentioned the 4th barrier layer; Top in the second p type island region territory obtains a P type lightly doped region and the 2nd P type lightly doped region; Top in a N type zone obtains the 3rd P type lightly doped region and the 4th P type lightly doped region, and the top in the 3rd p type island region territory obtains the 5th P type lightly doped region and the 6th P type lightly doped region;
H, remove above-mentioned the 4th barrier layer, and on first interarea deposit lateral protection material, form the lateral protection layer with both sides at floating gate electrode;
I, on above-mentioned first interarea deposit the 5th barrier layer, and optionally shelter and etching the 5th barrier layer, to remove the 5th barrier layer that the second p type island region territory, N type zone and the corresponding deposit in top, the 3rd p type island region territory cover;
J, the p type impurity ion is injected in autoregistration once more above above-mentioned the 5th barrier layer; Top in the second p type island region territory obtains a P type heavily doped region and the 2nd P type heavily doped region; Top in a N type zone obtains the 3rd P type heavily doped region and the 4th P type heavily doped region, and the top in the 3rd P type heavily doped region obtains the 5th P type heavily doped region and the 6th P type heavily doped region;
The 5th barrier layer on k, removal first interarea;
L, above first interarea of semiconductor substrate deposit P+ floating gate electrode material, and optionally shelter floating gate electrode material, directly over the drift angle of PMOS access transistor, control capacitance both sides isolated groove, all to form the P+ floating gate electrode with etching P+.
In said step a, when semiconductor substrate was P conduction type substrate, said step b comprised
B1, on first interarea of P conduction type substrate deposit first barrier layer, and optionally shelter and said first barrier layer of etching, N type foreign ion is injected in autoregistration above first barrier layer, in semiconductor substrate, to obtain the 2nd N type zone;
B2, remove first barrier layer on corresponding first interarea of above-mentioned P conduction type substrate, and on first interarea deposit second barrier layer;
B3, optionally shelter and etching second barrier layer; And N type foreign ion is injected in autoregistration above second barrier layer; In semiconductor substrate, to form N type zone and the 3rd N type zone, N type zone and the 3rd N type zone all are positioned at the top in the 2nd N type zone;
B4, remove second barrier layer on corresponding first interarea of above-mentioned P conduction type substrate, and on first interarea deposit the 3rd barrier layer;
B5, optionally shelter and etching the 3rd barrier layer; And the p type impurity ion is injected in autoregistration above the 3rd barrier layer; Above the 2nd N type zone, to form the second p type island region territory and the 3rd p type island region territory, pass through a N type zone isolation between the second p type island region territory and the 3rd p type island region territory.
In said step a, when semiconductor substrate was N conduction type substrate, said step b comprised
S1, on first interarea deposit second barrier layer, and optionally shelter and etching second barrier layer;
S2, N type foreign ion is injected in autoregistration above above-mentioned second barrier layer, obtains required N type zone and the 2nd N type zone with the top in N conduction type substrate;
S3, remove second barrier layer on first interarea, and on first interarea deposit the 3rd barrier layer;
S4, optionally shelter and etching the 3rd barrier layer, and the p type impurity ion is injected in autoregistration above the 3rd barrier layer, in N conduction type substrate, to obtain the second p type island region territory and the 3rd p type island region territory.
Advantage of the present invention: the top in the semiconductor substrate is provided with some isolated grooves; Be provided with spacer medium in the said isolated groove to form the field areas of dielectric, the intracellular PMOS access transistor of memory body, control capacitance and programming electric capacity are isolated through the field areas of dielectric each other; Be provided with the P+ floating gate electrode directly over the drift angle of isolated groove, said P+ floating gate electrode is positioned on the gate dielectric layer, and with the corresponding distribution of the drift angle of isolated groove; The width of P+ floating gate electrode can block the thin oxide layer in drift angle place fully, and the P+ floating gate electrode is the conductive polycrystalline silicon of P conduction type, and the electronics on the P+ floating gate electrode is few son; When the non-volatility memory store electrons, because the existence of P+ floating gate electrode, electronics is difficult to leak electricity through the oxide layer at drift angle place more like this; Thereby improved the time data memory of non-volatility memory, compact conformation can be compatible with the CMOS logic process; Reduce use cost, improve the dependability of non-volatility memory.
Description of drawings
Fig. 1 is the structural representation of the embodiment of the invention 1.
Fig. 2 is the structural representation of the embodiment of the invention 2.
Fig. 3 ~ Figure 14 is the practical implementation technology cutaway view of the embodiment of the invention 1, wherein:
Fig. 3 adopts the cutaway view of P conduction type substrate for the present invention.
Fig. 4 obtains the cutaway view behind the 2nd N type zone for the present invention.
Fig. 5 obtains the cutaway view behind N type zone and the 3rd N type zone for the present invention.
Fig. 6 obtains the cutaway view behind the second p type island region territory and the 3rd p type island region territory for the present invention.
Fig. 7 obtains the cutaway view after the areas of dielectric of field for the present invention.
Fig. 8 obtains the cutaway view behind the gate dielectric layer for the present invention.
Fig. 9 obtains the cutaway view behind the floating gate electrode for the present invention.
Figure 10 injects the cutaway view after the P foreign ion obtains lightly doped region for autoregistration of the present invention.
Figure 11 obtains the cutaway view behind the lateral protection layer for the present invention.
Figure 12 injects the cutaway view after the P foreign ion obtains heavily doped region for autoregistration of the present invention.
Figure 13 removes the cutaway view behind the 5th barrier layer for the present invention.
Figure 14 obtains the cutaway view behind the P+ floating gate electrode for the present invention.
Figure 15 ~ Figure 25 is the practical implementation technology cutaway view of the embodiment of the invention 2, wherein:
Figure 15 is the cutaway view of the N conduction type substrate of the present invention's employing.
Figure 16 obtains the cutaway view behind N type zone and the 2nd N type zone for the present invention.
Figure 17 obtains the cutaway view behind the second p type island region territory and the 3rd p type island region territory for the present invention.
Figure 18 obtains the cutaway view after the areas of dielectric of field for the present invention.
Figure 19 obtains the cutaway view behind the gate dielectric layer for the present invention.
Figure 20 obtains the cutaway view behind the floating gate electrode for the present invention.
Figure 21 injects the cutaway view after the P foreign ion obtains lightly doped region for autoregistration of the present invention.
Figure 22 obtains the cutaway view behind the lateral protection layer for the present invention.
Figure 23 injects the cutaway view after the P foreign ion obtains heavily doped region for autoregistration of the present invention.
Figure 24 removes the cutaway view behind the 5th barrier layer for the present invention.
Figure 25 obtains the cutaway view behind the P+ floating gate electrode for the present invention.
Description of reference numerals: 1-P conduction type substrate; 2-the one N type zone; 3-the 2nd N type zone; 4-the 3rd N type zone; The 5-second p type island region territory; 6-the one P type doped region; 7-the one P type heavily doped region; 8-the one P type lightly doped region; 9-the 2nd P type doped region; The 10-isolated groove; 11-the 2nd P type lightly doped region; 12-the 2nd P type heavily doped region; 13-P type source area; 14-field areas of dielectric; The 15-gate dielectric layer; The 16-floating gate electrode; 17-lateral protection layer; 18-the 3rd P type lightly doped region; 19-the 3rd P type heavily doped region; The 20-P+ floating gate electrode; 21-P type drain region; 22-the 4th P type lightly doped region; 23-the 4th P type heavily doped region; 24-the 5th P type doped region; 25-the 5th P type heavily doped region; 26-the 5th P type lightly doped region; 27-the 6th P type doped region; 28-the 6th P type lightly doped region; 29-the 6th P type heavily doped region; The 30-drift angle; 31-the 3rd p type island region territory; 32-first interarea; 33-second interarea; 34-first barrier layer; 35-second barrier layer; 36-the 3rd barrier layer; 37-the 4th barrier layer; 38-the 5th barrier layer; 39-N conduction type substrate; 100-memory body cell; The 110-PMOS access transistor; 120-control capacitance and 130-programming electric capacity.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the present invention is described further.
Usually; Non-volatility memory comprises semiconductor substrate; Top in the said semiconductor substrate is provided with some memory body cells 100 that are used to store; Said memory body cell 100 comprises PMOS access transistor 110, control capacitance 120 and programming electric capacity 130, and said PMOS access transistor 110, control capacitance 120 and programming electric capacity 130 isolate 14 through the field areas of dielectric on semiconductor substrate top.In the CMOS logic process, general earlier through etching groove when forming field areas of dielectric 14 in order to dwindle the size of non-volatility memory, the oxide layer of in groove, growing then.When etching formed groove, groove had drift angle 30, sees from the cross section of non-volatility memory, and drift angle 30 is positioned at the edge of groove notch, and drift angle 30 generally has certain gradient.When growth oxide layer in groove, because the existence of drift angle 30, the oxidated layer thickness at drift angle 30 places of groove is all thinner than the oxide layer of other positions of groove; When carrying out storage through non-volatility memory; Because the oxide layer that drift angle 30 places are thin; Making the interior electronic energy of non-volatility memory pass thin oxide layer leaks electricity; Promptly make the data retention time of non-volatility memory can not reach required requirement, reduce the reliability of non-volatility memory storage data.In order to improve the retention time of non-volatility memory storage data, the present invention will be described with embodiment 2 through embodiment 1 below.
Like Fig. 1 with shown in Figure 13: in order to make non-volatility memory and CMOS logic process compatible mutually; Simultaneously can make non-volatility memory can store the longer time; Non-volatility memory comprises P conduction type substrate 1, and the material of P conduction type substrate 1 is a silicon.Top in the P conduction type substrate 1 is provided with at least one memory body cell 100; Said memory body cell 100 comprises PMOS access transistor 110, control capacitance 120 and programming electric capacity 130; Deposit is coated with gate dielectric layer 15 on the surface of P conduction type substrate 1; Said gate dielectric layer 15 covers the corresponding surface that forms memory body cell 100, and PMOS access transistor 110, control capacitance 120 and 130 field areas of dielectric of passing through in the P conduction type substrate 1 14 of programming electric capacity are isolated each other.Field areas of dielectric 14 is positioned at the isolated groove 10 of P conduction type substrate 1; Said isolated groove 10 is positioned at the top of P conduction type substrate 1; From first interarea 32 of P conduction type substrate 1 to extending below; Obtain field areas of dielectric 14 through growth gate oxide in isolated groove 10, the material of said field areas of dielectric 14 is generally silicon dioxide.Can know that by above-mentioned analysis the oxidated layer thickness at drift angle 30 places of isolated groove 10 is thinner than the oxidated layer thickness of isolated groove 10 other positions.
In order to improve the data retention time of non-volatility memory among the present invention; Directly over the drift angle 30 of PMOS access transistor 110, control capacitance 120 both sides isolated grooves 10, P+ floating gate electrode 20 is set all; Said P+ floating gate electrode 20 is positioned on the gate dielectric layer 15; And the width of P+ floating gate electrode 20 and drift angle 30 corresponding distributions specifically are that the width of P+ floating gate electrode 20 can block the thin oxide layer in drift angle 30 places fully.P+ floating gate electrode 20 is the conductive polycrystalline silicon of P conduction type; Electronics on the P+ floating gate electrode 20 is few son; Like this when the non-volatility memory store electrons; Because the existence of P+ floating gate electrode 20, electronics are difficult to leak electricity through the oxide layer at drift angle 30 places again, thereby improved the time data memory of non-volatility memory.
In embodiments of the present invention; In order further to improve the time data memory of non-volatility memory; Directly over the drift angle 30 of programming electric capacity 130 both sides isolated grooves 10, P+ floating gate electrode 20 is set all; Said P+ floating gate electrode 20 is corresponding with the drift angle 30 of programming electric capacity 130 both sides isolated grooves 10, to cover corresponding drift angle 30.In the embodiment of the invention, see on the cross section of non-volatility memory of the present invention that the drift angle 30 of said PMOS access transistor 110, control capacitance 120 and programming electric capacity 130 both sides isolated grooves 10 is meant drift angle 30 zones of floating gate electrode 16 both sides.Simultaneously; On the cross section of non-volatility memory of the present invention; Directly over the drift angle 30 of memory body cell 100 outside isolated grooves 10, also P+ floating gate electrode 20 can be set; In embodiment of the invention accompanying drawing, the P+ floating gate electrode 20 in the outside of memory body cell 100 is meant the P+ floating gate electrode 20 of right ends; Through after above-mentioned the setting,, can further improve the data retention time of non-volatility memory directly over the drift angle 30 that is formed on each isolated groove 20 P+ floating gate electrode 20 to be set all.
Be deposited with floating gate electrode 16 on the gate dielectric layer 15; Said floating gate electrode 16 is covered on the gate dielectric layer 15; And run through the gate dielectric layer 15 that covers PMOS access transistor 110, control capacitance 120 and programming electric capacity 130 correspondences, thereby PMOS access transistor 110, control capacitance 120 and programming electric capacity 130 are interconnected cooperation.The both sides of floating gate electrode 16 are coated with lateral protection layer 17, and said lateral protection layer 17 covers the outer wall surface of floating gate electrode 16 correspondences.On the top plan view of the non-volatility memory of the embodiment of the invention, see that P+ floating gate electrode 20 contacts with floating gate electrode 16.
Said PMOS access transistor 110, control capacitance 120 and programming electric capacity 130 are isolated with the P conductivity type regions in the P conduction type substrate 1 through the 3rd N type zone 4 in the outside and the 2nd N type zone 3 of below, and the P conductive region in the P conduction type substrate 1 forms the first p type island region territory.The material of floating gate electrode 16 comprises conductive polycrystalline silicon, and gate dielectric layer 15 is a silicon dioxide, and lateral protection layer 17 is silicon dioxide or silicon nitride; Field areas of dielectric 14 is a silicon dioxide.
Said PMOS access transistor 110 comprises N type zone 2; Tops in the said N type zone 2 are provided with the P type source area 13 and the P type drain region 21 of symmetrical distribution, and said P type source area 13, P type drain region 21 contact with the corresponding field areas of dielectric 14 and the gate dielectric layer 15 of top.P type source area 13 comprises the 3rd P type lightly doped region 18 and the 3rd P type heavily doped region 19, and the doping content of said the 3rd P type heavily doped region 19 is greater than the doping content of the 3rd P type lightly doped region 18.P type drain region 21 comprises the 4th P type lightly doped region 22 and the 4th P type heavily doped region 23, and the doping content of said the 4th P type heavily doped region 23 is greater than the doping content of the 4th P type lightly doped region 22.The 3rd P type lightly doped region 18 and the 4th P type lightly doped region 22 are same manufacturing layer, and the 3rd P type heavily doped region 19 and the 4th P type heavily doped region 23 are same manufacturing layer.The 3rd P type lightly doped region 18 contacts with the 3rd P type heavily doped region 19; And contact with field areas of dielectric 14 through the 3rd P type heavily doped region 19, the width of the 3rd P type lightly doped region 18 extension in N type zone 2 and the thickness of lateral protection layer 17 are consistent; Simultaneously, the setting of the 4th P type lightly doped region 22 is identical with the distributed and arranged of the 3rd P type lightly doped region 18.
Control capacitance 120 comprises the second p type island region territory 5, and the top in the said second p type island region territory 5 is provided with a P type doped region 6 and the 2nd P type doped region 9; A said P type doped region 6 and the 2nd P type doped region 9 are symmetrically distributed in the second p type island region territory 5.The one P type doped region 6, the 2nd P type doped region 9 contact with corresponding field areas of dielectric 14 and gate dielectric layer 15.The one P type doped region 6 comprises a P type lightly doped region 8 and a P type heavily doped region 7; The one P type lightly doped region 8 contacts with field areas of dielectric 14 through a P type heavily doped region 7, and the thickness of extended distance and the lateral protection layer 17 of a P type lightly doped region 8 in the second p type island region territory 5 is consistent.The 2nd P type doped region 9 comprises the 2nd P type lightly doped region 11 and the 2nd P type heavily doped region 12; Said the 2nd P type lightly doped region 11 contacts with field areas of dielectric 14 through the 2nd P type heavily doped region 12, and the distributed and arranged of the 2nd a P type lightly doped region 11 and a P type lightly doped region 8 is consistent.5 in the second p type island region territory of floating gate electrode 16 and gate dielectric layer 15 and gate dielectric layer 15 belows forms capacitance structure, and promptly control capacitance 120.In like manner, 31 in the 3rd p type island region territory of floating gate electrode 16 and gate dielectric layer 15 and gate dielectric layer 15 belows also forms capacitance structure, the electric capacity 130 of promptly programming.
Programming electric capacity 130 comprises the 3rd p type island region territory 31, and the top in said the 3rd p type island region territory 31 is provided with the 5th P type doped region 24 and the 6th P type doped region 27, and said the 5th P type doped region 24 and the 6th P type doped region 27 are symmetrically distributed in the 3rd p type island region territory 31.The 5th P type doped region 24 comprises the 5th P type lightly doped region 26 and the 5th P type heavily doped region 25; The doping content of the 5th P type heavily doped region 25 is greater than the doping content of the 5th P type lightly doped region 26; The 5th P type lightly doped region 26 contacts with field areas of dielectric 14 through the 5th P type heavily doped region 25, and the thickness of extended distance and the lateral protection layer 17 of the 5th P type lightly doped region 26 in the 3rd p type island region territory 31 is consistent.The 6th P type doped region 27 comprises the 6th P type lightly doped region 28 and the 6th P type heavily doped region 29; The 6th P type lightly doped region 28 contacts with field areas of dielectric 14 through the 4th N type lightly doped region 29, and the distributed and arranged of the 6th P type lightly doped region 28 and the 5th P type lightly doped region 26 is consistent.The 5th P type lightly doped region 26 and the 6th P type lightly doped region 28 are same manufacturing layer, and the 5th P type heavily doped region 25 and the 6th P type heavily doped region 29 are same manufacturing layer.
Can be through programming electric capacity 130 to memory body cell 100 is write data, perhaps with the data erase in the memory body cell 100; Can read the storing data state in the memory body cell 100 through PMOS access transistor 110; Can magnitude of voltage be passed on the floating gate electrode 16 through control capacitance 120; Realize floating gate electrode 16 and 130 magnitudes of voltage of programming electric capacity, can realize that according to the correspondent voltage value data write, wipe and read operation.
Like Fig. 3 ~ shown in Figure 13: the non-volatility memory of said structure can realize through following processing step, particularly:
A, P conduction type substrate 1 is provided, said P conduction type substrate 1 comprises first interarea 32 and second interarea 33; As shown in Figure 3: said P conduction type substrate 1 is compatible consistent mutually with the requirement of conventional cmos prepared, and the material of P conduction type substrate 1 can be selected silicon commonly used for use, and first interarea 32 is corresponding with second interarea 33;
B, on first interarea 32 of P conduction type substrate 1, carry out required barrier layer deposition, barrier etch and the autoregistration ion injects; In P conduction type substrate 1, to form required the 2, the 3rd N type 4, second p type island region territory 5, zone, N type zone and the 3rd p type island region territory 31; The one N type zone 2 is positioned at 31 in the second p type island region territory 5 and the 3rd p type island region territory, and the 3rd N type zone 4 is positioned at the outside in the second p type island region territory 5 and the 3rd p type island region territory 31;
Like Fig. 4 ~ shown in Figure 6, forming process is particularly:
B1, on first interarea 32 of P conduction type substrate 1 deposit first barrier layer 34; And optionally shelter and said first barrier layer 34 of etching; N type foreign ion is injected in autoregistration above first barrier layer 34, in P conduction type substrate 1, to obtain the 2nd N type zone 3; As shown in Figure 4, said first barrier layer 34 is silicon dioxide or silicon nitride; Behind deposit first barrier layer 34 on first interarea 32,, after N type foreign ion is injected in autoregistration, can in P conduction type substrate 1, obtain the 2nd N type zone 3 through first barrier layer 34 of etching central area; Said N type foreign ion is a foreign ion commonly used in the semiconductor technology, and dosage and energy through control N type foreign ion injects can form required the 2nd N type zone 3;
B2, remove first barrier layer 34 on above-mentioned P conduction type substrate 1 corresponding first interarea 32, and on first interarea 32 deposit second barrier layer 35;
B3, optionally shelter and etching second barrier layer 35; And N type foreign ion is injected in autoregistration above second barrier layer 35; In semiconductor substrate 1, to form the top that the 2 and the 3rd N type zone, 4, the one N types zone, the 2 and the 3rd N type zone, N type zone 4 all is positioned at the 2nd N type zone 3; As shown in Figure 5: optionally shelter with etching second barrier layer 35 after; Needs are formed the second corresponding barrier layer 35 of 4 tops, the 2 and the 3rd N type zone, N type zone to etch away; After injecting N type foreign ion; Can form the outside in the 4 and the one N type zone, 4, the three N types zone, the 2 and the 3rd N type zone, N type zone 2;
B4, remove second barrier layer 35 on above-mentioned P conduction type substrate 1 corresponding first interarea 32, and on first interarea 32 deposit the 3rd barrier layer 36;
B5, optionally shelter and etching the 3rd barrier layer 36; And the p type impurity ion is injected in autoregistration above the 3rd barrier layer 36; Pass through 2 isolation of N type zone above the 2nd N type zone 3, to form the second p type island region territory 5 and 31, the second p type island region territories 5, the 3rd p type island region territory and 31 in the 3rd p type island region territory;
As shown in Figure 6: as during etching the 3rd barrier layer 36, the 3rd corresponding barrier layer 36 of the second p type island region territory 5 and 31 tops, the 3rd p type island region territory to be removed, after the p type impurity ion is injected in autoregistration, can form the second p type island region territory 5 and the 3rd p type island region territory 31;
C, in above-mentioned semiconductor substrate, carry out etching groove; In semiconductor substrate, to form required isolated groove 10; And in isolated groove 10, spacer medium is set; In semiconductor substrate, forming field areas of dielectric 14, said field areas of dielectric 14 to extending below, and makes the top in 4, the second p type island region territory 5, the 3rd N type zone, the 2 and the 3rd p type island region territory 31, N type zone isolate each other from first interarea 32;
As shown in Figure 7: field areas of dielectric 14 is a silicon dioxide, can obtain in the growth of isolated groove 10 internal heating oxidations through routine;
D, on the first corresponding interarea 32 of above-mentioned P conduction type substrate 1 deposit gate dielectric layer 15, said gate dielectric layer 15 covers first interarea 32 of semiconductor substrates 1; As shown in Figure 8: said gate dielectric layer 15 is a silicon dioxide, and gate dielectric layer 15 is covered in the surface of field areas of dielectric 14 and semiconductor substrate 1 correspondence;
E, on first interarea 32 of above-mentioned P conduction type substrate 1 deposit floating gate electrode 16, said floating gate electrode 16 is covered on the gate dielectric layer 15 and runs through on the corresponding gate dielectric layer 15 in the second p type island region territory 5,31 tops, the 2 and the 3rd p type island region territory, N type zone; As shown in Figure 9: the second p type island region territory 5, the corresponding floating gate electrode 16 in 31 tops, the 2 and the 3rd p type island region territory, N type zone be same manufacturing layer among the figure, and interconnect and be integral; In order to show structure of the present invention, adopting at interval, the method for analysing and observe obtains cutaway view of the present invention here; Floating gate electrode 16 is the T font on gate dielectric layer 15;
F, on above-mentioned gate dielectric layer 15 deposit the 4th barrier layer 37, and optionally shelter and etching the 4th barrier layer 37, remove corresponding the 4th barrier layer 37 that covers floating gate electrode 16 in a N type 2, second p type island region territory 5, zone and 31 tops, the 3rd p type island region territory;
G, the p type impurity ion is injected in autoregistration above above-mentioned the 4th barrier layer 37; Top in the second p type island region territory 5 obtains a P type lightly doped region 8 and the 2nd P type lightly doped region 11; Top in N type zone 2 obtains the 3rd P type lightly doped region 18 and the 4th P type lightly doped region 22, and the top in the 3rd p type island region territory 31 obtains the 5th P type lightly doped region 26 and the 6th P type lightly doped region 28; Shown in figure 10: the 4th barrier layer 37 is silicon dioxide or silicon nitride; When optionally shelter with etching the 4th barrier layer 37 after, make all to stop in the p type impurity ion injection P-type conduction type of substrate 1 except that the second p type island region territory 5, corresponding zone, the 2 and the 3rd p type island region territory 31, N type zone; Adopt conventional autoregistration to inject the p type impurity ion, can obtain required P type lightly doped region simultaneously;
H, remove above-mentioned the 4th barrier layer 37, and on first interarea 32 deposit lateral protection material, form lateral protection layer 17 with both sides at floating gate electrode 16; Shown in figure 11: the material of said lateral protection layer 17 is silica or silicon dioxide, can form required heavily doped region through lateral protection layer 17, can make that corresponding lightly doped region and lateral protection layer 17 are corresponding to the same simultaneously;
I, on above-mentioned first interarea 32 deposit the 5th barrier layer 38, and optionally shelter and etching the 5th barrier layer 38, to remove the 5th barrier layer 38 that the second p type island region territory 5, the corresponding deposit in 31 tops, the 2 and the 3rd p type island region territory, N type zone cover; Deposit is also optionally sheltered and etching the 5th barrier layer 38, mainly is to avoid when forming heavily doped region, avoids ion to inject in P-type conduction type of substrate 1 interior other zones; The 5th barrier layer 38 is silicon dioxide or silicon nitride;
J, the p type impurity ion is injected in autoregistration once more above above-mentioned the 5th barrier layer 38; Top in the second p type island region territory 5 obtains a P type heavily doped region 7 and the 2nd P type heavily doped region 12; Top in N type zone 2 obtains the 3rd P type heavily doped region 19 and the 4th P type heavily doped region 23, and the top in the 3rd P type heavily doped region 31 obtains the 5th P type heavily doped region 25 and the 6th P type heavily doped region 29; Shown in figure 12: the ion concentration of the concentration of p type impurity ion greater than step g injected in said autoregistration; Because stopping of the 5th barrier layer 38 and lateral protection layer 17 arranged; Can make and form heavily doped region in the position of corresponding formation lightly doped region; And the lightly doped region that keeps can be consistent with lateral protection layer 17, thereby obtain required single polycrystalline framework;
The 5th barrier layer 38 on k, removal first interarea 32.Shown in figure 13: as to remove the 5th barrier layer 38, obtain required non-volatility memory.
L, on above-mentioned gate dielectric layer 15 deposit P+ floating gate electrode material; And optionally shelter floating gate electrode material with etching P+, shown in figure 14 directly over the drift angle 30 of PMOS access transistor 110, control capacitance 120 both sides isolated grooves 10, all to form P+ floating gate electrode 20.
Like Fig. 2 and shown in Figure 25: semiconductor substrate is a N conduction type substrate 39 in the present embodiment; After adopting N conduction type substrate 39; In N conduction type substrate 39, need not form the 2nd N type zone 3; Promptly the second p type island region territory 5 and the 3rd p type island region territory 31 directly contact with N type conduction type substrate 39, and simultaneously, N type zone 2 also directly contacts with N conduction type substrate 39 with the 3rd N type zone 4.All the other structures behind the employing N conduction type substrate 39 are all identical with being provided with of embodiment 1.
Like Figure 15 ~ shown in Figure 25: the non-volatility memory of said structure can realize through following processing step, particularly:
A, N conduction type substrate 39 is provided, said N conduction type substrate 39 comprises first interarea 32 and second interarea 33; Shown in figure 15, the material of N conduction type substrate 39 can be silicon;
B, on first interarea 32 of semiconductor substrate, carry out required barrier layer deposition, barrier etch and the autoregistration ion injects; In semiconductor substrate, to form required the 2, the 3rd N type 4, second p type island region territory 5, zone, N type zone and the 3rd p type island region territory 31; The one N type zone 2 is positioned at 31 in the second p type island region territory 5 and the 3rd p type island region territory, and the 3rd N type zone 4 is positioned at the outside in the second p type island region territory 5 and the 3rd p type island region territory 31;
The forming process of step b can be divided into:
S1, on first interarea 32 deposit second barrier layer 35, and optionally shelter and etching second barrier layer 35;
S2, N type foreign ion is injected in autoregistration above above-mentioned second barrier layer 35, and it is regional 4, shown in figure 16 to obtain required N type zone the 2 and the 2nd N type with the top N conduction type substrate 39 in;
S3, remove second barrier layer 35 on first interarea 32, and on first interarea 32 deposit the 3rd barrier layer 36;
S4, optionally shelter and etching the 3rd barrier layer 36, and the p type impurity ion is injected in autoregistration above the 3rd barrier layer 36, in N conduction type substrate 39, to obtain the second p type island region territory 5 and the 3rd p type island region territory 31, shown in figure 17;
C, in above-mentioned semiconductor substrate, carry out etching groove; In semiconductor substrate, to form required isolated groove 10; And in isolated groove 10, spacer medium is set; In semiconductor substrate, forming field areas of dielectric 14, said field areas of dielectric 14 to extending below, and makes the top in 4, the second p type island region territory 5, the 3rd N type zone, the 2 and the 3rd p type island region territory 31, N type zone isolate each other from first interarea 32; Shown in figure 18;
D, on the first corresponding interarea 32 of above-mentioned semiconductor substrate deposit gate dielectric layer 15, said gate dielectric layer 15 covers first interarea 32 of semiconductor substrates 1, and is shown in figure 19;
E, on first interarea 32 of above-mentioned semiconductor substrate deposit floating gate electrode 16; Said floating gate electrode 16 is covered on the gate dielectric layer 15 and runs through on the corresponding gate dielectric layer 15 in the second p type island region territory 5,31 tops, the 2 and the 3rd p type island region territory, N type zone, and is shown in figure 20;
F, on above-mentioned gate dielectric layer 15 deposit the 4th barrier layer 37, and optionally shelter and etching the 4th barrier layer 37, remove corresponding the 4th barrier layer 37 that covers floating gate electrode 16 in a N type 2, the second p type island region territories 5, zone and 31 tops, the 3rd p type island region territory;
G, the p type impurity ion is injected in autoregistration above above-mentioned the 4th barrier layer 37; Top in the second p type island region territory 5 obtains a P type lightly doped region 8 and the 2nd P type lightly doped region 11; Top in N type zone 2 obtains the 3rd P type lightly doped region 18 and the 4th P type lightly doped region 22; And the top in the 3rd p type island region territory 31 obtains the 5th P type lightly doped region 26 and the 6th P type lightly doped region 28, and is shown in figure 21;
H, remove above-mentioned the 4th barrier layer 37, and on first interarea 32 deposit lateral protection material, form lateral protection layer 17 with both sides at floating gate electrode 16, shown in figure 22;
I, on above-mentioned first interarea 32 deposit the 5th barrier layer 38, and optionally shelter and etching the 5th barrier layer 38, to remove the 5th barrier layer 38 that the second p type island region territory 5, the corresponding deposit in 31 tops, the 2 and the 3rd p type island region territory, N type zone cover;
J, the p type impurity ion is injected in autoregistration once more above above-mentioned the 5th barrier layer 38; Top in the second p type island region territory 5 obtains a P type heavily doped region 7 and the 2nd P type heavily doped region 12; Top in N type zone 2 obtains the 3rd P type heavily doped region 19 and the 4th P type heavily doped region 23; And the top in the 3rd P type heavily doped region 31 obtains the 5th P type heavily doped region 25 and the 6th P type heavily doped region 29, and is shown in figure 23;
The 5th barrier layer 38 on k, removal first interarea 32, shown in figure 24.
L, on above-mentioned gate dielectric layer 15 deposit P+ floating gate electrode material; And optionally shelter floating gate electrode material with etching P+; Directly over the drift angle 30 of PMOS access transistor 110, control capacitance 120 both sides isolated grooves 10, all to form P+ floating gate electrode 20, shown in figure 25.
In the foregoing description; The embodiment of the invention all comprises the structure of PMOS access transistor 110, control capacitance 120 and programming electric capacity 130 with memory body cell 100; PMOS access transistor 110, control capacitance 110 and programming electric capacity 120 are all isolated through field areas of dielectric 14 each other; The present technique field personnel can know; When in the process of preparation memory body cell 100, in isolated groove 10, during the areas of dielectric 14 of formation field, all can P+ floating gate electrode 20 be set at the drift angle 30 of isolated groove 10; The structure of the memory body cell of promptly describing except that the present invention 100, the method that the memory body cell 100 of all the other structures also can utilize the present invention that P+ floating gate electrode 20 is set improves data retention time.Memory body cell 100 structures of all the other structures are known by present technique field personnel, and the structure that memory body cell 100 structures of all the other structures utilize the present invention that 20 formation of P+ floating gate electrode are set is enumerated description here no longer one by one.
Simultaneously, during the foregoing description non-volatility memory, all comprise that with memory body cell 100 structure of PMOS access transistor 110, control capacitance 120 and programming electric capacity 130 describes complete preparation process.When the memory body cell 100 of non-volatility memory adopts other structures; Adopt with the compatible implementation step of CMOS logic process and all can; As long as on semiconductor substrate, form isolated groove 10 in the preparation memory body cell processes; And the growth spacer medium forms field areas of dielectric 14 in isolated groove 10, and the transistor AND gate electric capacity of isolating in the memory body cell 100 through field areas of dielectric 14 gets final product, and the memory body cell 100 preparation processes of all the other structures no longer detail here.
Like Fig. 1 and shown in Figure 14: for single memory body cell 100, it can realize writing, read and wiping of single binary data.Below through single memory body cell 100 being write, reads and erase process being explained the working mechanism of nonvolatile memory of the present invention.When needs write input according to the time; P type island region territory voltage in the P conduction type substrate 1 is put 0 current potential all the time; The 3 and the 3rd N type zone, the 2, the 2nd N type zone, the one N type zone 4 equal set 5 current potentials, the second p type island region territory 5 is set 0 current potential also, and the voltage in the 3rd p type island region territory 31 is-5V; The 5th P type doped region 24 of programming electric capacity 130 and the equal set-5V of voltage of the 6th P type doped region 27, a P type doped region 6 of control capacitance 120 and the 2nd P type doped region 9 equal set 5V; Because the transfer function of control capacitance 120; Can the magnitude of voltage of 5V be delivered on the floating gate electrode 16; Produce the magnitude of voltage of 4 ~ 5V on the floating gate electrode 16, this moment, the magnitude of voltage in 31 in floating gate electrode 16 and the 3rd p type island region territory was 9 ~ 10V, will reach field emission characteristic and be also referred to as the required electric field of FN (Fowler-Nordheim) tunnel effect; Electronics will arrive in the floating gate electrode 16 through gate dielectric layer 15, realizes writing of data.Because floating gate electrode 16 belows are isolated through gate dielectric layer 15, the side completely cuts off through lateral protection layer 17, so electronic energy can keep in floating gate electrode 16 for a long time.
During data in needs are wiped memory body cell 100; P type island region territory voltage in the P conduction type substrate 1 is put 0 current potential all the time; The equal set 5V of the voltage voltage in the 3 and the 3rd N type zone, the 2, the 2nd N type zone, the one N type zone 4, the voltage set-5V in the second p type island region territory 5, the equal set-5V of voltage of a P type doped region 6, the 2nd P type doped region 9; The voltage set 5V in the 3rd p type island region territory 31; The 5th P type doped region 24 and the 6th P type doped region 27 equal set 5V voltages, in control capacitance 120 effect down, can make floating gate electrode 16 interior generation-4V ~-voltage of 5V; This moment the magnitude of voltage in 31 in floating gate electrode 16 and the 3rd p type island region territory be-9 ~-10V; Will reach field emission characteristic and be also referred to as the required electric field of FN (Fowler-Nordheim) tunnel effect, electronics can get in the 3rd p type island region territory 31 through gate dielectric layer 15, thereby realizes data erase in the floating gate electrode 16.
During data in needs read memory body cell 100; P type island region territory voltage in the P conduction type substrate 1 is put 0 current potential all the time; The equal set 5V of the voltage voltage in the 3 and the 3rd N type zone, the 2, the 2nd N type zone, the one N type zone 4; Second p type island region territory 5 set-1V, a P type doped region 6 and the 2nd P type doped region 9 equal set-1V, PMOS access transistor source area 13 and PMOS access transistor drain region 21 equal set 0.5V; The 3rd p type island region territory 31 set 5V voltages, the 5th P type doped region 24 and the 6th P type doped region 27 equal set 5V voltages.After loading above-mentioned magnitude of voltage, when writing data in the memory body cell 100, a large amount of electronics are arranged in the floating gate electrode 16, when data were wiped free of in the memory body cell 100, electronics flowed out in floating gate electrode 16; When in the floating gate electrode 16 electronics being arranged; Electric current through PMOS access transistor source area 13 is bigger; When electronics flows out in floating gate electrode 16; Electric current through PMOS access transistor source area 13 is less, thereby according to the size of corresponding electric current, can know that memory body cell 100 writes data mode or is in the data erase state.
Since in a P type doped region 6, the 2nd P type doped region 9, P type source area 13, P type drain region 21, the 5th P type doped region 24 and the 6th P type doped region 27 in the corresponding P+ zone transportable anion (electronics) be few son; More of a specified duration when what manage the data that suck like this, more safe and reliable when storage is used.
Simultaneously; Directly over the drift angle 30 of isolated groove 10, P+ floating gate electrode 20 is set, P+ floating gate electrode 20 is the conductive polycrystalline silicon of P conduction type, and the electronics on the P+ floating gate electrode 20 is few son; Like this when the non-volatility memory store electrons; Because the existence of P+ floating gate electrode 20, electronics are difficult to leak electricity through the oxide layer at drift angle 30 places again, thereby further improved the time data memory of non-volatility memory.
Like Fig. 2 and shown in Figure 23: adopt the non-volatility memory of the N conduction type substrate 39 corresponding single polycrystalline frameworks that form, need carry out write, wipe and read the time, need corresponding on-load voltage, write accordingly, wipe and read operation realizing.Particularly, voltage was consistent when the voltage loading that writes accordingly, wipes and read was operated with the non-volatility memory of the single polycrystalline framework that adopts the 1 corresponding formation of P conduction type substrate, no longer was described in detail here.
Top in the semiconductor substrate of the present invention is provided with some isolated grooves 10; Be provided with spacer medium in the said isolated groove 10 to form field areas of dielectric 14, the PMOS access transistor 110 in the memory body cell 100, control capacitance 120 and programming electric capacity 130 are isolated through field areas of dielectric 14 each other; Be provided with P+ floating gate electrode 20 directly over the drift angle 30 of isolated groove 10; Said P+ floating gate electrode 20 is positioned on the gate dielectric layer 15, and with the drift angle 30 corresponding distributions of isolated groove 10, the width of P+ floating gate electrode 20 can block the thin oxide layer in drift angle 30 places fully; P+ floating gate electrode 20 is the conductive polycrystalline silicon of P conduction type; Electronics on the P+ floating gate electrode 20 is few son, like this when the non-volatility memory store electrons, because the existence of P+ floating gate electrode 20; Electronics is difficult to leak electricity through the oxide layer at drift angle 30 places again, thereby has improved the time data memory of non-volatility memory.
Claims (10)
1. the non-volatility memory with P+ floating gate electrode comprises semiconductor substrate, and the top in the said semiconductor substrate is provided with some memory body cells (100) that are used to store; Said memory body cell (100) comprises PMOS access transistor (110), control capacitance (120) and programming electric capacity (130); It is characterized in that: the top in the said semiconductor substrate is provided with some isolated grooves (10), is provided with spacer medium in the said isolated groove (10) to form field areas of dielectric (14); PMOS access transistor (110) in the memory body cell (100), control capacitance (120) and programming electric capacity (130) are isolated through field areas of dielectric (14) each other; Be deposited with gate dielectric layer (15) on first interarea (32) of semiconductor substrate, said gate dielectric layer (15) covers the notch of isolated groove (10) and covers first interarea (32) of semiconductor substrate; Directly over the drift angle (30) of PMOS access transistor (110), control capacitance (120) both sides isolated grooves (10) P+ floating gate electrode (20) is set all; Said P+ floating gate electrode (20) is positioned on the gate dielectric layer (15), and corresponding with the drift angle (30) of corresponding isolated groove (10).
2. according to the said a kind of non-volatility memory with P+ floating gate electrode of claim 1, it is characterized in that: said P+ floating gate electrode (20) is the conductive polycrystalline silicon of P conduction type.
3. according to the said a kind of non-volatility memory of claim 1 with P+ floating gate electrode; It is characterized in that: directly over the drift angle (30) of said programming electric capacity (130) both sides isolated grooves (10) P+ floating gate electrode (20) is set, said P+ floating gate electrode (20) is corresponding with the drift angle (30) of programming electric capacity (130) both sides isolated grooves (10).
4. according to the said a kind of non-volatility memory with P+ floating gate electrode of claim 1, it is characterized in that: the material of said semiconductor substrate comprises silicon, and semiconductor substrate is P conduction type substrate (1) or N conduction type substrate (39); When said semiconductor substrate was P conduction type substrate (1), said PMOS access transistor (110), control capacitance (120) and programming electric capacity (130) were isolated with P-type conduction type of substrate (1) through the 3rd N type zone (4) of zone of the 2nd N type in the P-type conduction type of substrate (1) (3) and top, the 2nd N type zone (3).
5. according to the said a kind of non-volatility memory of claim 4 with P+ floating gate electrode; It is characterized in that: said gate dielectric layer (15) is provided with floating gate electrode (16); Said floating gate electrode (16) covers and runs through the gate dielectric layer (15) of PMOS access transistor (110), control capacitance (120) and programming electric capacity (130) top correspondence; The both sides of floating gate electrode (16) are deposited with lateral protection layer (17), and lateral protection layer (17) covers the sidewall of floating gate electrode (16); PMOS access transistor (110) comprises N type zone (2) and is positioned at the P type source area (13) and P type drain region (21) of said N type zone (2) internal upper part that control capacitance (120) comprises the second p type island region territory (5) and is positioned at a P type doped region (6) and the 2nd P type doped region (9) of said second p type island region territory (5) internal upper part; Programming electric capacity (130) comprises the 3rd p type island region territory (31) and is positioned at the 5th P type doped region (24) and the 6th P type doped region (27) of said the 3rd p type island region territory (31) internal upper part; The one P type doped region (6), the 2nd P type doped region (9), the 5th P type doped region (24), the 6th P type doped region (27), P type source area (13) and P type drain region (21) are corresponding with the floating gate electrode (16) of top, and contact with corresponding gate dielectric layer (15) and field areas of dielectric (14) respectively.
6. according to the said a kind of non-volatility memory with P+ floating gate electrode of claim 5, it is characterized in that: the material of said gate dielectric layer (15) comprises silicon dioxide; Said lateral protection layer (17) is silicon nitride or silicon dioxide.
7. according to the said a kind of non-volatility memory with P+ floating gate electrode of claim 5, it is characterized in that: the material of said floating gate electrode (16) comprises the conductive polycrystalline silicon of N conduction type.
8. the non-volatility memory preparation method with P+ floating gate electrode is characterized in that the preparation method of said non-volatility memory comprises the steps:
(a), provide semiconductor substrate, said semiconductor substrate to comprise first interarea (32) and second interarea (33);
(b), on first interarea (32) of semiconductor substrate, carrying out required barrier layer deposition, barrier etch and autoregistration ion injects; In semiconductor substrate, to form required N type zone (2), the 3rd N type zone (4), the second p type island region territory (5) and the 3rd p type island region territory (31); The one N type zone (2) is positioned between the second p type island region territory (5) and the 3rd p type island region territory (31), and the 3rd N type zone (4) is positioned at the outside in the second p type island region territory (5) and the 3rd p type island region territory (31);
(c), in above-mentioned semiconductor substrate, carry out etching groove; In semiconductor substrate, to form required isolated groove (10); And in isolated groove (10), spacer medium is set; In semiconductor substrate, forming field areas of dielectric (14), said field areas of dielectric (14) to extending below, and makes the top in the 3rd N type zone (4), the second p type island region territory (5), N type zone (2) and the 3rd p type island region territory (31) isolate each other from first interarea (32);
(d), go up deposit gate dielectric layer (15), first interarea (32) of said gate dielectric layer (15) covering semiconductor substrate (1) at corresponding first interarea (32) of above-mentioned semiconductor substrate;
(e), upward deposit floating gate electrode (16), said floating gate electrode (16) is covered in gate dielectric layer (15) and goes up and run through on the corresponding gate dielectric layer (15) in the second p type island region territory (5), N type zone (2) and top, the 3rd p type island region territory (31) at first interarea (32) of above-mentioned semiconductor substrate;
(f), go up deposit the 4th barrier layer (37) at above-mentioned gate dielectric layer (15); And optionally shelter and etching the 4th barrier layer (37), to remove N type zone (2), corresponding the 4th barrier layer (37) that covers floating gate electrode (16) in the second p type island region territory (5) and top, the 3rd p type island region territory (31);
(g), the p type impurity ion is injected in the top autoregistration on above-mentioned the 4th barrier layer (37); Top in the second p type island region territory (5) obtains a P type lightly doped region (8) and the 2nd P type lightly doped region (11); Top in N type zone (2) obtains the 3rd P type lightly doped region (18) and the 4th P type lightly doped region (22), and the top in the 3rd p type island region territory (31) obtains the 5th P type lightly doped region (26) and the 6th P type lightly doped region (28);
(h), remove above-mentioned the 4th barrier layer (37), and go up deposit lateral protection material at first interarea (32), form lateral protection layer (17) with both sides at floating gate electrode (16);
(i), go up deposit the 5th barrier layer (38) at above-mentioned first interarea (32); And optionally shelter and etching the 5th barrier layer (38), to remove the 5th barrier layer (38) that the second p type island region territory (5), N type zone (2) and the corresponding deposit in top, the 3rd p type island region territory (31) cover;
(j), in above-mentioned the 5th barrier layer (38) top once more autoregistration inject the p type impurity ion; Top in the second p type island region territory (5) obtains a P type heavily doped region (7) and the 2nd P type heavily doped region (12); Top in N type zone (2) obtains the 3rd P type heavily doped region (19) and the 4th P type heavily doped region (23), and the top in the 3rd P type heavily doped region (31) obtains the 5th P type heavily doped region (25) and the 6th P type heavily doped region (29);
(k), the 5th barrier layer (38) on removal first interarea (32);
(l), deposit P+ floating gate electrode material above first interarea of semiconductor substrate; And optionally shelter floating gate electrode material with etching P+, directly over the drift angle (30) of PMOS access transistor (110), control capacitance (120) both sides isolated grooves (10), all to form P+ floating gate electrode (20).
9. said according to Claim 8 a kind of non-volatility memory preparation method with P+ floating gate electrode is characterized in that: in said step (a), when semiconductor substrate was P conduction type substrate (1), said step (b) comprised
(b1), go up deposit first barrier layer (34) at first interarea (32) of P conduction type substrate (1); And optionally shelter and said first barrier layer of etching (34); Inject N type foreign ion in first barrier layer (34) top autoregistration, in semiconductor substrate (1), to obtain the 2nd N type zone (3);
(b2), remove first barrier layer (34) on above-mentioned P conduction type substrate (1) corresponding first interarea (32), and go up deposit second barrier layer (35) at first interarea (32);
(b3), optionally shelter and etching second barrier layer (35); And N type foreign ion is injected in autoregistration above second barrier layer (35); In semiconductor substrate (1), to form N type zone (2) and the 3rd N type zone (4), N type zone (2) and the 3rd N type zone (4) all are positioned at the top in the 2nd N type zone (3);
(b4), remove second barrier layer (35) on above-mentioned P conduction type substrate (1) corresponding first interarea (32), and go up deposit the 3rd barrier layer (36) at first interarea (32);
(b5), optionally shelter and etching the 3rd barrier layer (36); And the p type impurity ion is injected in autoregistration above the 3rd barrier layer (36); To form the second p type island region territory (5) and the 3rd p type island region territory (31), isolate through N type zone (2) between the second p type island region territory (5) and the 3rd p type island region territory (31) in top, the 2nd N type zone (3).
10. said according to Claim 8 a kind of non-volatility memory preparation method with P+ floating gate electrode is characterized in that: in said step (a), when semiconductor substrate was N conduction type substrate (39), said step (b) comprised
(s1), upward deposit second barrier layer (35), and optionally shelter and etching second barrier layer (35) at first interarea (32);
(s2), N type foreign ion is injected in autoregistration in the top on above-mentioned second barrier layer (35), obtains required N type zone (2) and the 2nd N type zone (4) with the top in N conduction type substrate (39);
(s3), remove second barrier layer (35) on first interarea (32), and go up deposit the 3rd barrier layer (36) at first interarea (32);
(s4), optionally shelter and etching the 3rd barrier layer (36), and inject the p type impurity ion, in N conduction type substrate (39), to obtain the second p type island region territory (5) and the 3rd p type island region territory (31) in the 3rd barrier layer (36) top autoregistration.
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| US20050219912A1 (en) * | 2002-04-15 | 2005-10-06 | Philippe Gendrier | Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane |
| CN1909211A (en) * | 2005-08-04 | 2007-02-07 | 三星电子株式会社 | Nonvolatile memory devices and methods of fabricating the same |
| CN101136375A (en) * | 2006-08-31 | 2008-03-05 | 富士通株式会社 | Semiconductor device and method of manufacturing the same |
| CN102544074A (en) * | 2012-02-21 | 2012-07-04 | 无锡来燕微电子有限公司 | Non-volatile memory compatible with complementary metal oxide semiconductor (CMOS) logical process and preparation method for non-volatile memory |
| CN202712188U (en) * | 2012-07-11 | 2013-01-30 | 无锡来燕微电子有限公司 | Nonvolatile memory body with P+ floating-gate electrodes |
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| US20050219912A1 (en) * | 2002-04-15 | 2005-10-06 | Philippe Gendrier | Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane |
| CN1909211A (en) * | 2005-08-04 | 2007-02-07 | 三星电子株式会社 | Nonvolatile memory devices and methods of fabricating the same |
| CN101136375A (en) * | 2006-08-31 | 2008-03-05 | 富士通株式会社 | Semiconductor device and method of manufacturing the same |
| CN102544074A (en) * | 2012-02-21 | 2012-07-04 | 无锡来燕微电子有限公司 | Non-volatile memory compatible with complementary metal oxide semiconductor (CMOS) logical process and preparation method for non-volatile memory |
| CN202712188U (en) * | 2012-07-11 | 2013-01-30 | 无锡来燕微电子有限公司 | Nonvolatile memory body with P+ floating-gate electrodes |
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