CN102723328B - Mask, static random access memory (sram) cell and memory - Google Patents
Mask, static random access memory (sram) cell and memory Download PDFInfo
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- CN102723328B CN102723328B CN201210214369.3A CN201210214369A CN102723328B CN 102723328 B CN102723328 B CN 102723328B CN 201210214369 A CN201210214369 A CN 201210214369A CN 102723328 B CN102723328 B CN 102723328B
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Abstract
A kind of have the mask of static random access memory (sram) cell figure, a kind of static random access memory (sram) cell and memory.Mask comprises at least one access nmos pass transistor figure and at least one load PMOS transistor figure, both quantity are equal and have the first identical critical dimension, access nmos pass transistor figure and load PMOS transistor figure are arranged in pairs, and just to connection on the first critical dimension direction.Static random access memory (sram) cell comprises at least one access nmos pass transistor and at least one load PMOS transistor, both quantity are equal and have the first identical critical dimension, access nmos pass transistor and load PMOS transistor are positioned on substrate, paired arrangement, and just to connection on the first critical dimension direction.Memory comprises above-mentioned memory cell.The present invention is simple for production, does not affect device performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of mask, static random access memory (sram) cell and the memory with static random access memory (sram) cell figure.
Background technology
Semiconductor memory is different according to the mode storing data, can be divided into random access memory (RAM) and the large class of read-only memory (ROM) two.Random access memory (RAM) can be divided into again static RAM (SRAM) and dynamic random access memory (DRAM).Compared with DRAM, SRAM has read or write speed faster.And the information that SRAM does not need periodic refresh to store, its Design and manufacture is relatively simple.
SRAM overall structure can be divided into bank array and peripheral circuit two parts.Wherein, bank array is made up of pre-charge circuit and memory cell array.In sram, memory cell is its most basic, most important part, and the area of memory cell occupies the major part of whole integrated circuit chip area.The area of memory cell and stability are two importances of SRAM design.The area of memory cell determines the size of memory chip to a great extent.The stability of memory cell determines the data reliability of memory.
The main flow memory cell of SRAM is six transistor units (6T), and its formation both can be whole CMOS planar structure, also can be laminated type three-dimensional structure.Shown in Fig. 1 is the circuit diagram of traditional whole CMOS SRAM.As shown in Figure 1, the first inverter INV1 and the second inverter INV2 forms latch, drives selectively respectively by access nmos pass transistor TA1 and TA2.First inverter INV1 comprises the first load PMOS transistor TP1 and the first driving N MOS transistor TN1, and the second inverter INV2 comprises the second load PMOS transistor TP2 and the second driving N MOS transistor TN2.Wherein, first load PMOS transistor TP1 is connected with supply voltage Vdd with the source electrode of the second load PMOS transistor TP2, the drain electrode of the first load PMOS transistor TP1 and the drain electrode of the first driving N MOS transistor TN1 are connected in S1 point, the drain electrode of the second load PMOS transistor TP2 and the drain electrode of the second driving N MOS transistor TN2 are connected in S2 point, the grid of the first load PMOS transistor TP1 is connected with the grid of the first driving N MOS transistor TN1 and is connected to S2 point, the grid of the second load PMOS transistor TP2 is connected with the grid of the second driving N MOS transistor TN2 and is connected to S1 point.The grid of the first access nmos pass transistor TA1 is connected with wordline WL, and its source electrode is connected with bit line BL, and its drain electrode is connected with S1 point.Equally, the grid of the second access nmos pass transistor TA2 is connected with wordline WL, and its source electrode non-with bit line (BitLineBar) DBL is connected, and its drain electrode is connected with S2 point.The signal that the non-DBL of bit line transmits is the inversion signal of bit line BL.When wordline WL is high level, access nmos pass transistor TA1 and TA2 conducting, the signal of bit line BL and the non-DBL of bit line is sent to INV1 and INV2 respectively, and the write of data or reading are performed.
When body silicon substrate forms above-mentioned SRAM, easy generation latch phenomenon (latch-up), namely when nmos pass transistor and PMOS transistor arranged adjacent one another time, n-p-n-p structure is formed by the active area of the active area of NMOS, substrate P, N trap, PMOS, when one of them triode positively biased, the phenomenon that positive feedback forms breech lock will be formed.For avoiding above-mentioned phenomenon, the distance between N trap and P trap can be strengthened, but its final result is the chip size increase that result in SRAM.
In order to avoid latch phenomenon, SRAM is integrated into (SOI, SiliconOnInsulator) in silicon-on-insulator substrate by existing technique.In SOI technology, device is only manufactured in the very thin silicon fiml in top layer, separated by one deck buried oxidation layer between device and substrate, when SRAM is integrated in silicon-on-insulator substrate, transistor is all formed among SOI substrate Shang Dao district (Island), form STI isolation between the district of island, can not produce as the latch phenomenon in body silicon substrate.
At present in order to ensure that the memory cell of SRAM normally works, the size of the driving N MOS transistor in memory cell must be greater than access nmos pass transistor, to obtain β value (betaratio).Both size disparities are larger, and its betaratio is larger; And betaratio value is larger, the stability of memory cell is higher.But, when actual fabrication driving N MOS transistor is greater than access nmos pass transistor, all inevitably create chamfering to a certain degree needing the part being made into right angle.Use such mask to carry out subsequent step, finally can have influence on the performance of device.
Be disclose more information about SOISRAM memory cell in the U.S. Patent application of US6198173B1 at document number.
Summary of the invention
Technical problem to be solved by this invention makes static random access memory (sram) cell simple for production, can not affect device performance because right angle portions is impaired.
In order to solve the problem, the invention provides a kind of mask with static random access memory (sram) cell figure, comprise at least one access nmos pass transistor figure and at least one load PMOS transistor figure; Described access nmos pass transistor figure is equal with load PMOS transistor figure quantity and have the first identical critical dimension, described access nmos pass transistor figure and described load PMOS transistor figure are arranged in pairs, and just to connection on the first critical dimension direction.
Optionally, described mask also comprises at least one driving N MOS transistor figure, and described driving N MOS transistor figure has the second critical dimension.
Optionally, described second critical dimension is greater than the first critical dimension.
Optionally, described mask comprises first, second access nmos pass transistor figure, first, second driving N MOS transistor figure and first, second load PMOS transistor figure, described first access nmos pass transistor figure and described first load PMOS transistor figure are just to being connected on the first critical dimension direction, and described second accesses nmos pass transistor figure and described second load PMOS transistor figure on the first critical dimension direction just to being connected.
Optionally, the first driving N MOS transistor figure of described mask and the second driving N MOS transistor figure are between the first access nmos pass transistor figure and the second access nmos pass transistor figure, and noncontact each other.
Present invention also offers a kind of static random access memory (sram) cell, comprise at least one access nmos pass transistor and the load PMOS transistor of at least one, described access nmos pass transistor is equal with load PMOS number of transistors and have the first identical critical dimension, and described access nmos pass transistor and described load PMOS transistor are positioned on substrate; Described access nmos pass transistor and described load PMOS transistor are arranged in pairs, and just to connection on the first critical dimension direction.
Optionally, described static random access memory (sram) cell also comprises at least one the driving N MOS transistor be positioned on substrate, and described driving N MOS transistor has the second critical dimension.
Optionally, described second critical dimension is greater than the first critical dimension.
Optionally, described static random access memory (sram) cell comprises first, second access nmos pass transistor, first, second driving N MOS transistor and first, second load PMOS transistor, described first access nmos pass transistor and described first load PMOS transistor is just to being connected on the first critical dimension direction, and described second accesses nmos pass transistor and described second load PMOS transistor on the first critical dimension direction just to being connected.
Optionally, described first driving N MOS transistor and the second driving N MOS transistor are between the first access nmos pass transistor and the second access nmos pass transistor, and noncontact each other.
Optionally, described substrate is silicon-on-insulator substrate, the top silicon layer comprising silicon substrate, be positioned at the oxide skin(coating) on silicon substrate and be positioned on oxide skin(coating).
Optionally, source electrode and the drain electrode of described each transistor are positioned at described top silicon layer, and bottom all contacts with described oxide skin(coating).
Optionally, the source electrode of the grid of described first load PMOS transistor, the grid of described first driving N MOS transistor, the drain electrode of described second load PMOS transistor, described second driving N MOS transistor, the drain electrode electrical connection of described second access nmos pass transistor;
The source electrode of the grid of described second load PMOS transistor, the grid of described second driving N MOS transistor, the drain electrode of described first load PMOS transistor, described first driving N MOS transistor, the drain electrode electrical connection of described first access nmos pass transistor.
Present invention also offers a kind of static RAM, comprise writing unit, bank array, sensing element, described bank array is made up of any one memory cell above-mentioned.
Optionally, described static RAM also comprises the dielectric layer be positioned in described bank array, is positioned at the interconnection layer on dielectric layer, and described interconnection layer comprises wordline, bit line, power and ground;
Described wordline is electrically connected with the grid of described access nmos pass transistor;
Described bit line is electrically connected with the source electrode of described access nmos pass transistor;
Described power line is electrically connected with the source electrode of described load PMOS transistor;
Described ground wire is electrically connected with the drain electrode of described driving N MOS transistor.
Compared with prior art, technical scheme of the present invention has the following advantages:
By there is the metal-oxide-semiconductor of identical critical dimension just to arrangement, avoid the mismatch problem caused in plate-making and subsequent process because critical dimension differs, make simpler, and the performance of device can not be had influence on because right angle is impaired.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of traditional whole CMOS SRAM;
Fig. 2 is the existing schematic top plan view with the mask of static random access memory (sram) cell figure;
Fig. 3 is the schematic top plan view with a kind of embodiment of the mask of static random access memory (sram) cell figure of the present invention;
Fig. 4 is the cross-sectional view intercepted along AA ' line by the memory cell that mask shown in Fig. 3 is obtained.
Embodiment
Existing technique is in order to ensure that the memory cell of SRAM normally works, and the size of the driving N MOS transistor in memory cell must be greater than access nmos pass transistor, to obtain β value (betaratio).Both size disparities are larger, and its betaratio is larger; And betaratio value is larger, the stability of memory cell is higher.
Fig. 2 is the existing schematic top plan view with the mask of static random access memory (sram) cell figure.As shown in Figure 2, the first load PMOS transistor TP1 figure, the first access nmos pass transistor TA1 figure, the second load PMOS transistor TP2 figure, the second access nmos pass transistor TA2 figure have the first identical critical dimension a.First driving N MOS transistor TN1 figure and the second driving N MOS transistor TN2 figure have the second identical critical dimension b.In order to obtain above-mentioned betaratio, second critical dimension b of the first driving N MOS transistor TN1 figure must be greater than the first critical dimension a of the first access nmos pass transistor TA1 figure, in like manner, second critical dimension b of the second driving N MOS transistor TN2 figure is also greater than the first critical dimension a of the second access nmos pass transistor TA2 figure, i.e. b>a.In actual fabrication domain, nmos pass transistor figure and driving N MOS transistor figure will be accessed when critical dimension direction upper part overlapping arrangement (as shown in Figure 2), because size differs, cause not mating (mismatch) on width, thus add manufacture difficulty.Especially the intersection of nmos pass transistor TA1 figure and the first driving N MOS transistor TN1 figure and the intersection of the second access nmos pass transistor TA2 figure and the second driving N MOS transistor TN2 figure is accessed first, because two right angles that size differs (b>a) produces are when reality is made a plate, cannot just in time accomplish 90 °, and inevitably have chamfering to a certain degree.First access nmos pass transistor TA1 figure and the first effect of driving N MOS transistor TN1 figure needed for reality (as is shown in phantom lines) shown in Fig. 2; As a comparison, the second access nmos pass transistor TA2 figure and the second driving N MOS transistor TN2 figure are through reality plate-making income effect (as is shown in phantom lines).The part that visible actual needs is made into right angle all inevitably creates chamfering to a certain degree.Use such mask to carry out subsequent step, finally can have influence on the performance of device.
In order to solve the problem, the present inventor is through research, propose a kind of mask with static random access memory (sram) cell figure newly, specifically as shown in Figure 3, mask comprises: the first load PMOS transistor TP1 figure, the first access nmos pass transistor TA1 figure, the second load PMOS transistor TP2 figure, the second access nmos pass transistor TA2 figure, the first driving N MOS transistor TN1 figure and the second driving N MOS transistor TN2 figure.
In the present embodiment, the first load PMOS transistor TP1 figure, the first access nmos pass transistor TA1 figure, the second load PMOS transistor TP2 figure, the second access nmos pass transistor TA2 figure have the first identical critical dimension a.Wherein, the first access nmos pass transistor TA1 figure and the first load PMOS transistor TP1 figure on the first critical dimension direction just to being connected; Second access nmos pass transistor TA2 figure and the second load PMOS transistor TP2 figure on the first critical dimension direction just to being connected.Described just to connection on the first critical dimension direction the first access nmos pass transistor TA1 figure and the first load PMOS transistor TP1 figure or second to access nmos pass transistor TA2 figure overlapping with the second load PMOS transistor TP2 visuals, and both form a strip.
In the present embodiment, the first driving N MOS transistor TN1 figure, the second driving N MOS transistor TN2 figure have identical second critical dimension b.In order to obtain betaratio, the second critical dimension b is greater than the first critical dimension a.The difference of the first critical dimension a and the second critical dimension b is larger, and the betaratio obtained is larger, and the stability of transistor is also higher.Wherein, the first critical dimension a at least should be more than or equal to the minimum critical dimension that described transistor allows.First driving N MOS transistor TN1 figure and the second driving N MOS transistor TN2 figure with the second critical dimension b access between nmos pass transistor TA2 figure at the first access nmos pass transistor TA1 figure and second, and noncontact each other.
In order to avoid not mating on width, access nmos pass transistor figure and the load PMOS transistor figure in this embodiment with identical critical dimension occur all in pairs, and just to connection on critical dimension direction.
In above-mentioned arrangement mode, just to the transistor be arranged together, all there is identical critical dimension, also just without the right angle produced because critical dimension differs, manufacture more simple.Meanwhile, because do not have right angle, the chamfering that also right angle would not be had to cause has influence on device performance.
Fig. 4 is the cross-sectional view intercepted along AA ' line by the memory cell that mask shown in Fig. 3 is obtained.Although illustrate only the first load PMOS transistor TP1 and first access nmos pass transistor TA1 in Fig. 4, but because other is just to the transistor AND gate first load PMOS transistor TP1 of arrangement, the structural similarity of the first access nmos pass transistor TA1, those skilled in the art by reading structure shown in Fig. 4, without the need to additional inventive work can understand other each transistor just to arrangement.As shown in Figure 4, substrate 100 is silicon-on-insulator substrate (SOI, SiliconOnInsulator), comprises silicon substrate 101, oxide skin(coating) 102 and top silicon layer 103.First access nmos pass transistor TA1 comprises source electrode 104a, drain electrode 104b, grid 106; First load PMOS transistor TP1 comprises source electrode 105a, drain electrode 105b, grid 107.The described source electrode 104a of the first access nmos pass transistor TA1 and the bottom of the drain electrode bottom of 104b and the source electrode 105a of the first load PMOS transistor TP1 and drain electrode 105b contact with oxide skin(coating) 102 respectively, to utilize the buffer action of oxide skin(coating) 102, avoid interacting of the source/drain region in the source/drain region in N trap and P trap, P trap and N trap.The P of the first load PMOS transistor TP1
+the N accessing nmos pass transistor TA1 with first
+also contact with each other.
It should be noted that, memory cell of the present invention needs on insulator silicon (SOI) substrate to realize.This is because SOI technology makes have one deck oxide skin(coating) to separate between device and substrate on the one hand, realizes Fully dielectric isolation, the source/drain region P in N trap
+with the source/drain region N in P trap, P trap
+can not interact with N trap, so the arrangement of each metal-oxide-semiconductor of memory cell of the present invention is achieved.On the other hand, after memory cell of the present invention lines up bank array, its N trap is discontinuous, cannot draw and be connected on fixed potential (ground connection or power supply).And also do not need in the SOI technology of reality to extract, so can on insulator silicon (SOI) substrate be achieved.
Present invention also offers a kind of static RAM, comprise writing unit, bank array, sensing element.Described bank array is made up of memory cell of the present invention.Described static RAM is also formed on silicon-on-insulator (SOI) substrate, also comprise the dielectric layer be positioned in described bank array, be positioned at the interconnection layer on dielectric layer, described interconnection layer comprises wordline, bit line, power and ground, and wordline, bit line, power and ground are electrically connected with corresponding transistor by the connector in dielectric layer.
It should be noted that, still continue to use the electric connection mode of 6T type static random access memory (sram) cell in prior art in this embodiment, that is: the grid of the first access nmos pass transistor, the grid of the second access nmos pass transistor, be electrically connected with wordline; The source electrode of the first access nmos pass transistor, the source electrode of the second access nmos pass transistor, be electrically connected with bit line; The source electrode of the first load PMOS transistor, the source electrode of the second load PMOS transistor, be electrically connected with power line; The drain electrode of the first driving N MOS transistor, the drain electrode of the second driving N MOS transistor, be electrically connected with ground wire; The drain electrode electrical connection of the drain electrode of the grid of the first load PMOS transistor, the grid of the first driving N MOS transistor, the second load PMOS transistor, the source electrode of the second driving N MOS transistor, the second access nmos pass transistor; The drain electrode electrical connection of the drain electrode of the grid of the second load PMOS transistor, the grid of the second driving N MOS transistor, the first load PMOS transistor, the source electrode of the first driving N MOS transistor, the first access nmos pass transistor.In other embodiments, other electric connection mode can be had.
Described bank array and memory all can be realized by this area conventional means, and its specific implementation is well known to those skilled in the art, and does not repeat them here.
It should be noted that, although all adopt conventional 6T type static random access memory (sram) cell to be described and to explain in this embodiment, not should be understood to the present invention and be only limitted to 6T type static random access memory (sram) cell.In fact, other the static random access memory (sram) cell expanded on 6T type basis, such as: 4T, 8T, 5T, as long as its access nmos pass transistor is equal with load PMOS number of transistors and have identical critical dimension, all available the present invention is achieved.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. there is a mask for static random access memory (sram) cell figure, comprise at least one access nmos pass transistor figure and at least one load PMOS transistor figure; Described access nmos pass transistor figure is equal with load PMOS transistor figure quantity and have the first identical critical dimension, it is characterized in that:
Described access nmos pass transistor figure and described load PMOS transistor figure are arranged in pairs, and just to connection on the first critical dimension direction, described just to connecting on the first critical dimension direction, the described access nmos pass transistor of arrangement is overlapping with described load PMOS transistor visuals in pairs, and form a strip.
2. mask as claimed in claim 1, it is characterized in that: also comprise at least one driving N MOS transistor figure, described driving N MOS transistor figure has the second critical dimension.
3. mask as claimed in claim 2, is characterized in that: described second critical dimension is greater than the first critical dimension.
4. mask as claimed in claim 2, it is characterized in that: described mask comprises first, second access nmos pass transistor figure, first, second driving N MOS transistor figure and first, second load PMOS transistor figure, described first access nmos pass transistor figure and described first load PMOS transistor figure are just to being connected on the first critical dimension direction, and described second accesses nmos pass transistor figure and described second load PMOS transistor figure on the first critical dimension direction just to being connected.
5. mask as claimed in claim 4, is characterized in that: described first driving N MOS transistor figure and the second driving N MOS transistor figure are between the first access nmos pass transistor figure and the second access nmos pass transistor figure, and noncontact each other.
6. a static random access memory (sram) cell, comprise at least one access nmos pass transistor and the load PMOS transistor of at least one, described access nmos pass transistor is equal with load PMOS number of transistors and have the first identical critical dimension, it is characterized in that:
Described access nmos pass transistor and described load PMOS transistor are positioned on substrate;
Described access nmos pass transistor and described load PMOS transistor are arranged in pairs, and just to connection on the first critical dimension direction, described just to connecting on the first critical dimension direction, the described access nmos pass transistor of arrangement is overlapping with described load PMOS transistor visuals in pairs, and form a strip.
7. static random access memory (sram) cell as claimed in claim 6, is characterized in that: also comprise at least one the driving N MOS transistor be positioned on substrate, described driving N MOS transistor has the second critical dimension.
8. static random access memory (sram) cell as claimed in claim 7, is characterized in that: described second critical dimension is greater than the first critical dimension.
9. static random access memory (sram) cell as claimed in claim 7, it is characterized in that: comprise first, second access nmos pass transistor, first, second driving N MOS transistor and first, second load PMOS transistor, described first access nmos pass transistor and described first load PMOS transistor is just to being connected on the first critical dimension direction, and described second accesses nmos pass transistor and described second load PMOS transistor on the first critical dimension direction just to being connected.
10. static random access memory (sram) cell as claimed in claim 9, is characterized in that:
Described first driving N MOS transistor and the second driving N MOS transistor are between the first access nmos pass transistor and the second access nmos pass transistor, and noncontact each other.
11. static random access memory (sram) cells as claimed in claim 7, is characterized in that: described substrate is silicon-on-insulator substrate, the top silicon layer comprising silicon substrate, be positioned at the oxide skin(coating) on silicon substrate and be positioned on oxide skin(coating).
12. static random access memory (sram) cells as claimed in claim 11, is characterized in that: source electrode and the drain electrode of described each transistor are positioned at described top silicon layer, and bottom all contacts with described oxide skin(coating).
13. static random access memory (sram) cells as claimed in claim 9, is characterized in that:
The source electrode of the grid of described first load PMOS transistor, the grid of described first driving N MOS transistor, the drain electrode of described second load PMOS transistor, described second driving N MOS transistor, the drain electrode electrical connection of described second access nmos pass transistor;
The source electrode of the grid of described second load PMOS transistor, the grid of described second driving N MOS transistor, the drain electrode of described first load PMOS transistor, described first driving N MOS transistor, the drain electrode electrical connection of described first access nmos pass transistor.
14. 1 kinds of static RAMs, is characterized in that: comprise writing unit, bank array, sensing element, and described bank array is made up of any one memory cell in claim 7 to 13.
15. static RAMs as claimed in claim 14, is characterized in that:
Described static RAM also comprises the dielectric layer be positioned in described bank array, is positioned at the interconnection layer on dielectric layer, and described interconnection layer comprises wordline, bit line, power and ground;
Described wordline is electrically connected with the grid of described access nmos pass transistor;
Described bit line is electrically connected with the source electrode of described access nmos pass transistor;
Described power line is electrically connected with the source electrode of described load PMOS transistor;
Described ground wire is electrically connected with the drain electrode of described driving N MOS transistor.
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| CN1485926A (en) * | 2002-09-04 | 2004-03-31 | ���ǵ�����ʽ���� | Sram formed on soi substrate |
| CN1677681A (en) * | 2004-03-31 | 2005-10-05 | 台湾积体电路制造股份有限公司 | Connection structure for SOI devices |
| CN102298956A (en) * | 2011-06-14 | 2011-12-28 | 上海宏力半导体制造有限公司 | Static random access memory (SRAM) formed on silicon on insulator (SOI) substrate |
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| US7078297B2 (en) * | 2004-05-28 | 2006-07-18 | Freescale Semiconductor, Inc. | Memory with recessed devices |
| US7915691B2 (en) * | 2007-10-30 | 2011-03-29 | International Business Machines Corporation | High density SRAM cell with hybrid devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1485926A (en) * | 2002-09-04 | 2004-03-31 | ���ǵ�����ʽ���� | Sram formed on soi substrate |
| CN1677681A (en) * | 2004-03-31 | 2005-10-05 | 台湾积体电路制造股份有限公司 | Connection structure for SOI devices |
| CN102298956A (en) * | 2011-06-14 | 2011-12-28 | 上海宏力半导体制造有限公司 | Static random access memory (SRAM) formed on silicon on insulator (SOI) substrate |
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