CN102722600A - Method for calculating chip power consumption - Google Patents

Method for calculating chip power consumption Download PDF

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CN102722600A
CN102722600A CN2012101350291A CN201210135029A CN102722600A CN 102722600 A CN102722600 A CN 102722600A CN 2012101350291 A CN2012101350291 A CN 2012101350291A CN 201210135029 A CN201210135029 A CN 201210135029A CN 102722600 A CN102722600 A CN 102722600A
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power consumption
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CN102722600B (en
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杨小林
杜刚
刘晓彦
张兴
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Peking University
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Abstract

The invention discloses a method for calculating chip power consumption. The method comprises the following steps: A, selecting the technology and the working voltage of a chip, and carrying out SPICE simulation on logic gate standard cells under the technology in different input states; B, according to a simulation result, for each logic gate standard cell, establishing a lookup table of the input states corresponding to leakage power consumptions; C, reading the logic gate in the circuit meshwork list of the chip, and determining that the logic gate input is the total input of the chip or the output of other logic gates; D, according to a determination result, calculating the probability of each input equal to (0) or (1) of the logic gate; E, according to the corresponding relation of the input states of the logic gate and leakage power consumptions and the probability of logic gate input states, calculating the leakage power consumption of the logic gate; and F, traversing the logic gates of the chip to obtain the leakage power consumption of each logic gate, and accumulating the obtained leakage power consumptions of the logic gates to obtain the leakage power consumption of the chip. The method of the invention can improve calculation accuracy of the chip power consumption based on a statistical sense.

Description

The computing method of chip power-consumption
Technical field
The present invention relates to the SIC (semiconductor integrated circuit) technical field, relate in particular to a kind of computing method of chip power-consumption.
Background technology
Current, along with constantly reducing of chip features size, the leakage power of chip proportion in whole power consumption is increasing, and the chip leakage power is mainly caused by the leakage current of metal-oxide-semiconductor.The metal-oxide-semiconductor leakage current mainly is made up of sub-threshold current leakage, gate oxide leakage current and substrate leakage current.Sub-threshold current leakage is dominate in three kinds of leakage currents, and the statistical computation mode of three kinds of electric currents is about the same, therefore, carries out the major part that has been calculated to be power consumption analysis based on the sub-threshold current leakage of statistics.
Chip power-consumption analysis based on statistics is a kind of method of the overall power of chip being assessed in the gate level netlist stage of Design of Digital Integrated Circuit.For a certain special process, estimate chip power-consumption for circuit optimization and all fabulous directive property effect of layout design afterwards, thereby become necessary part in the Design of Digital Integrated Circuit.Current, more international bigger EDA company such as Cadence, Synopsys has the power consumption analysis instrument of oneself; The content of analyzing comprises the power consumption size; Variance, probability density function (Probability Density Function) etc., the power consumption size is wherein most basic part.
At present, handle by following two kinds of methods usually based on statistical power consumption analysis:
1. for a certain concrete cmos logic gate, suppose that the probability of its various input states is identical (, to be input as 00 as for two input nand gates; 01,10,11 probability is 1/4); When adding up its power consumption, the power consumption of its different input states is pressed the equiprobability weighted sum;
2. carry out equiprobability for different input states and distribute, for any cmos logic gate, will be from the output node to ground between the identical input state of conducting metal-oxide-semiconductor quantity merge.
Method 1 is not considered the logical relation between each logic gate, thereby makes for certain some certain logic door, carries out arbitrarily to it that permutation and combination can draw identical result of calculation, thereby error is bigger.Though and 2 pairs of states of method merge and have reduced calculated amount, have increased error, as 4 input nand gates when input state is < 1000>and phase inverter at the leakage current of input state during and different for < 1 >, but this method unifiedly is a kind of expression formula with it.
Summary of the invention
The technical matters that (one) will solve
The technical matters that the present invention will solve is: a kind of computing method of chip power-consumption are provided, and it can improve the computational accuracy based on the chip power-consumption on the statistical significance.
(2) technical scheme
For addressing the above problem, the invention provides a kind of computing method of chip power-consumption, may further comprise the steps:
A: the technology and the WV of selected chip, the logic gate standard block under this technology is carried out SPICE emulation under different input states;
B: according to simulation result, for each logic gate standard block is set up input state and the corresponding look-up table of leakage power;
C: read the logic gate in the circuit meshwork list of chip, each input of this logic gate is judged that it is that total input of chip still is the output of other logic gates;
D: the probability that equals < 0>or < 1>according to each input of this logic gate of judged result calculating;
E:, calculate the leakage power of this logic gate according to each input state and the corresponding relation of leakage power and the probability of this each input state of logic gate of this logic gate in the look-up table;
F: each logic gate is obtained the leakage power of each logic gate in the traversal chip, and the leakage power of each logic gate of obtaining is added up obtains the leakage power of chip.
In the computing method of aforesaid chip power-consumption, said step D further comprises: if the total input that is input as chip of this logic gate, then to equal the probability of < 0>or < 1>be 1/2 in this input;
If the output that is input as logic gate A of this logic gate, computational logic door A is output as the probability of < 0>or < 1 >, as the step of the corresponding probability of importing of this logic gate.
In the computing method of aforesaid chip power-consumption, computational logic door A is output as<0>Or<1>Probability, further comprise: the probability of establishing each input state of logic gate A is 1/2 NStep, N is the input number of logic gate A.
In the computing method of aforesaid chip power-consumption, said step e further comprises: the leakage power under the different input states of this logic gate is carried out the step that the leakage power of this logic gate is obtained in weighted sum according to the probability of input state.
In the computing method of aforesaid chip power-consumption, said steps A also comprises: the step of obtaining the sub-threshold current leakage of logic gate standard block under different input states.
In the computing method of aforesaid chip power-consumption, said step B further comprises: for the logic gate standard block of N input, set up 2 NThe step of individual input state and the corresponding look-up table of leakage power.
(3) beneficial effect
When calculating based on the chip power-consumption on the statistical significance; Always import the input state of deducing each from chip fully and need specific circuit structure (combinational circuit); And can add intensive, and give no thought to the input and output annexation between the logic gate, then can cause the error of calculation bigger.The present invention can significantly reduce the error of calculation with the two consideration that combines under the situation that increases the low computational effort amount, can be easy to be generalized to simultaneously two kinds of computing method in addition.
Description of drawings
Fig. 1 is the process flow diagram of the computing method of chip power-consumption described in the embodiment of the present invention;
Fig. 2 is the schematic diagram of the computing method of chip power-consumption described in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
Shown in Fig. 1-2, the computing method of a kind of chip power-consumption of the present invention may further comprise the steps:
A: selected a certain special process and WV; To the logic gate standard block under this technology: like two input nand gate NAND2 etc.; (< 00 >, < 01 >, < 10>under different input states; < 11 >) carry out SPICE emulation, also can obtain the sub-threshold current leakage of logic gate standard block under different input states;
B: according to simulation result, for each logic gate standard block is set up input state and the corresponding look-up table of leakage power (Look-Up-Table).For the logic gate standard block of N input, set up 2 NThe corresponding look-up table of individual input state and leakage power;
C: for a certain circuit meshwork list (like ISCAS85 Benchmark) of chip, the delegation that reads the net table judges that its total input that is input as chip still is the output of other logic gates; (G9 G5), representes two input nand gates, is input as G9, and G5 is output as G15 like G15=NAND.Judge that G9 and G5 are the total input of chip or the output of other logic gates;
D: if the total input that is input as chip of this logic gate, then to equal the probability of < 0>or < 1>be 1/2 in this input;
If the output that is input as other logic gates A of this logic gate, the probability of setting each input state of logic gate A is 1/2 N, wherein N is the input number of logic gate A, and computational logic door A output state does in view of the above<0>Or<1>Probability, as the state probability of the corresponding input of this NAND logic gate;
E:, calculate the leakage power of this logic gate, that is: according to each input state and the corresponding relation of leakage power and the probability of this each input state of logic gate of this logic gate in the look-up table
Figure DEST_PATH_GDA00001875055200011
P wherein Gate.iThe leakage power of presentation logic door i, p (n) expression input state is the probability of n, input state is the leakage power of n in P (n) the expression look-up table.(n is expressed as scale-of-two in the look-up table)
F: according to step C-E; Traversal each logic gate in the chip, and to the leakage power of each logic gate of obtaining add up just can obtain entire chip leakage power for
Figure DEST_PATH_GDA00001875055200012
wherein W be the number that Benchmark comprises logic gate.
Use the method for the invention respectively 6 kinds of different chips (Benchmark) to be made an experiment: make total input end of chip produce input vector at random, carry out revision test 1000 times, experimental result is as shown in table 1.Can find out by table 1, adopt the error of the inventive method computing chip power consumption obviously to reduce.
Table 1
Figure BDA0000159050070000051
Wherein, Random input sampling refers to produce input vector at random at total input end of benchmark (chip), carries out revision test 1000 times;
The state of Total input 1/2 each total input end of finger setting is 1/2 for the probability of < 0>or < 1 >, deduces the probability of calculating each different input state from total input;
The state that Gate input 1/2 refers to set each input end of each is 1/2 for the probability of < 0>or < 1 >;
My method is a method used in the present invention.
Above embodiment only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.

Claims (6)

1.一种芯片功耗的计算方法，其特征在于，包括以下步骤：1. a calculation method of chip power consumption, is characterized in that, comprises the following steps: A：选定芯片的工艺及工作电压，对该工艺下的逻辑门标准单元在不同输入状态下进行SPICE仿真；A: Select the process and working voltage of the chip, and perform SPICE simulation on the logic gate standard cell under the process under different input states; B：根据仿真结果，为每个逻辑门标准单元建立输入状态与泄漏功耗相对应的查找表；B: According to the simulation results, a look-up table corresponding to the input state and leakage power consumption is established for each logic gate standard unit; C：读取芯片的电路网表中的逻辑门，对该逻辑门的每一个输入判断其为芯片的总输入还是其他逻辑门的输出；C: Read the logic gates in the circuit netlist of the chip, and judge whether each input of the logic gate is the total input of the chip or the output of other logic gates; D：根据判断结果计算该逻辑门的每一个输入等于<0>或<1>的概率；D: Calculate the probability that each input of the logic gate is equal to <0> or <1> according to the judgment result; E：根据查找表中该逻辑门的每一个输入状态与泄漏功耗的对应关系以及该逻辑门每一个输入状态的概率，计算该逻辑门的泄漏功耗；E: Calculate the leakage power consumption of the logic gate according to the corresponding relationship between each input state of the logic gate and the leakage power consumption in the look-up table and the probability of each input state of the logic gate; F：遍历芯片中每一个逻辑门获取每一个逻辑门的泄漏功耗，对获得的每一个逻辑门的泄漏功耗进行累加获得芯片的泄漏功耗。F: traverse each logic gate in the chip to obtain the leakage power consumption of each logic gate, and accumulate the obtained leakage power consumption of each logic gate to obtain the leakage power consumption of the chip. 2.如权利要求1所述的芯片功耗的计算方法，其特征在于，所述步骤D进一步包括：若该逻辑门的输入为芯片的总输入，则该输入等于<0>或<1>的概率为1/2；2. The method for calculating chip power consumption according to claim 1, wherein said step D further comprises: if the input of the logic gate is the total input of the chip, then the input is equal to <0> or <1> The probability of is 1/2; 若该逻辑门的输入为逻辑门A的输出，计算逻辑门A输出为<0>或<1>的概率，作为该逻辑门对应输入的概率的步骤。If the input of the logic gate is the output of logic gate A, calculate the probability that the output of logic gate A is <0> or <1>, as a step of the probability of the corresponding input of the logic gate. 3.如权利要求2所述的芯片功耗的计算方法，其特征在于，计算逻辑门A输出为<0>或<1>的概率，进一步包括：设逻辑门A的每一种输入状态的概率为1/2N的步骤，N为逻辑门A的输入个数。3. The calculating method of chip power consumption as claimed in claim 2 is characterized in that, calculating the probability that logic gate A outputs is <0> or <1>, further comprises: setting each input state of logic gate A A step with a probability of 1/2N, where N is the number of inputs to logic gate A. 4.如权利要求1所述的芯片功耗的计算方法，其特征在于，所述步骤E进一步包括：对该逻辑门不同输入状态下的泄漏功耗按照输入状态的概率进行加权求和获取该逻辑门的泄漏功耗的步骤。4. The calculation method of chip power consumption as claimed in claim 1, characterized in that, said step E further comprises: carrying out weighted summation according to the probability of the input state of the leakage power consumption of the logic gate under different input states to obtain the Steps for leakage power consumption of logic gates. 5.如权利要求1所述的芯片功耗的计算方法，其特征在于，所述步骤A还包括：获取逻辑门标准单元在不同输入状态下的亚阈值漏电流的步骤。5 . The method for calculating chip power consumption according to claim 1 , wherein said step A further comprises: a step of obtaining subthreshold leakage currents of logic gate standard cells under different input states. 6 . 6.如权利要求1所述的芯片功耗的计算方法，其特征在于，所述步骤B进一步包括：对于N输入的逻辑门标准单元，建立2N个输入状态与泄漏功耗相对应的查找表的步骤。6. The calculation method of chip power consumption as claimed in claim 1, is characterized in that, described step B further comprises: For the logic gate standard cell of N input, set up the look-up table corresponding to 2N input state and leakage power consumption A step of.
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CN110619168A (en) * 2019-09-11 2019-12-27 上海高性能集成电路设计中心 Super-large-scale chip information analysis method based on netlist
CN113988469A (en) * 2021-11-17 2022-01-28 海光信息技术股份有限公司 Method and device for predicting static power consumption of chip, electronic equipment and storage medium
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CN118709645A (en) * 2024-08-30 2024-09-27 英诺达(成都)电子科技有限公司 Leakage power consumption calculation method, device, electronic device, storage medium and computer program product

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CN104424377A (en) * 2013-08-30 2015-03-18 台湾积体电路制造股份有限公司 System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (pode)
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CN113988469A (en) * 2021-11-17 2022-01-28 海光信息技术股份有限公司 Method and device for predicting static power consumption of chip, electronic equipment and storage medium
CN115792364A (en) * 2023-02-07 2023-03-14 南京美斯玛微电子技术有限公司 Power consumption calculation method based on standby state analysis
CN118709645A (en) * 2024-08-30 2024-09-27 英诺达(成都)电子科技有限公司 Leakage power consumption calculation method, device, electronic device, storage medium and computer program product

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