CN102710917A - Slicer level calculating device - Google Patents
Slicer level calculating device Download PDFInfo
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- CN102710917A CN102710917A CN2011100848996A CN201110084899A CN102710917A CN 102710917 A CN102710917 A CN 102710917A CN 2011100848996 A CN2011100848996 A CN 2011100848996A CN 201110084899 A CN201110084899 A CN 201110084899A CN 102710917 A CN102710917 A CN 102710917A
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Abstract
The invention discloses a slicer level calculating device, which comprises a signal detecting circuit, a moving average calculating circuit, a synchronous tip (sync-tip) voltage sampling circuit, a blank voltage sampling circuit, a slicer voltage level arithmetic circuit and a backend processing circuit. The signal detecting circuit judges whether an input image signal meets a low signal to noise ratio (SNR) condition or not, and if so, enables a low SNR control signal. The moving average calculating circuit finds out the moving average voltage level of the input image signal. The sync-tip voltage sampling circuit, the blank voltage sampling circuit and the slicer voltage level arithmetic circuit respectively find out a sync-tip voltage level, a blank voltage level and a slicer voltage level. The backend processing circuit selectively carries out a low-frequency wave filtration operation on the slicer voltage level in response to the low SNR control signal.
Description
Technical field
The invention relates to a kind of clip level (Slicer Level) calculation element; And particularly relevant for a kind of signal noise of importing signal of video signal of adapting to than (Signal to Noise Ratio, SNR) condition and with disturbing (Co-channel Interference) condition to change the clip level calculation element of clip level calculating operation frequently.
Background technology
In the prior art, the technology that reduction obtains synchronizing signal (Sync.Signal) according to the signal of video signal that receives exists.With synchronizing signal is the situation of two bits (Binary) signal, and the level of signal of video signal can correspond to different two signal levels (high level and low level) in response to different logical value (logical value 1 and logical value 0).In this example, if desire is carried out the restoring operation of synchronizing signal to this signal of video signal, need judge accordingly then that in this signal of video signal which partly corresponds to logical value 1 and which partly corresponds to logical value 0, reduction obtains this synchronizing signal by this.In general; The logical value decision operation of aforementioned signal of video signal is via relatively the level of signal of video signal and the level of clip level (Slicer Level) realize that wherein clip level for example is the intermediate value of the blank voltage level (Blanking Level) and synchronous top (Sync-tip) voltage level of signal of video signal.
Yet in actual conditions; Often because the signal noise of signal of video signal than (Signal to Noise Ratio; SNR) cross low or it is subjected to the influence of disturbing (Co-channel Interference) frequently; The accuracy of the clip level that feasible estimation obtains is lower, and then causes lock in time the synchronizing signal error rate problem of higher that (Sync Timing) is long and reduction obtains.
Summary of the invention
The present invention is relevant for a kind of clip level (Slicer Level) calculation element; Compared to traditional clip level counting circuit; The clip level calculation element that the present invention is correlated with has can be at the signal noise of signal of video signal than (Signal to Noise Ratio; SNR) lower or its receive with frequently disturbing under the situation of (Co-channel Interference), produce the advantage of the higher clip level of accuracy effectively.
A kind of clip level calculation element is proposed according to the present invention; In order to find out the clip level of input signal of video signal, the clip level calculation element comprises first signal deteching circuit, rolling average counting circuit, synchronous top (Sync-tip) voltage value circuit, blank voltage value circuit, limiting voltage level computing circuit and back-end processing circuit.First signal deteching circuit judges whether the input signal of video signal satisfies the low signal noise than (Signal to Noise Ratio, SNR) condition is if first signal deteching circuit enables low SNR control signal.The rolling average counting circuit is found out the rolling average voltage level of input signal of video signal.Top voltage value circuit is found out the synchronous top voltage level of synchronous top temporal information and input signal of video signal synchronously.Blank voltage value circuit is found out the blank voltage level of blank time information and input signal of video signal with reference to synchronous top temporal information.Limiting voltage level computing circuit is according to top voltage level and blank voltage level are found out the limiting voltage level synchronously.The back-end processing circuit optionally carries out the low frequency filtering operation to the limiting voltage level in response to low SNR control signal.
For there is better understanding above-mentioned and other aspects of the present invention, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows:
Description of drawings
Fig. 1 illustrates the calcspar according to the clip level calculation element of first embodiment of the invention.
It is the detailed block diagram of the signal deteching circuit 12 among Fig. 1 that Fig. 2 illustrates.
It is the operation chart of the comparing unit 12d among Fig. 2 that Fig. 3 illustrates.
Fig. 4 illustrates the calcspar according to the clip level calculation element of second embodiment of the invention.
It is the detailed block diagram of the signal deteching circuit 33 among Fig. 4 that Fig. 5 illustrates.
It is the detailed block diagram of the control circuit 31 among Fig. 4 that Fig. 6 illustrates.
[main element symbol description]
1,3: the clip level calculation element
10,20,22a, 213,217,30,42a, 329: low pass filter
12,32,33: signal deteching circuit
14,34: the rolling average counting circuit
16,36: synchronous top voltage value circuit
18,38: blank voltage value circuit
20,40: the limiting voltage electrical level computing circuit
22,42: the back-end processing circuit
24,44: the synchronous altitude signal computing circuit
26,46: sequential control circuit
14a, 207,34a: summer
14b, 20b, 209,215,34b, 40b, 332,406,409,423,426: multiplier
16a, 36a: minimum value is searched the unit
16b, 18b, 22c, 211,36b, 38b, 40d, 42c, 44d, 323,325: buffer
18a, 38a: following counting unit
20a, 24a, 203,225,40a, 44a, 327,312: adder
22b, 223,40e, 42b, 309: multiplexer
24b, 205,44b: absolute value value device
26a, 46a: horizontal synchronization phase-locked loop unit
26b, 46b: timing unit
12a, 33a: arithmetic element
201: delayer
12b, 12d, 33b, 33d, 304,31a, 31b, 31c: comparing unit
12c, 33c: counting unit
227,314: counter
36c, 40c, 42d, 44c, 31d: logical block
NOT1, OT2, NOT3: inverse gate
OR1, OR2, OR3: or door
440,441,442,443, AND1, AND2, AND3: and door
31: control circuit
33e: timing control unit
319: the maximum search unit
320: minimum value is searched the unit
301: go up counting unit
401,403,411,429,414,432: comparator
Embodiment
The clip level of present embodiment (Slicer Level) calculation element; With when the output enable switch switches its conduction and cut-off state, isolate its corresponding voltage that produces and redistribute the part circuit in effect and electric charge coupling effect (Coupling Effect) and the operational amplifier.
First embodiment
The clip level calculation element of present embodiment is to use to be relevant to the signal noise than (Signal to Noise ratio; SNR) signal deteching circuit when the input signal of video signal corresponds to different SNR value, calculates clip level with different arithmetic operations with fitting property.
Please with reference to Fig. 1, it illustrates the calcspar of clip level (Slicer Level) calculation element according to first embodiment of the invention.Clip level calculation element 1 receives input signal of video signal Vs and finds out its clip level Lsl.Clip level calculation element 1 comprises low pass filter 10, signal deteching circuit 12, rolling average counting circuit 14, synchronous top (Sync-tip) voltage value circuit 16, blank voltage value circuit 18, limiting voltage electrical level computing circuit 20, back-end processing circuit 22 and sequential control circuit 26.Low pass filter 10 is in order to produce the input signal of video signal VsL behind the LPF according to input signal of video signal Vs.
Signal deteching circuit 12 judges whether the input signal of video signal VsL behind the LPF satisfies the low signal noise than (Signal to Noise Ratio, SNR) condition; When the input signal of video signal VsL behind the LPF satisfied this low SNR condition, signal deteching circuit 12 enabled low SNR control signal S1.For instance, signal deteching circuit 12 arithmetic element 12a, comparing unit 12b, 12d and counting unit 12c, as shown in Figure 2.
Delayer 201 and adder 203 are in order to find out radio-frequency component signal VsH according to the difference of input signal of video signal Vs and the VsL of low frequency composition signal.Absolute value value device 205, summer 207 and multiplier 209 are in order to carry out absolute value rolling average arithmetic operation according to radio-frequency component signal VsH, to obtain noise strength signal NS.Buffer 211 is in response to enabling sequence number E2, and noise strength signal NS is taken a sample obtains sampled signal NS_S.And low pass filter 213 and multiplier 215, it is in order to the operation that computes weighted according to sampled signal NS_S, to produce noise strength signal Nr.
Comparing unit 12b judges that whether its noise strength signal Nr is greater than the synchronous altitude signal SH_L behind the LPF that produces via low pass filter 217; If comparing unit 12b provides the selection signal F1 that corresponds to first level (for example being the selection signal F1 that corresponds to logical value 1); If not, comparing unit 12b provides the selection signal F1 that corresponds to second level (for example being the selection signal F1 that corresponds to logical value 0).
For instance; Synchronous altitude signal SH is by 24 generations of the synchronous altitude signal computing circuit in the clip level calculation element 1; Comprising adder 24a and absolute value value device 24b, its absolute value in order to the difference of synchronous top voltage level L_synctip of basis and blank voltage level L_blanking produces synchronous altitude signal SH.
Comparing unit 12d judges that whether parameter Psnr is greater than critical value M1.During greater than critical value M1, comparing unit 12d judges that input signal of video signal Vs satisfies low SNR condition, and triggers the low SNR control signal S1 that enables accordingly in the numerical value of judging parameter Psnr, and wherein M is the natural number greater than 1.For instance; Comparing unit 12d for example is sluggish comparing unit (Hysteresis Comparator); Its beginning output when judging parameter Psnr greater than critical value M1 (promptly being to judge that input signal of video signal Vs satisfies low SNR condition) corresponds to the low SNR control signal S1 that enables level (for example being logical value 1); And beginning output corresponds to the low SNR control signal S1 of disable level (for example being logical value 0) when judging parameter Psnr less than critical value 0 (promptly being to judge that input signal of video signal Vs does not satisfy low SNR condition), and is as shown in Figure 3; Wherein critical value M1 is greater than numerical value 0.
Rolling average counting circuit 14 is found out the rolling average voltage level Lma of the input signal of video signal VsL behind the LPF.For instance; Rolling average counting circuit 14 comprises summer 14a and multiplier 14b; Wherein summer 14a is for example according to following equation, calculate during N the operator of one period operating period in behind the LPF input signal of video signal VsL add total value:
Wherein i is a time index, and N is the natural number greater than 1.Multiplier 14b adds total value divided by N in order to what summer 14a totalling was obtained, to obtain importing signal of video signal VsL in the average voltage level Lma of this section in operating period accordingly.
Synchronously top voltage value circuit 16 is found out the synchronous top voltage level L_synctip of synchronous top temporal information T_synctip and input signal of video signal Vs in this section in operating period.For instance, top voltage value circuit 16 comprises minimum value search unit 16a and buffer 16b synchronously.Minimum value is searched unit 16a in order to when finding out the minimum value of this section rolling average voltage level Lma in operating period, to enable M signal E1.Buffer 16b takes a sample to rolling average voltage level Lma in response to the M signal E1 that enables, to obtain synchronous top voltage level L_synctip.Minimum value is searched unit 16a and more for example is replacement in response to the row update signal Slu that enables, and carries out the seek operations of synchronous summit voltage level L_synctip by this to the image data of next row.
Blank voltage value circuit 18 is found out the blank voltage level L_blanking of blank time information T_blanking and input signal of video signal Vs with reference to top temporal information T_synctip synchronously in this section in operating period.For instance; Blank voltage value circuit 18 comprises counting unit (Down Counter) 18a and buffer 18b down; Wherein descend counting unit 18a to carry out number operation down, after receiving the one period time of delay of drive signal E1 delay (this is the operating time of number operation down) that enables, enable drive signal E3 by this in receiving the drive signal E1 that enables.Buffer 18b takes a sample to rolling average voltage level Lma in response to the drive signal E3 that enables, to obtain blank voltage level L_blanking.
Limiting voltage level computing circuit 20 is according to top voltage level L_synctip and blank voltage level L_blanking find out limiting voltage level T2 synchronously.For instance, comprise the arithmetic element with adder 20a and multiplier 20b in the limiting voltage level computing circuit 20, its intermediate level according to blank voltage level L_blanking and synchronous top voltage level L_synctip obtains limiting voltage level T2.
Back-end processing circuit 22 is in order in response to low SNR control signal S1; Optionally limiting voltage level T2 is carried out low frequency filtering operation, and optionally with the limiting voltage level after limiting voltage level T2 and the low-pass filtering operation as output violent change voltage level L_slicer.For instance, when low SNR control signal S1 corresponds to logical value 1 (promptly being to judge that input signal of video signal Vs satisfies low SNR condition), back-end processing circuit 22 accordingly with the limiting voltage level after the low-pass filtering operation as output violent change voltage level L_slicer; When low SNR control signal S1 corresponds to logical value 0 (promptly being to judge that input signal of video signal Vs does not satisfy low SNR condition), back-end processing circuit 22 accordingly with limiting voltage level T2 as output violent change voltage level L_slicer.For instance, back-end processing circuit 22 can low pass filter 22a, multiplexer 22b and buffer 22c realize.
In view of the above, the clip level calculation element 1 of present embodiment can optionally export the limiting voltage level after the low-pass filtering operation or not carry out the limiting voltage level of low-pass filtering operation with reference to the condition whether input signal of video signal Vs satisfies low SNR.
Second embodiment
The clip level calculation element of present embodiment is used and is relevant to the signal deteching circuit that disturbs (Co-channel Interference) frequently when the same frequency that the input signal of video signal corresponds to varying strength disturbs, to fit property ground and calculate clip level with different arithmetic operations.
Please with reference to Fig. 4, it illustrates the clip level calculation element according to second embodiment of the invention.What the clip level calculation element 3 of present embodiment was different with the clip level calculation element of first embodiment is in wherein more comprising in order to signal deteching circuit 33 that detects the same frequency interference cases of importing signal of video signal Vs and the control circuit 31 that is controlled by signal deteching circuit 33.
Please with reference to Fig. 5, it illustrates the detailed block diagram of the signal deteching circuit 33 that is Fig. 4.Say that further signal deteching circuit 33 comprises arithmetic element 33a, comparing unit 33b, 33d, counting unit 33c and sequential control unit 33e.Arithmetic element 33a finds out the horizontal synchronization amplitude A_synctip of synchronous top voltage level L_synctip.For instance; Comprise minimum value search unit 320, maximum search unit 319, buffer 323,325, adder 327, low pass filter 329 and multiplier 332 among the arithmetic element 33a; It is in order to finding out the amplitude size Sw of synchronous top voltage level L_synctip with reference to the difference of the maximum of synchronous top voltage level L_synctip and minimum value, and produces horizontal synchronization amplitude A_synctip according to this amplitude size behind the ranking operation.
Whether A_synctip is greater than synchronous altitude signal SH for comparing unit 33b determined level sync amplitude value; If the same frequency interference cases that signal of video signal Vi is imported in expression this moment is serious, so comparing unit 33b provides the selection signal F3 that corresponds to first level (for example being the selection signal F1 that corresponds to logical value 1) accordingly; If not, it is slight that the same frequency disturbed condition of signal of video signal Vi is imported this moment in expression, and comparing unit 33b provides the selection signal F3 that corresponds to second level (for example being the selection signal F3 that corresponds to logical value 0) accordingly.
Counting unit 33c will judge that in response to first level of selecting signal F3 parameter Pcci increases progressively 1, and will judge that in response to second level of selecting signal F3 parameter Pcci successively decreases 1.For instance, the counting unit 12c among the counting unit 33c and first embodiment in the signal deteching circuit 12 has approaching circuit structure and operation, in this, and no longer it is given unnecessary details.
Comparing unit 33d is in the numerical value of judging parameter Pcci during greater than critical value M2, judges that input signal of video signal Vi satisfies with disturbed condition frequently, and triggers accordingly with Interference Control signal S2 frequently.The comparing unit 12d that disclosed in the signal deteching circuit 12 in first embodiment; Comparing unit 33d in the signal deteching circuit 33 also for example is sluggish comparing unit; Beginning output corresponds to the same frequency Interference Control signal S2 that enables level (for example being logical value 1) when being used to judge parameter Pcci greater than critical value M2 (promptly being to judge that input signal of video signal Vs satisfies with disturbed condition frequently), and beginning output corresponds to the same frequency Interference Control signal S2 of disable level (for example being logical value 0) when judging parameter Pcci less than critical value 0 (promptly being to judge that input signal of video signal Vs does not satisfy with disturbed condition frequently); Wherein critical value M2 is greater than numerical value 0.
The size of more blank voltage level L_blanking of comparing unit 31a and the blank voltage level L_blanking_d1 of last pen; And when L_blanking_d1 and the blank voltage level _ blanking_d1 of last pen are greater than blank voltage level L_blanking during greater than the blank voltage level of last pen, control signal C10 that enables and the control signal C11 that enables are provided respectively in blank voltage level L_blanking.For instance, comparing unit 31a can realize by comparator 401 and 403.
Comparing unit 31b compares the size of synchronous altitude signal SH and last synchronous altitude signal SH_d1; And when synchronous altitude signal SH is multiplied by weighting parameters R3 greater than last synchronous altitude signal SH_d1 and synchronous altitude signal SH when being multiplied by weighting parameters R4, the control signal C13 and the C15 that enable are provided respectively greater than last synchronous altitude signal SH_d1.For instance, comparing unit 31b can multiplier 406,409, comparator 414 and 432 realizes.
Comparing unit 31c compares the size of synchronous altitude signal SH and last synchronous altitude signal SH_d1; And when last synchronous altitude signal SH_d1 is multiplied by weighting parameters R3 greater than synchronous altitude signal SH and last synchronous altitude signal SH_d1 when being multiplied by weighting parameters R4, the control signal C12 and the C14 that enable are provided respectively greater than synchronous altitude signal SH.For instance, comparing unit 31c can multiplier 423,426, comparator 411 and 429 realizes.
When with Interference Control signal S2 frequently for enable and control signal C11 for enabling (promptly being that blank voltage level L_blanking is higher than last blank voltage level L_blanking_d1) and control signal C13 when enabling (promptly be synchronous altitude signal SH be higher than last synchronous altitude signal SH_d be multiplied by weighting parameters R3), control circuit 31d enables this and organizes the status signal B2 in status signal.
When being disable and control signal C10 with Interference Control signal S2 frequently for enabling (promptly being that the blank voltage level L_blanking_d1 of last pen is higher than blank voltage level L_blanking) and control signal C14 when enabling (promptly be last synchronous altitude signal SH_d be higher than synchronous altitude signal SH be multiplied by weighting parameters R4), control circuit 31d enables this and organizes the status signal C1 in status signal.
When this is disable and control signal C11 for enabling (promptly being that blank voltage level L_blanking is higher than the blank voltage level L_blanking_d1 of last pen) and control signal C15 when enabling (promptly be synchronous altitude signal SH be higher than last synchronous altitude signal SH_d be multiplied by weighting parameters R4) with Interference Control signal S2 frequently, control circuit 31d enables this and organizes the status signal C2 in status signal.
For instance, logical block 31d can and door (And Gate) 440,441,442,443 and inverse gate (NotGate) 420 realize.
In the present embodiment, same frequency Interference Control signal S2 and status signal B1, B2, C1 and C2 that signal deteching circuit 33 and control circuit 31 are produced are provided to each sub-circuit in the limiting voltage calculation element 3, come it is carried out corresponding control operation.
Right property control to back-end processing circuit 42
Please once more with reference to Fig. 4.In an example, more comprise logical block 42d in the back-end processing circuit 42, it produces the temporary operation that drive signal E4 drives buffer 42c in order to reference state signal B2, C1 and C2.Further, when logical block 42d was disable in status signal B2, C1 and C2, reference columns update signal Slu enabled drive signal E4, and in status signal B2, C1 and C2 wherein part or all be when enabling, disable drive signal E4.In view of the above, when the state of status signal B2, C1 and C2 arbitrary indication wherein took place, drive signal E4 was a disable, with the temporary operation of disable buffer 42c, with the renewal operation of disable clip level L_slicer.And be when not taking place at the state of status signal B2, C1 and C2 indication, for enabling, 42c upgrades clip level L_slicer to drive signal E4 accordingly with the driving buffer when row update signal Slu enables.
Right property control to limiting voltage electrical level computing circuit 40
Please once more with reference to Fig. 4.In an example, more comprise logical block 40c, buffer 40d and multiplexer 40e in the limiting voltage electrical level computing circuit 40.Buffer 40 is taken a sample to the blank voltage level L_blanking of blank voltage value circuit 38 outputs in response to drive signal E5, to provide last pen blank voltage level L_blanking_d1.
For instance, logical block 40c can or door OR2, inverse gate NOT2 and and a door AND2 realize.
Right property control to synchronous altitude signal computing circuit 44
Please once more with reference to Fig. 4.In an example; Synchronous altitude signal computing circuit 44 in the clip level calculation element 3 comprises buffer 44d; It is taken a sample in order to the synchronous altitude signal SH that adder 44a and absolute value value device 44b are produced, and obtains last synchronous altitude signal SH_d with sampling.Status signal B1 for enable or status signal B2 when enabling, present blank voltage level L_blanking and be unreliable because serious same frequency disturbs probably according to the synchronous altitude signal SH that its reckoning obtains.In view of the above; Synchronous altitude signal computing circuit 44 for example comprises the logical block 44c similar with logical block 40c; It is in order to being under the situation about enabling at status signal B1 or B2; Produce the drive signal E5 ' of disable, avoid buffer 44d to carry out sampling operation by this to insecure synchronous altitude signal SH.
Right property control to synchronous top voltage value circuit 36 bags
Please once more with reference to Fig. 4.In an example, top voltage value circuit 36 comprises minimum value search unit 36a, buffer 36b and logical block 36c synchronously.Minimum value is searched unit 36a and when finding out the minimum value of rolling average voltage level Lma in operating period, is enabled M signal E1.Buffer 36b takes a sample to rolling average voltage level Lma in response to the drive signal E2 that enables, to obtain synchronous top voltage level L_synctip.
The clip level calculation element of previous embodiment of the present invention is provided with signal deteching circuit, when hanging down the SNR conditioned disjunction with the frequency disturbed condition in order to satisfy at the input signal of video signal, fits its calculating operation to clip level of property ground change.In view of the above, compared to traditional clip level counting circuit, the clip level calculation element of previous embodiment of the present invention have can be at the SNR of signal of video signal lower or its receive with under the situation about disturbing frequently, produce the advantage of the higher clip level of accuracy effectively.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is when being as the criterion with what claim defined.
Claims (14)
1. clip level calculation element, in order to find out a clip level of an input signal of video signal, this clip level calculation element comprises:
Whether one first signal deteching circuit should satisfy a low signal noise than condition by the input signal of video signal, when this input signal of video signal satisfied this low signal noise than condition, this first signal deteching circuit enabled a low signal noise and compares control signal in order to judge;
One rolling average counting circuit is in order to find out a rolling average voltage level of this input signal of video signal;
One synchronous top voltage value circuit is in order to find out a synchronous top voltage level of a synchronous top temporal information and this input signal of video signal;
One blank voltage value circuit is in order to find out a blank voltage level of a blank time information and this input signal of video signal with reference to this synchronous top temporal information;
One limiting voltage level computing circuit is in order to according to this synchronous top voltage level and should find out a limiting voltage level by the blank voltage level; And
One back-end processing circuit, in order in response to this low signal noise than control signal, optionally this limiting voltage level is carried out low frequency filtering operation.
2. limiting voltage calculation element as claimed in claim 1 is characterized in that, more comprises:
Whether one secondary signal testing circuit should satisfy together disturbed condition frequently by the input signal of video signal in order to judge, when this input signal of video signal satisfies should be with disturbed condition frequently the time, this secondary signal testing circuit enables together Interference Control signal frequently.
3. limiting voltage calculation element as claimed in claim 2 is characterized in that, this synchronous top voltage value circuit comprises:
One minimum value is searched the unit, enables a M signal when being used to find out the minimum value of this rolling average voltage level;
One buffer is taken a sample to this rolling average voltage level in response to a drive signal that enables, to obtain this synchronous top voltage level; And
One logical block; Being used to this is that a disable or a synchronous gate signal are to enable this drive signal according to this M signal that enables when enabling with Interference Control signal frequently, and in this with frequency Interference Control signal for enabling and this sync gate signal this drive signal of disable when being disable.
4. limiting voltage calculation element as claimed in claim 2 is characterized in that, more comprises:
One control circuit, in order to according to should with Interference Control signal frequently, this blank voltage level, last pen should the blank voltage level, the numerical relation of a synchronous altitude signal and last this synchronous altitude signal produces one group of status signal.
5. limiting voltage calculation element as claimed in claim 4 is characterized in that:
Should the blank voltage level and this synchronous altitude signal when being higher than last this synchronous altitude signal for enabling and should the blank voltage level being higher than last pen when this with Interference Control signal frequently, this control circuit enables one first status signal in this group status signal;
When this is disable and last pen when should the blank voltage level being higher than this blank voltage level and last this synchronous altitude signal of pen and being higher than this synchronous altitude signal with Interference Control signal frequently, this control circuit enables one second status signal in this group status signal;
When this with Interference Control signal frequently be disable and should the blank voltage level be higher than last pen should the blank voltage level and this synchronous altitude signal when being higher than last this synchronous altitude signal of pen, this control circuit enables the third state signal in this group status signal.
6. limiting voltage calculation element as claimed in claim 5 is characterized in that, this back-end processing circuit comprises:
One low-pass filter unit is in order to carrying out low-pass filtering operation to this limiting voltage level, to obtain this limiting voltage level behind the LPF;
One multiplexer, receive and in response to this low signal noise than control signal optionally export behind this limiting voltage level and the LPF this limiting voltage level one of them;
One buffer, in response to a drive signal store this multiplexer output this limiting voltage level and this limiting voltage level behind the LPF one of them; And
One logical block; Be used to this first, this second and this third state signal when being disable; Enable this drive signal with reference to a row update signal, and in this first to this third state signal wherein part or all be this drive signal of disable when enabling.
7. limiting voltage calculation element as claimed in claim 4 is characterized in that:
When this with Interference Control signal frequently for enabling and last pen when should the blank voltage level being higher than this blank voltage level and last this synchronous altitude signal and being higher than this synchronous altitude signal, this control circuit enables the four condition signal in this group status signal; And
Should the blank voltage level and this synchronous altitude signal when being higher than last this synchronous altitude signal for enabling and should the blank voltage level being higher than last pen when this with Interference Control signal frequently, this control circuit enables one first status signal in this group status signal.
8. limiting voltage calculation element as claimed in claim 7 is characterized in that, this limiting voltage level computing circuit comprises:
One buffer is taken a sample to this blank voltage level of this blank voltage value circuit output in response to a drive signal, should the blank voltage level so that last pen to be provided;
One multiplexer, receive and in response to this four condition signal-selectivity ground output should the blank voltage level and last should the blank voltage level one of them; And
One arithmetic element, in order to this blank voltage level of providing according to this multiplexer and last pen should the blank voltage level one of them obtain this limiting voltage level with this synchronous top voltage level.
9. limiting voltage calculation element as claimed in claim 8 is characterized in that, this limiting voltage level computing circuit comprises:
One logical block, be used to this first and this four condition signal when being disable, enable this drive signal with reference to a row update signal, and in this first and this four condition signal wherein part or all be this drive signal of disable when enabling.
10. limiting voltage calculation element as claimed in claim 7 is characterized in that, more comprises:
One synchronous altitude signal computing circuit comprises:
One arithmetic element is in order to this synchronous top voltage level and should subtract each other the computing that takes absolute value by the blank voltage level, to find out a synchronous altitude signal;
One buffer is taken a sample to this synchronous altitude signal of this arithmetic element output in response to a drive signal, so that last this synchronous altitude signal of pen to be provided; And
One logical block, be used to this first and this four condition signal when being disable, enable this drive signal with reference to a row update signal, and in this first and this four condition signal wherein part or all be this drive signal of disable when enabling.
11. limiting voltage calculation element as claimed in claim 2 is characterized in that, this secondary signal testing circuit comprises:
One arithmetic element is in order to find out a horizontal synchronization amplitude of this synchronous top voltage level;
One first comparing unit is in order to judge that whether this horizontal synchronization amplitude is greater than a synchronous altitude signal; If this comparing unit provides the selection signal that corresponds to one first level; If not, this comparing unit provides the selection signal that corresponds to one second level;
One counting unit judges that with one parameter increases progressively 1 in response to this first level of this selection signal, and should judge in response to this second level of this selection signal that parameter successively decreased 1; And
One second comparing unit, the numerical value that is used to this judgement parameter judge that this input signal of video signal satisfies during greater than a critical value should be with disturbed condition frequently, and triggers frequency Interference Control signal together accordingly.
12. limiting voltage calculation element as claimed in claim 11 is characterized in that, this secondary signal testing circuit more comprises:
One sequential control unit upgrades clock signal in order to provide one with reference to a row update signal, to control one section reproducting periods this horizontal synchronization amplitude of replacement in the every interval of this secondary signal testing circuit and this judgement parameter.
13. limiting voltage calculation element as claimed in claim 2 is characterized in that, this blank voltage value circuit comprises:
Once counting unit postpones one period time of delay in response to this drive signal, to enable one second drive signal;
One buffer is taken a sample to this rolling average voltage level in response to this second drive signal that enables, to obtain this blank voltage level.
14. limiting voltage calculation element as claimed in claim 1 is characterized in that, this first signal deteching circuit comprises:
One arithmetic element in order to finding out a radio-frequency component signal of this input signal of video signal, and is carried out absolute value rolling average and ranking operation operation to this radio-frequency component signal, to find out a noise strength signal;
One first comparing unit is in order to judge that whether this noise strength signal is greater than a synchronous altitude signal; If this comparing unit provides the selection signal that corresponds to one first level; If not, this comparing unit provides the selection signal that corresponds to one second level;
One counting unit judges that with one parameter increases progressively 1 in response to this first level of this selection signal, and should judge in response to this second level of this selection signal that parameter successively decreased 1; And
One second comparing unit, the numerical value that is used to this judgement parameter judge that this input signal of video signal satisfies this low signal noise than condition during greater than a critical value, and trigger this low signal noise accordingly and compare control signal.
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| CN101202850A (en) * | 2006-12-14 | 2008-06-18 | 联詠科技股份有限公司 | Apparatus and method useful for horizontal synchronizing signal phase locking return circuit of television video signal |
| CN101409780A (en) * | 2007-10-10 | 2009-04-15 | 三洋电机株式会社 | Sync separation circuit |
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| CN1079857A (en) * | 1992-03-11 | 1993-12-22 | 汤姆森消费电子有限公司 | Auxiliary video data slicer |
| CN1503965A (en) * | 2001-01-10 | 2004-06-09 | 三菱电机株式会社 | Color image display device |
| CN101202850A (en) * | 2006-12-14 | 2008-06-18 | 联詠科技股份有限公司 | Apparatus and method useful for horizontal synchronizing signal phase locking return circuit of television video signal |
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