CN102710239A - Broadband orthogonal signal generator - Google Patents
Broadband orthogonal signal generator Download PDFInfo
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- CN102710239A CN102710239A CN2012101914275A CN201210191427A CN102710239A CN 102710239 A CN102710239 A CN 102710239A CN 2012101914275 A CN2012101914275 A CN 2012101914275A CN 201210191427 A CN201210191427 A CN 201210191427A CN 102710239 A CN102710239 A CN 102710239A
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Abstract
The invention discloses a broadband orthogonal signal generator, which comprises a phase shifter, an I-path amplitude adjuster and a Q-path amplitude adjuster, wherein positive and negative input signals are transmitted to an I+ input end and an I- input end of the I-path amplitude adjuster respectively by a first resistor and a third resistor of the phase shifter and then transmitted to a Q+ input end and a Q- input end of the Q-path amplitude adjuster after being subjected to phase shifting by the phase shifter; and the I-path amplitude adjuster and the Q-path amplitude adjuster are respectively used for carrying out amplitude adjustment on the received I-path signals and Q-path signals under the control of a reference voltage to obtain I/O outputs with same amplitudes. The broadband orthogonal signal generator disclosed by the invention achieves the purpose of acquiring orthogonal signals with better orthogonality in a broader bandwidth.
Description
Technical field
The present invention relates to a kind of orthogonal signalling generator, particularly relate to a kind of wideband orthogonal signal generator.
Background technology
In the modern communications, receiver uses Direct Conversion or Low Medium Frequency technology usually, and this needs the local oscillation signal of two quadratures usually.
Three kinds of methods that are usually used in obtaining homophase (I) and quadrature (Q) signal are arranged, that is: use phase shifter; Use and remove two-divider and use coupled oscillator, the wherein modal phase shifter that just is to use.
Fig. 1 produces the circuit diagram of the orthogonal signalling generator of orthogonal signalling for using phase shifter in the prior art.As shown in Figure 1, this quadrature generator is done phase shift through resistance R 1 and capacitor C 1, through buffer, obtains homophase (I) and quadrature (Q) signal Vout_ip, Vout_qp, Vout_in and Vout_qn, according to formula:
For in wider bandwidth, obtaining good quadrature accuracy and obtaining good image rejection ratio (IRR), adopt multistage multiphase filter usually, Fig. 2 is the circuit diagram of the orthogonal signalling generator of the multistage multiphase filter of available technology adopting.In Fig. 2, the orthogonal signalling generator has adopted multistage RC filter (R1 and C1, R2 and C2 ... Rn and Cn); Though there is following other problems in the problem that it can solve the narrow bandwidth among Fig. 1: every grade of meeting is introduced the 3dB loss because of limit and load effect, simultaneously; For keeping required amplitude; Must need extra amplifier, thereby make the waste of band internal power, power consumption is bigger.
Summary of the invention
For overcoming the deficiency that above-mentioned prior art exists, the present invention's purpose is to provide a kind of wideband orthogonal signal generator, and the orthogonal signalling of its generation can obtain better orthogonality in wider bandwidth.
For reaching above-mentioned and other purpose; The present invention provides a kind of wideband orthogonal signal generator; Comprise phase shifter, in addition, this wideband orthogonal signal generator also comprises I road amplitude adjuster and Q road amplitude adjuster; I+, I-input that wherein positive and negative input signal is delivered to this I road amplitude adjuster through first resistance and the 3rd resistance of this phase shifter respectively; After this phase shifter phase shift, deliver to Q+, the Q-input of this Q road amplitude adjuster, this I road amplitude adjuster and this Q road amplitude adjuster are carried out the amplitude adjustment to received I road signal and Q road signal respectively under the control of reference voltage, to obtain the I/Q output of equal amplitude.
Further, this amplitude adjuster comprises:
The amplitude detection circuit is used for the alternating voltage on I road/Q road is become dc control signal;
Reference voltage circuit is used for that this reference voltage displacement is become suitable comparison circuit and uses reference voltage to export also and the input of comparison circuit isolation;
Comparison circuit is used for the output of this reference voltage circuit and the output of this amplitude detection circuit are compared, and exports the bias current that a control signal removes to control buffer amplifier circuit; And
Buffer amplifier circuit will pass through the orthogonal signalling amplitude of carrying out of this phase shifter and amplify under the control of this control signal, make the amplitude output signal on I road and Q road equate.
Further; This amplitude detection circuit comprises first detection tube, second detection tube, mirror-image constant flow source and load circuit; This first detection tube, second detection tube are connected with the output detection to this buffer amplifier circuit with the output of first difference, the output of second difference of this buffer amplifier circuit respectively, on this load circuit, form detecting circuit.
Further, this first detection tube and second detection tube are the NMOS pipe, and its grid is connected with this first difference output, the output of second difference through a capacitance respectively, and drain electrode connects supply voltage, and source electrode is connected to this mirror-image constant flow source and this load circuit.
Further; This load circuit comprises the NMOS pipe and second electric capacity; The one NMOS pipe is formed the RC load with second electric capacity; Be connected to the source electrode of this first detection tube and this second detection tube, NMOS pipe is formed the source electrode that mirror-image constant flow source is connected to this first detection tube and this second detection tube with the 12 NMOS pipe.
Further; This reference voltage circuit comprises the 5th NMOS pipe and the 2nd NMOS pipe; The 5th NMOS tube grid connects this reference voltage, and drain electrode connects supply voltage, and source electrode connects the drain electrode of the 2nd NMOS pipe; The 2nd NMOS pipe is formed mirror-image constant flow source as the load of the 5th NMOS pipe with the 12 NMOS pipe.
Further; This comparison circuit comprises the first comparator amplifier tube, second comparator amplifier tube and the mirror-image constant flow source; This first comparator amplifier tube is connected in the output of this reference voltage circuit to obtain reference voltage output; This second comparator amplifier tube is connected in the output of this amplitude detection circuit to obtain this detecting circuit, and this first comparator amplifier tube and the second comparator amplifier tube amplify the difference of this reference voltage output and this detecting circuit, export this control signal.
Further; This first comparator amplifier tube and this second comparator amplifier tube are the NMOS pipe, and this first comparator amplifier tube grid connects the 5th NMOS pipe source electrode to obtain this reference voltage output, and drain electrode connects mirror-image constant flow source; Source electrode is through a current source ground connection; This second comparator amplifier tube grid connects this detecting circuit, and drain electrode connects mirror-image constant flow source, and source electrode is through a current source ground connection.
Further; This buffer amplifier circuit comprises constant-current source bias circuit and buffer amplifier; This buffer amplifier has two inputs, and the I road signal or the Q road signal that are used to receive after the phase shift amplify its amplitude of carrying out, and form this first difference output and the output of this second difference; This constant-current source bias circuit links to each other with this second comparator amplifier tube drain electrode, with under the control of this control signal, through the gain of this buffer amplifier of Control current control.
This buffer amplifier comprises the tenth NMOS pipe and the 11 NMOS pipe; The tenth NMOS pipe and the 11 NMOS tube grid connect I road signal or Q road signal after the phase shift through a capacitance respectively; Drain electrode is connected to supply voltage through load respectively and exports this first difference output and the output of this second difference, and source electrode all is connected to this constant-current source bias circuit.
Compared with prior art, a kind of wideband orthogonal signal generator of the present invention obtains quadrature phase through RC network, utilizes amplitude adjuster to obtain the I/Q output of equal amplitude, has reached the purpose that in wider bandwidth, obtains better orthogonality.
Description of drawings
Fig. 1 produces the circuit diagram of the orthogonal signalling generator of orthogonal signalling for using phase shifter in the prior art;
Fig. 2 is the circuit diagram of the orthogonal signalling generator of the multistage multiphase filter of available technology adopting;
Fig. 3 is the circuit diagram of the preferred embodiment of a kind of wideband orthogonal signal generator of the present invention;
Fig. 4 is the circuit diagram of amplitude adjuster in the preferred embodiment of the present invention;
Fig. 5 and Fig. 6 are respectively the analogous diagram of the orthogonal signalling generator of prior art at 2.4GHz and 2GHz;
Fig. 7 and Fig. 8 are respectively the analogous diagram of the present invention's wideband orthogonal signal generator at 2.4GHz and 2GHz.
Fig. 9 is the output timing diagram of the orthogonal signalling generator of prior art at 2GHz;
Figure 10 is the output timing diagram of the present invention's wideband orthogonal signal generator at 2GHz
Embodiment
Below through specific instantiation and accompanying drawings execution mode of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can implement or use through other different instantiation, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
Fig. 3 is the circuit diagram of the preferred embodiment of a kind of wideband orthogonal signal generator of the present invention.As shown in Figure 3, a kind of wideband orthogonal signal generator of the present invention comprises phase shifter 301, I road amplitude adjuster 302 and Q road amplitude adjuster 303.
Wherein, positive and negative input signal Vin+, Vin-deliver to I+, the I-input of I road amplitude adjuster 302 respectively respectively through first resistance R 1, the 3rd resistance R 3 of phase shifter 301; Positive and negative input signal Vin+, Vin-be respectively through the first capacitor C 1-of phase shifter 301, the second resistance R 2-, second capacitor C 2,4 phase shifts of the 3rd capacitor C 3-the 4th resistance R 4-the 4th capacitor C, exports Q+, the Q-input of Q road amplitude adjuster 303 respectively at the common port of first capacitor C 1 and second resistance R 2, the 3rd capacitor C 3 and the 4th resistance R 4; I road amplitude adjuster 302 is carried out the amplitude adjustment to received I road signal and Q road respectively with Q road amplitude adjuster 303, to obtain the I/Q output of equal amplitude.
Fig. 4 is the circuit diagram of amplitude adjuster in the preferred embodiment of the present invention.As shown in Figure 4, the amplitude adjuster among the present invention comprises amplitude detection circuit 401, reference voltage circuit 402, comparison circuit 403 and buffer amplifier circuit 404.
Wherein amplitude detection circuit 401 is used for the alternating voltage on I road/Q road is become dc control signal; Reference voltage circuit 402 be used for reference voltage Vref displacement with input become reference voltage output that suitable comparison circuit 403 uses and with the input isolation of comparison circuit 403; Comparison circuit 403 is used for the output of reference voltage circuit 402 and 401 outputs of amplitude detection circuit are compared, and exports the bias current that a control signal removes to control buffer amplifier circuit 404, thereby reaches its gain of control; Buffer amplifier circuit 404 will pass through orthogonal signalling (like the VIP/VIN) amplitude of carrying out of phase-shift network and amplify, and make the amplitude output signal on I road and Q road equate.
In preferred embodiment of the present invention; Amplitude detection circuit 401 comprises the first detection tube M3, the second detection tube M4, mirror-image constant flow source and load circuit; Wherein the first detection tube M3 is connected with first difference output VON of buffer amplifier circuit 404; Upper half with to first difference output VON carries out detection, and the second detection tube M4 exports VOP with second difference of buffer amplifier circuit 404 and is connected, being that the lower half of VON carries out detection to half cycle on the opposite signal VOP of VON; The first detection tube M3 and the second detection tube M4 promptly carry out full-wave detection to the output of buffer amplifier circuit 404 altogether, on load circuit, form detecting circuit VD.Specifically; The first detection tube M3 and the second detection tube M4 are the NMOS pipe; Its grid is connected with first difference output VON, second difference output VOP of buffer amplifier circuit 404 through capacitance C0 and C1 respectively, and drain electrode connects supply voltage, and source electrode is connected to mirror-image constant flow source and load circuit; In preferred embodiment of the present invention; The one NMOS pipe M1 and the 12 NMOS pipe M12 form mirror-image constant flow source, and load circuit comprises that NMOS pipe M1 and second capacitor C, 2, the one NMOS pipe M1 and second capacitor C 2 form the RC load; Be connected to the source electrode of the first detection tube M3 and the second detection tube M4, promptly the first detection tube M3 and the second detection tube M4 form formation detecting circuit VD in the RC load at the NMOS pipe M1 and second capacitor C 2.Preferable, the grid of the first detection tube M3 and the second detection tube M4 also is connected to a biasing circuit respectively, and the first detection tube M3 is connected to bias voltage VB1 through a resistance R 0, and the second detection tube M4 is connected to bias voltage VB1 through resistance R 1.
Reference voltage circuit 402 is used for converting reference voltage Vref into reference voltage output VR; It comprises the 5th NMOS pipe M5 and the 2nd NMOS pipe M2; The 5th NMOS tube grid connects reference voltage Vref, and drain electrode connects supply voltage, and source electrode connects the 2nd NMOS pipe M2 drain electrode; The 2nd NMOS pipe M2 is as the load of the 5th NMOS pipe M5, and itself and the 12 NMOS pipe M12 form mirror-image constant flow source.
Comparison circuit 403 comprises the first comparator amplifier tube M6, second comparator amplifier tube M7 and the mirror-image constant flow source, and the first comparator amplifier tube M6 is connected in the output of reference voltage circuit 402 to obtain reference voltage output VR, and the second comparator amplifier tube M7 is connected in the output of amplitude detection circuit 401 to obtain detecting circuit VD; The first comparator amplifier tube M6 and the second comparator amplifier tube M7 amplify the difference of VR and VD; In preferred embodiment of the present invention, the first comparator amplifier tube M6 and the second comparator amplifier tube M7 are the NMOS pipe, and the M6 grid connects the M5 source electrode to obtain reference voltage output VR; Drain electrode connects mirror-image constant flow source; Source electrode is through a current source ground connection, and the M7 grid connects the M3/M4 source electrode to obtain detecting circuit VD, and drain electrode connects mirror-image constant flow source; Source electrode is through a current source ground connection; VR and VD difference are amplified through M6/M7, and from M7 drain electrode output VC.At this, mirror-image constant flow source is made up of the 8th PMOS pipe and the 9th PMOS pipe.
Buffer amplifier circuit 404 comprises constant-current source bias circuit I 1 and buffer amplifier; Wherein buffer amplifier has two inputs; The I road signal VIP/VIN or the Q road signal VQP/VQN that are used to receive after the phase shift amplify its amplitude of carrying out; Forming first difference output VON and second difference output VOP, in preferred embodiment of the present invention, is example with the I road then.Buffer amplifier comprises the tenth NMOS pipe M10 and the 11 NMOS pipe M11; The tenth NMOS pipe M10 and the 11 NMOS pipe M11 grid meet VIP/VIN through a capacitance respectively, and at this, the tenth NMOS pipe M10 meets VIP through capacitance C3; The 11 NMOS pipe M11 meets VIN through capacitance C4; Preferable, the tenth NMOS pipe M10 and the 11 NMOS pipe M11 grid also can connect biasing circuit, meet bias voltage VB2 like the tenth NMOS pipe M10 grid through biasing resistor R2; The 11 NMOS pipe M11 meets bias voltage VB2 through biasing resistor R3; The tenth NMOS pipe M10 and the 11 NMOS pipe M11 drain electrode are connected to supply voltage through load z1 and z2 respectively and export first difference output VON and second difference output VOP, and source electrode all is connected to constant-current source bias circuit I 1, and constant-current source bias circuit I 1 links to each other with second comparator amplifier tube M7 drain electrode; With under the control of output VC; Through the gain of Control current control buffer amplifier, thus the amplitude of first difference output VON and second difference output VOP control by reference voltage Vref, Vref can obtain equal amplitude to the I/Q adjustment.
Fig. 5 and Fig. 6 are the analogous diagram of the orthogonal signalling generator of prior art at 2.4GHz and 2GHz.It is thus clear that this orthogonal signalling generator obtains orthogonal signalling when 2.4GHz, when 2GHz, then can't obtain orthogonal signalling, so there is the problem of narrow bandwidth in this orthogonal signalling generator.Fig. 7 and Fig. 8 are respectively the analogous diagram of the present invention's wideband orthogonal signal generator at 2.4GHz and 2GHz; Fig. 9 is the output timing diagram of the orthogonal signalling generator of prior art at 2GHz; Figure 10 then is the output timing diagram of the present invention's wideband orthogonal signal generator at 2GHz, and visible, the present invention's wideband orthogonal signal generator no matter is at 2.4GHz or 2GHz all can obtain orthogonal signalling; I, Q two-way amplitude equal phase difference are 90 degree, can in wider bandwidth, obtain better orthogonality.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, rights protection scope of the present invention should be listed like claims.
Claims (10)
1. wideband orthogonal signal generator; Comprise phase shifter; It is characterized in that: this wideband orthogonal signal generator also comprises I road amplitude adjuster and Q road amplitude adjuster; I+, I-input that wherein positive and negative input signal is delivered to this I road amplitude adjuster through first resistance and the 3rd resistance of this phase shifter respectively; After this phase shifter phase shift, deliver to Q+, the Q-input of this Q road amplitude adjuster, this I road amplitude adjuster and this Q road amplitude adjuster are carried out the amplitude adjustment to received I road signal and Q road signal respectively under the control of reference voltage, to obtain the I/Q output of equal amplitude.
2. wideband orthogonal signal generator as claimed in claim 1 is characterized in that, this amplitude adjuster comprises:
The amplitude detection circuit is used for the alternating voltage on I road/Q road is become dc control signal;
Reference voltage circuit is used for that this reference voltage displacement is become suitable comparison circuit and uses reference voltage to export also and the input of comparison circuit isolation;
Comparison circuit is used for the output of this reference voltage circuit and the output of this amplitude detection circuit are compared, and exports the bias current that a control signal removes to control buffer amplifier circuit; And
Buffer amplifier circuit will pass through the orthogonal signalling amplitude of carrying out of this phase shifter and amplify under the control of this control signal, make the amplitude output signal on I road and Q road equate.
3. wideband orthogonal signal generator as claimed in claim 2; It is characterized in that: this amplitude detection circuit comprises first detection tube, second detection tube, mirror-image constant flow source and load circuit; This first detection tube, second detection tube are connected with the output detection to this buffer amplifier circuit with the output of first difference, the output of second difference of this buffer amplifier circuit respectively, on this load circuit, form detecting circuit.
4. wideband orthogonal signal generator as claimed in claim 3; It is characterized in that: this first detection tube and second detection tube are the NMOS pipe; Its grid is connected with this first difference output, the output of second difference through a capacitance respectively; Drain electrode connects supply voltage, and source electrode is connected to this mirror-image constant flow source and this load circuit.
5. wideband orthogonal signal generator as claimed in claim 4; It is characterized in that: this load circuit comprises the NMOS pipe and second electric capacity; The one NMOS pipe is formed the RC load with second electric capacity; Be connected to the source electrode of this first detection tube and this second detection tube, NMOS pipe is formed the source electrode that mirror-image constant flow source is connected to this first detection tube and this second detection tube with the 12 NMOS pipe.
6. wideband orthogonal signal generator as claimed in claim 5; It is characterized in that: this reference voltage circuit comprises the 5th NMOS pipe and the 2nd NMOS pipe; The 5th NMOS tube grid connects this reference voltage, and drain electrode connects supply voltage, and source electrode connects the drain electrode of the 2nd NMOS pipe; The 2nd NMOS pipe is formed mirror-image constant flow source as the load of the 5th NMOS pipe with the 12 NMOS pipe.
7. wideband orthogonal signal generator as claimed in claim 6; It is characterized in that: this comparison circuit comprises the first comparator amplifier tube, second comparator amplifier tube and the mirror-image constant flow source; This first comparator amplifier tube is connected in the output of this reference voltage circuit to obtain reference voltage output; This second comparator amplifier tube is connected in the output of this amplitude detection circuit to obtain this detecting circuit; This first comparator amplifier tube and the second comparator amplifier tube amplify the difference of this reference voltage output and this detecting circuit, export this control signal.
8. wideband orthogonal signal generator as claimed in claim 7; It is characterized in that: this first comparator amplifier tube and this second comparator amplifier tube are the NMOS pipe, and this first comparator amplifier tube grid connects the 5th NMOS pipe source electrode to obtain this reference voltage output, and drain electrode connects mirror-image constant flow source; Source electrode is through a current source ground connection; This second comparator amplifier tube grid connects this detecting circuit, and drain electrode connects mirror-image constant flow source, and source electrode is through a current source ground connection.
9. wideband orthogonal signal generator as claimed in claim 8; It is characterized in that: this buffer amplifier circuit comprises constant-current source bias circuit and buffer amplifier; This buffer amplifier has two inputs; The I road signal or the Q road signal that are used to receive after the phase shift amplify its amplitude of carrying out, and form this first difference output and the output of this second difference; This constant-current source bias circuit links to each other with this second comparator amplifier tube drain electrode, with under the control of this control signal, through the gain of this buffer amplifier of Control current control.
10. wideband orthogonal signal generator as claimed in claim 8; It is characterized in that: this buffer amplifier comprises the tenth NMOS pipe and the 11 NMOS pipe; The tenth NMOS pipe and the 11 NMOS tube grid connect I road signal or Q road signal after the phase shift through a capacitance respectively; Drain electrode is connected to supply voltage through load respectively and exports this first difference output and the output of this second difference, and source electrode all is connected to this constant-current source bias circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210191427.5A CN102710239B (en) | 2012-06-11 | 2012-06-11 | Broadband orthogonal signal generator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210191427.5A CN102710239B (en) | 2012-06-11 | 2012-06-11 | Broadband orthogonal signal generator |
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| CN102710239A true CN102710239A (en) | 2012-10-03 |
| CN102710239B CN102710239B (en) | 2017-12-08 |
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| CN201210191427.5A Active CN102710239B (en) | 2012-06-11 | 2012-06-11 | Broadband orthogonal signal generator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104320204A (en) * | 2014-11-11 | 2015-01-28 | 中国电子科技集团公司第五十四研究所 | Local oscillator IQ signal phase and amplitude calibration device |
| US20220200781A1 (en) * | 2020-12-18 | 2022-06-23 | Intel Corporation | Wide-range inductor-based delay-cell and area efficient termination switch control |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964643B (en) * | 2009-07-22 | 2013-01-02 | 中国科学院微电子研究所 | Self-adaptive broadband quadrature phase-shift circuit and application thereof |
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2012
- 2012-06-11 CN CN201210191427.5A patent/CN102710239B/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104320204A (en) * | 2014-11-11 | 2015-01-28 | 中国电子科技集团公司第五十四研究所 | Local oscillator IQ signal phase and amplitude calibration device |
| US20220200781A1 (en) * | 2020-12-18 | 2022-06-23 | Intel Corporation | Wide-range inductor-based delay-cell and area efficient termination switch control |
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| CN102710239B (en) | 2017-12-08 |
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