CN102709328A - Array substrate, manufacturing method thereof, display panel and display device - Google Patents
Array substrate, manufacturing method thereof, display panel and display device Download PDFInfo
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- CN102709328A CN102709328A CN2012101677778A CN201210167777A CN102709328A CN 102709328 A CN102709328 A CN 102709328A CN 2012101677778 A CN2012101677778 A CN 2012101677778A CN 201210167777 A CN201210167777 A CN 201210167777A CN 102709328 A CN102709328 A CN 102709328A
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- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000013459 approach Methods 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 12
- 150000004706 metal oxides Chemical class 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 30
- 238000000034 method Methods 0.000 description 19
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000002207 thermal evaporation Methods 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
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- 239000011733 molybdenum Substances 0.000 description 2
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- 239000010937 tungsten Substances 0.000 description 2
- 206010034960 Photophobia Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000004070 electrodeposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate, a manufacturing method thereof, a display panel and a display device, belonging to the field of liquid crystal display. The manufacturing method comprises: forming an etching barrier layer on a substrate formed with an active layer, and etching a source electrode contact hole and a drain electrode contact hole, after adopting a first mask for photo-etching; forming a source electrode, a drain electrode and data lines on the substrate formed with the etching barrier layer, wherein the source electrode is connected with the active layer through the source electrode contact hole, and the drain electrode is connected with the active layer through the drain electrode contact hole; forming a passivation layer on the substrate formed with the source electrode, the drain electrode and the data lines, and etching a pixel electrode contact hole, after adopting the first mask for the photo-etching; and forming a pixel electrode on the substrate formed with the passivation layer, wherein the pixel electrode is connected with the drain electrode through the pixel electrode contact hole. According to the invention, the manufacturing cost of the array substrate can be decreased.
Description
Technical field
The present invention relates to field of liquid crystal display, relate in particular to a kind of array base palte, its manufacturing approach, display floater and display unit.
Background technology
The shortcoming of utilizing amorphous silicon (a-Si) thin-film transistor (TFT) to make TFT thin film transistor monitor be its electron mobility very low (<1cm
2/ V.S), a-Si is opaque at visible-range simultaneously, and light sensitivity is strong, so its range of application is restricted.Appearance along with new technology; Like Organic Light Emitting Diode (OLED) Display Technique, transparent liquid crystal Display Technique, drive circuit integrated glass technology (Gate Driver on Array; GOA) etc. progress into people's the visual field; Need thin film semiconductor material to have higher electron mobility, better amorphous state homogeneity, and can reduce threshold voltage (Vth) drift etc.
Metal oxide semiconductor films transistor (Oxide TFT; O-TFT) it is low that metal oxide semiconductor films has a depositing temperature; Electron mobility is high, is easy to etching, and transmitance is high in visible-range; And electron mobility does not depend on the particle size of film so, promptly has Vth homogeneity advantages of higher.
Fig. 1 is the structural representation of existing metal oxide thin-film transistor array base palte, and wherein, Fig. 1 b is the plane graph of array base palte, and Fig. 1 a is the A-A sectional view of Fig. 1 b.With reference to Fig. 1, said array base palte comprises: substrate 101; Be formed on gate electrode 102 and grid line on the substrate 101; Be formed on the gate insulation layer 103 on gate electrode 102 and the grid line; Be formed on the metal oxide active layer 104 on the gate insulation layer 103; Be formed on etching barrier layer on the active layer 104 (Etch Stop Layer, ESL) 105, source electrode 106, drain electrode 107 and data wire; Passivation layer 108 on source electrode 106, drain electrode 107 and the data wire is formed with via hole 109 on the passivation layer 108; Be formed on the pixel electrode 110 on the passivation layer 108, pixel electrode 110 is connected with drain electrode 107 through via hole 109.
The manufacturing process of above-mentioned Oxide-TFT array base palte is following: deposition grid metal level on substrate 101, make public with mask, and make gate electrode 102 through development, etching technics again; Deposit gate insulation layer 103 and metal oxide semiconductor layer above that successively, make public, make active layer 104 through development, etching technics again with mask; The deposited barrier layer material makes public with mask above that, makes etching barrier layer 105 through development, etching technics again; Sedimentary origin leaks metal level above that, makes public with mask, makes source electrode 106, drain electrode 107 through development, etching technics again; Deposit passivation layer 108 above that, make public with mask, make via hole 109 through development, etching technics again; The deposit transparent electrode layer makes public with mask above that, makes pixel electrode 110 through development, etching technics again.
Can find out that the manufacture process of above-mentioned array base palte has comprised composition technology six times, each composition technology is all used a different mask, causes the manufacturing cost of this array base palte higher.
Summary of the invention
Technical problem to be solved by this invention provides a kind of array base palte, its manufacturing approach, display floater and display unit, to reduce the manufacturing cost of array base palte.
For solving the problems of the technologies described above, the present invention provides technical scheme following:
A kind of array base palte comprises:
Be formed on the etching barrier layer on the substrate that is formed with active layer with source electrode contact hole and drain electrode contact hole;
Be formed on source electrode, drain electrode and data wire on the substrate that is formed with etching barrier layer, the source electrode is connected with active layer through source electrode contact hole, and drain electrode is connected with active layer through the drain electrode contact hole;
Be formed on the passivation layer with pixel electrode contact hole on the substrate that forms active electrode, drain electrode and data wire, said pixel electrode contact hole overlaps with the orthographic projection of said drain electrode contact hole on substrate in the orthographic projection on the substrate;
Be formed on the pixel electrode on the substrate that is formed with passivation layer, said pixel electrode is connected with drain electrode through the pixel electrode contact hole.
Above-mentioned array base palte wherein, also comprises:
Be formed on gate electrode and grid line on the substrate;
Be formed on the gate insulation layer on the substrate that is formed with gate electrode and grid line;
Be formed on the active layer on the gate insulation layer.
Above-mentioned array base palte, wherein: said active layer is the metal oxide active layer.
Above-mentioned array base palte, wherein: the orthographic projection of said pixel electrode contact hole on substrate is positioned at the residing zone of gate electrode.
Above-mentioned array base palte, wherein: said etching barrier layer all covers said substrate.
A kind of manufacturing approach of array base palte comprises:
Form etching barrier layer being formed with on the substrate of active layer, adopt first mask to carry out photoetching after, etch source electrode contact hole and drain electrode contact hole;
Be formed with formation source electrode, drain electrode and data wire on the substrate of etching barrier layer, the source electrode is connected with active layer through source electrode contact hole, and drain electrode is connected with active layer through the drain electrode contact hole;
Form passivation layer forming on the substrate of active electrode, drain electrode and data wire, adopt said first mask to carry out photoetching after, etch the pixel electrode contact hole;
Form pixel electrode being formed with on the substrate of passivation layer, said pixel electrode is connected with drain electrode through the pixel electrode contact hole.
Above-mentioned manufacturing approach wherein, also comprised before forming etching barrier layer:
On substrate, form gate electrode and grid line;
On the substrate that is formed with gate electrode and grid line, form gate insulation layer;
On gate insulation layer, form active layer.
Above-mentioned manufacturing approach, wherein: said active layer is the metal oxide active layer.
A kind of display floater comprises above-mentioned array base palte.
A kind of display unit comprises above-mentioned array base palte.
Compared with prior art, the invention has the beneficial effects as follows:
1, when the figure of figure that forms etching barrier layer and passivation layer, can use same mask, thereby reduce the quantity of mask, can reduce the manufacturing cost of array base palte;
2, the pixel electrode contact hole is formed on the gate electrode upper area, for prior art is formed on pixel region, has improved the aperture opening ratio of array base palte;
3, the whole covered substrates of etching barrier layer can not produce the contraposition offset issue of prior art, and the breadth length ratio of thin-film transistor (W/L) can finely tune through exposure sources according to the actual process situation, but the device property micro-control, and process conditions are flexible.
Description of drawings
Fig. 1 is the structural representation of existing metal oxide thin-film transistor array base palte;
Fig. 2 is the structural representation of the array base palte behind the formation gate electrode in the embodiment of the invention;
Fig. 3 is the structural representation of the array base palte behind the formation gate insulation layer in the embodiment of the invention;
Fig. 4 is the structural representation of the array base palte behind the formation active layer in the embodiment of the invention;
Fig. 5 is the structural representation of the array base palte behind the formation etching barrier layer in the embodiment of the invention;
Fig. 6 is the structural representation of the array base palte behind the formation source-drain electrode in the embodiment of the invention;
Fig. 7 is the structural representation of the array base palte behind the formation passivation layer in the embodiment of the invention;
Fig. 8 is the structural representation of the array base palte of the embodiment of the invention;
Fig. 9 is the manufacturing approach flow chart according to the array base palte of the embodiment of the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing and specific embodiment to describe the present invention below.
With reference to Fig. 9, the manufacturing approach of the array base palte of the embodiment of the invention can comprise the steps:
As shown in Figure 2; At first; Can adopt sputter, thermal evaporation or other film build method, on the transparency carrier of glass substrate 101 or other types, form the grid metal level, the grid metal level can adopt chromium (Cr), molybdenum (Mo), aluminium (Al), copper (Cu), tungsten (W), neodymium (Nd), indium-zinc oxide (IZO), indium tin oxide (ITO) and alloy thereof; And the grid metal level can be one or more layers; Then, on the grid metal level, form photoresist; Secondly, the employing portrayal has the mask of figure that photoresist is made public and develops formation photoresist mask; Once more, adopt the photoresist mask that the grid metal level is carried out etching, form the figure of gate electrode 201 and grid line; At last, peel off remaining photoresist.
As shown in Figure 3, can strengthen chemical vapour deposition (CVD) methods such as (PECVD) by using plasma, deposition gate insulation layer 301 on said substrate 101.Wherein, gate insulation layer 301 can be selected oxide (for example SiOx) or nitride materials such as (for example SiNx) for use, also can be two kinds combination.
The method that forms active layer is: as shown in Figure 4 (Fig. 4 a is a sectional view; Fig. 4 b is a plane graph); At first, can adopt methods such as sputter, on said substrate 101, form semiconductor layer; Semiconductor layer can be metal oxide semiconductor layer; Its material can be the zno-based material, also can be the IGZO sill, and its thickness is between
; Then, on semiconductor layer, form photoresist; Secondly, the employing portrayal has the mask of figure that photoresist is made public and develops formation photoresist mask; Once more, adopt the photoresist mask that semiconductor layer is carried out etching, form the figure of active layer 401; At last, peel off remaining photoresist.Wherein, active layer 401 can be bulk figure.
It is as shown in Figure 5 that (Fig. 5 a is a sectional view; Fig. 5 b is a plane graph); At first; Can adopt methods such as PECVD, on said substrate 101, form etching barrier layer 501, etching barrier layer 501 can adopt materials such as SiNx or SiOx; Also can be two kinds combination, its thickness is between
; Then, on etching barrier layer 501, form photoresist; Secondly, the employing portrayal has the mask (being referred to as first mask) of figure that photoresist is made public and develops formation photoresist mask; Once more, adopt the photoresist mask that etching barrier layer 501 is carried out etching, form first contact hole (source electrode contact hole) 502 and second contact hole (drain electrode contact hole) 503; At last, peel off remaining photoresist.
Shown in Fig. 5 b; The length (referring to along the length of grid line direction) of source electrode contact hole 502 and drain electrode contact hole 503 is the W of active switch; Distance between source electrode contact hole 502 and the drain electrode contact hole 503 (in Fig. 5 b, referring to the distance between the bottom of top and drain electrode contact hole 503 of source electrode contact hole 502) is the L of active switch.Because etching barrier layer 501 whole covered substrates, can not produce the contraposition offset issue of prior art, and the breadth length ratio of thin-film transistor (W/L) can finely tune according to the actual process situation through exposure sources, but the device property micro-control, process conditions are flexible.In the present embodiment, W is between 2 ~ 30um, and L is between 2 ~ 30um.
It is as shown in Figure 6 that (Fig. 6 a is a sectional view; Fig. 6 b is a plane graph), at first, can adopt sputter, thermal evaporation or other film build method; Metal level is leaked in the formation source on said substrate 101; Source drain-gate metal level can adopt chromium (Cr), molybdenum (Mo), aluminium (Al), copper (Cu), tungsten (W), neodymium (Nd), indium-zinc oxide (IZO), indium tin oxide (ITO) and alloy thereof, and metal level is leaked in the source can be one or more layers; Then, on source leakage metal level, form photoresist; Secondly, the employing portrayal has the mask of figure that photoresist is made public and develops formation photoresist mask; Once more, adopt the photoresist mask that metal level is leaked in the source and carry out etching, form the figure of source electrode 601, drain electrode 602 and data wire; At last, peel off remaining photoresist.Wherein, source electrode 601 is connected with active layer 401 through source electrode contact hole 502, and drain electrode 602 is connected with active layer 401 through drain electrode contact hole 503.
(Fig. 7 a is a sectional view, and Fig. 7 b is a plane graph) as shown in Figure 7 at first, can adopt methods such as PECVD, on said substrate 101, forms passivation layer 701, and passivation layer 701 can adopt materials such as SiNx or SiOx, also can be two kinds combination; Then, on passivation layer 701, form photoresist; Secondly, the employing portrayal has the mask (being aforesaid first mask) of figure that photoresist is made public and develops formation photoresist mask; Once more, adopt the photoresist mask that etching barrier layer 701 is carried out etching, form the 3rd contact hole 702 and the 4th contact hole (pixel electrode contact hole) 703; At last, peel off remaining photoresist.
In this step, identical mask when having adopted with the figure that forms etching barrier layer, and etch and be used for the 4th contact hole 703 that pixel electrode is connected with drain electrode 602.Need to prove; This step has also etched and the 3rd corresponding fully contact hole 702 of first contact hole 502 simultaneously; The generation of the 3rd contact hole 702 can not influence this complex procedures property and follow-up process complexity, and the product performance of thin-film transistor is not exerted an influence yet.
It is as shown in Figure 8 that (Fig. 8 a is a sectional view; Fig. 8 b is a plane graph); At first; Can adopt magnetron sputtering, thermal evaporation or other film build method, on said substrate 101, form transparency conducting layer, transparency conducting layer can adopt materials such as tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide; Then, on transparency conducting layer, form photoresist; Secondly, the employing portrayal has the mask plate of figure that photoresist is made public and develops, and forms the photoresist mask; Once more, adopt the photoresist mask that transparency conducting layer is carried out etching, form the figure of pixel electrode 801, said pixel electrode 801 is connected with drain electrode 602 through pixel electrode contact hole 703; At last, peel off remaining photoresist.
Need to prove; In this step; Also can in the 3rd contact hole 702, form electrically conducting transparent part 802, still, because pixel electrode 801 does not link to each other with electrically conducting transparent part 802; And this part is above gate electrode 201, so the existence of electrically conducting transparent part 802 can not exert an influence to display performance and display quality.
Manufacturing approach according to the above embodiment of the present invention is forming contact hole and on passivation layer, is forming contact hole on the etching barrier layer, employing be same mask, therefore reduced mask quantity, practiced thrift cost and reduced cost.The whole covered substrates of etching barrier layer can not produce the problem of prior art contraposition deviation, and to not influence of transmitance.Because the W and the L of active switch directly make public through the etching barrier layer mask, so W/L can finely tune through exposure sources according to the actual process situation, but the device property micro-control, and process conditions are flexible.Pixel electrode contact via hole is positioned at drain electrode position, gate electrode top, can not produce the reduction of the aperture opening ratio that prior art pixel electrode contact hole position causes in pixel portion, has improved the aperture opening ratio of product.
The embodiment of the invention also provides a kind of array base palte, in this array base palte, is formed with first contact hole and second contact hole on the etching barrier layer; Be formed with the 3rd contact hole and the 4th contact hole on the passivation layer; Because what form these contact holes employings is same mask, therefore, first contact hole is identical with the shape of the 3rd contact hole; And position corresponding (that is, said first contact hole overlaps with the orthographic projection of said the 3rd contact hole on substrate in the orthographic projection on the substrate); Second contact hole is identical with the shape of the 4th contact hole, and position corresponding (that is, said second contact hole overlaps with the orthographic projection of said the 4th contact hole on substrate in the orthographic projection on the substrate)
With reference to Fig. 8,, can comprise according to the array base palte of the embodiment of the invention:
Be formed on gate electrode 201 and grid line on the substrate 101;
Be formed on the gate insulation layer 301 on the substrate 101 that is formed with gate electrode 201 and grid line;
Be formed on the active layer 401 on the gate insulation layer 301;
Be formed on the etching barrier layer 501 on the substrate 101 that is formed with active layer 401 with source electrode contact hole 502 and drain electrode contact hole 503;
Be formed on source electrode 601, drain electrode 602 and data wire on the substrate 101 that is formed with etching barrier layer 501, source electrode 601 is connected with active layer 401 through source electrode contact hole 502, and drain electrode 602 is connected with active layer 401 through drain electrode contact hole 503;
Be formed on the passivation layer with pixel electrode contact hole 703 701 on the substrate that forms active electrode 601, drain electrode 602 and data wire, said pixel electrode contact hole 703 overlaps with the orthographic projection of said drain electrode contact hole 503 on substrate 101 in the orthographic projection on the substrate 101;
Be formed on the pixel electrode 801 on the substrate 101 that is formed with passivation layer 701, said pixel electrode 801 is connected with drain electrode 602 through pixel electrode contact hole 703.
Preferably; Said active layer 401 is the metal oxide active layer; Its material can be the zno-based material; Also can be the IGZO sill, its thickness is between
.
Preferably, the orthographic projection of said pixel electrode contact hole 703 on substrate 101 is positioned at gate electrode 201 residing zones.
Need to prove, in above-mentioned array base palte, also be formed with in the passivation layer 701 and the 3rd corresponding fully contact hole 702 of first contact hole 502, and, in the 3rd contact hole 702, also form electrically conducting transparent part 802.But because pixel electrode 801 do not link to each other with electrically conducting transparent part 802, and this part is above gate electrode 201, so the existence of electrically conducting transparent part 802 can not exert an influence to display performance and display quality.
The embodiment of the invention also provides a kind of display floater, and said display floater comprises any above-mentioned array base palte.
The embodiment of the invention also provides a kind of display unit, and said display unit comprises any above-mentioned array base palte.Said display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Should be noted that at last; Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Those of ordinary skill in the art is to be understood that; Can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit of technical scheme of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. an array base palte is characterized in that, comprising:
Be formed on the etching barrier layer on the substrate that is formed with active layer with source electrode contact hole and drain electrode contact hole;
Be formed on source electrode, drain electrode and data wire on the substrate that is formed with etching barrier layer, the source electrode is connected with active layer through source electrode contact hole, and drain electrode is connected with active layer through the drain electrode contact hole;
Be formed on the passivation layer with pixel electrode contact hole on the substrate that forms active electrode, drain electrode and data wire, said pixel electrode contact hole overlaps with the orthographic projection of said drain electrode contact hole on substrate in the orthographic projection on the substrate;
Be formed on the pixel electrode on the substrate that is formed with passivation layer, said pixel electrode is connected with drain electrode through the pixel electrode contact hole.
2. array base palte as claimed in claim 1 is characterized in that, also comprises:
Be formed on gate electrode and grid line on the substrate;
Be formed on the gate insulation layer on the substrate that is formed with gate electrode and grid line;
Be formed on the active layer on the gate insulation layer.
3. according to claim 1 or claim 2 array base palte is characterized in that:
Said active layer is the metal oxide active layer.
4. according to claim 1 or claim 2 array base palte is characterized in that:
The orthographic projection of said pixel electrode contact hole on substrate is positioned at the residing zone of gate electrode.
5. according to claim 1 or claim 2 array base palte is characterized in that:
Said etching barrier layer all covers said substrate.
6. the manufacturing approach of an array base palte is characterized in that, comprising:
Form etching barrier layer being formed with on the substrate of active layer, adopt first mask to carry out photoetching after, etch source electrode contact hole and drain electrode contact hole;
Be formed with formation source electrode, drain electrode and data wire on the substrate of etching barrier layer, the source electrode is connected with active layer through source electrode contact hole, and drain electrode is connected with active layer through the drain electrode contact hole;
Form passivation layer forming on the substrate of active electrode, drain electrode and data wire, adopt said first mask to carry out photoetching after, etch the pixel electrode contact hole;
Form pixel electrode being formed with on the substrate of passivation layer, said pixel electrode is connected with drain electrode through the pixel electrode contact hole.
7. manufacturing approach as claimed in claim 6 is characterized in that, before forming etching barrier layer, also comprises:
On substrate, form gate electrode and grid line;
On the substrate that is formed with gate electrode and grid line, form gate insulation layer;
On gate insulation layer, form active layer.
8. like claim 6 or 7 described manufacturing approaches, it is characterized in that:
Said active layer is the metal oxide active layer.
9. a display floater is characterized in that, comprises each described array base palte in the claim 1 to 5.
10. a display unit is characterized in that, comprises each described array base palte in the claim 1 to 5.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101677778A CN102709328B (en) | 2012-05-25 | 2012-05-25 | Array substrate, manufacturing method thereof, display panel and display device |
| PCT/CN2012/084166 WO2013174105A1 (en) | 2012-05-25 | 2012-11-06 | Array substrate, manufacturing method thereof, display panel, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101677778A CN102709328B (en) | 2012-05-25 | 2012-05-25 | Array substrate, manufacturing method thereof, display panel and display device |
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| Publication Number | Publication Date |
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| CN102709328A true CN102709328A (en) | 2012-10-03 |
| CN102709328B CN102709328B (en) | 2013-07-03 |
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| CN2012101677778A Active CN102709328B (en) | 2012-05-25 | 2012-05-25 | Array substrate, manufacturing method thereof, display panel and display device |
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| CN (1) | CN102709328B (en) |
| WO (1) | WO2013174105A1 (en) |
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| CN104269413A (en) * | 2014-09-22 | 2015-01-07 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display device |
| WO2017197913A1 (en) * | 2016-05-16 | 2017-11-23 | 京东方科技集团股份有限公司 | Thin film transistor array substrate and display device using same |
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| CN101964330A (en) * | 2009-07-24 | 2011-02-02 | 乐金显示有限公司 | Array substrate and method of fabricating the same |
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| CN102709328B (en) * | 2012-05-25 | 2013-07-03 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
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| CN101196668A (en) * | 2006-12-07 | 2008-06-11 | 三菱电机株式会社 | Display device and method of producing the same |
| CN101964330A (en) * | 2009-07-24 | 2011-02-02 | 乐金显示有限公司 | Array substrate and method of fabricating the same |
| CN102074502A (en) * | 2009-11-20 | 2011-05-25 | 乐金显示有限公司 | Method of fabricating array substrate |
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| US10163939B2 (en) | 2016-05-16 | 2018-12-25 | Boe Technology Group Co., Ltd. | Thin film transistor array substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013174105A1 (en) | 2013-11-28 |
| CN102709328B (en) | 2013-07-03 |
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