CN102708829A - Gate driving circuit and flat panel display equipment - Google Patents
Gate driving circuit and flat panel display equipment Download PDFInfo
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- CN102708829A CN102708829A CN2012101885516A CN201210188551A CN102708829A CN 102708829 A CN102708829 A CN 102708829A CN 2012101885516 A CN2012101885516 A CN 2012101885516A CN 201210188551 A CN201210188551 A CN 201210188551A CN 102708829 A CN102708829 A CN 102708829A
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Abstract
The invention provides a gate driving circuit and flat panel display equipment. The gate driving circuit comprises a pulse input circuit, a level shift circuit and an output buffer circuit, wherein the pulse input circuit outputs first and second control signals with opposite polarities; the level shift circuit receives the first and second control signals, and outputs a shift signal; the gate of a P-channel metal oxide semiconductor (PMOS) transistor of the output buffer circuit receives the shift signal, and the source of the PMOS transistor is connected to first threshold voltage; a common node of the PMOS transistor and a resistor is connected to the gate of a thin film transistor; and the other end of the resistor is connected to a grounding terminal. By the gate driving circuit and the flat panel display equipment, the output buffer circuit is designed into a mode that the PMOS transistor is connected in series with the resistor, so that the source of the PMOS transistor is connected to the first threshold voltage, and one end of the resistor is connected to the grounding terminal. Negative threshold voltage is not required to be additionally provided; and therefore, compared with the prior art, the gate driving circuit and the flat panel display equipment have the advantages of lowering complexity in circuit design, optimizing a circuit manufacture procedure and reducing a circuit layout space occupied by a printed circuit board.
Description
Technical field
The present invention relates to lcd technology, the flat-panel display devices that relates in particular to a kind of gate driver circuit and comprise this gate driver circuit.
Background technology
Flat-panel monitor (Flat panel display) is claimed flat-panel screens again, comprises LCD, plasma scope, electroluminescent display, vacuum fluorescent display, surface plate type cathode ray tube and light emitting diode etc.Flat-panel monitor has many advantages: slim and light and handy, complete machine can be made portable; Voltage is low, do not have X-radiation, do not have flashing, do not produce static, thereby can insalubrity; Low in energy consumption; The life-span of most of flat-panel monitor is longer than the life-span of cathode-ray tube (CRT).
Continuous progress along with development of science and technology and semiconductor technology; Thin Film Transistor-LCD (TFT-LCD; Thin Film Transistor Liquid Crystal Display) with its high brightness, high-contrast, low-power consumption, volume is little and many advantages such as in light weight, becomes the main flow display in the flat-panel display devices gradually.
Particularly; In TFT-LCD, be each color of pixel and brightness on the control display screen accurately, generally need install accordingly the switch (being TFT) of similar window shutter in each pixel; When " window shutter " when opening light can transmission come in, and " window shutter " light can't transmission when closing.For example, among the traditional T FT-LCD, through V
GH(also can be described as high-potential voltage) and V
GL(also can be described as low-potential voltage) also controlled opening and turn-offing of TFT switch, and then the driving that the liquid crystal molecule in the liquid crystal layer is discharged and recharged to realize picture shows.
Yet, in above-mentioned control mode, need extraly in control circuit provide gate driving required V
GL(being generally negative voltage), thereby can make circuit design more complicated, and can increase the pin number of chip for driving, the components and parts cost is raise.In addition, often size is bigger for the numerous chip for driving of pin number, need take more cloth board space, thereby has increased the area of printed circuit board (PCB).
In view of this, how existing gate driver circuit being improved, when realizing the driven function, also can reduce the purchase cost of circuit elements device, reduce the fabric swatch area of printed circuit board (PCB), is the person skilled problem that need solve in the industry.
Summary of the invention
To gate driver circuit of the prior art existing above-mentioned defective when designing, the flat-panel display devices that the invention provides a kind of gate driver circuit of novelty and comprise this gate driver circuit.
According to an embodiment of the present invention, a kind of gate driver circuit is provided, comprising:
One pulse input circuit is used to receive an input pulse, and exports one first control signal and one second control signal according to said input pulse, and said first control signal is opposite with the said second control signal polarity;
One level shift circuit is used to receive said first control signal and said second control signal, and exports a shift signal; And
One output buffer; Comprise a PMOS transistor and a resistance; The transistorized grid of said PMOS is used to receive said shift signal; The transistorized source electrode of said PMOS is connected to a first threshold voltage, and the node that said PMOS transistor drain links to each other with an end of said resistance is electrically connected to the grid of thin film transistor (TFT), and the other end of said resistance is connected to an earth terminal.
In one embodiment, pulse input circuit also comprises a phase inverter, and the input end of said phase inverter receives said pulse signal and exports said second control signal.
In one embodiment; Level shift circuit also comprises: one the one PMOS transistor; Its source electrode is electrically connected to said first threshold voltage, and its grid is electrically connected to the transistorized source electrode of said the 2nd NM0S, and its drain electrode is electrically connected to the source electrode of said first nmos pass transistor; One the 2nd PMOS transistor, its source electrode are electrically connected to said first threshold voltage, and its grid is electrically connected to the source electrode of said first nmos pass transistor, and its drain electrode is electrically connected to the source electrode of said second nmos pass transistor; One first nmos pass transistor, its grid are used to receive said first control signal, and its source electrode is electrically connected to the transistorized grid of PMOS of said output buffer, and its drain electrode is electrically connected to said earth terminal; And one second nmos pass transistor, its grid is used to receive said second control signal, and its drain electrode is electrically connected to said earth terminal.
When said first control signal is high level and said second control signal when being low level, the PMOS transistor of said output buffer is in opening state.When said first control signal is low level and said second control signal when being high level, the PMOS transistor of said output buffer is in off state.
According to another embodiment of the present invention, a kind of flat-panel display devices is provided, this flat-panel display devices comprises: like the described a plurality of gate driver circuits of an above-mentioned embodiment of the present invention, a pel array and a plurality of current-limiting resistance.Wherein, pel array comprises: many gate lines, the parallel setting of along continuous straight runs; Many data lines, vertically parallel setting; And a plurality of thin film transistor (TFT)s, each thin film transistor (TFT) is arranged at the crossover location of said gate line and corresponding data line.One end of each current-limiting resistance is electrically connected to a plurality of thin film transistor (TFT)s grid separately on the same gate line, and the other end is electrically connected to one second outside threshold voltage, and wherein this second threshold voltage is a negative voltage.
In one embodiment, the resistance of output buffer is mega-ohms, and said current-limiting resistance is a kilo-ohm level.When the PMOS of said output buffer transistor was opened, said first threshold voltage formed one first current return via said PMOS transistor, said current-limiting resistance and said second threshold voltage, and said thin film transistor (TFT) is opened.When the PMOS of said output buffer transistor turn-offed, said second threshold voltage formed one second current return via the resistance of said current-limiting resistance and said output buffer, and said thin film transistor (TFT) turn-offs.
In one embodiment, this flat-panel display devices is a LCD.
The flat-panel display devices that adopts gate driver circuit of the present invention and comprise this gate driver circuit; Output buffer is designed to PMOS transistor AND gate resistance series connection ways of connecting; Make the transistorized source electrode of PMOS be connected to first threshold voltage; And an end of resistance is connected to earth terminal, and same exportable TFT opens or turn-off required driving voltage.Than prior art, gate driver circuit of the present invention need not the extra threshold voltage that negative polarity is provided, thereby can reduce the complexity of circuit design.In addition,,, circuit manufacture procedure can not only be optimized, the shared cloth board space of printed circuit board (PCB) can also be reduced to replace existing nmos pass transistor through resistance serial connection PMOS transistor.
Description of drawings
The reader with reference to advantages after the embodiment of the present invention, will become apparent various aspects of the present invention.Wherein,
Fig. 1 illustrates the structural representation according to the gate driver circuit of an embodiment of the present invention;
Circuit theory synoptic diagram when Fig. 2 illustrates the gate driver circuit that uses Fig. 1 and comes drive thin film transistors to open; And
Circuit theory synoptic diagram when Fig. 3 illustrates the gate driver circuit that uses Fig. 1 and comes drive thin film transistors to turn-off.
Embodiment
For technology contents that the application is disclosed is more detailed and complete, can be with reference to accompanying drawing and following various specific embodiments of the present invention, identical mark is represented same or analogous assembly in the accompanying drawing.Yet the embodiment that those of ordinary skill in the art should be appreciated that hereinafter to be provided is used for limiting the scope that the present invention is contained.In addition, accompanying drawing only is used for schematically explaining, does not draw according to its life size.
With reference to the accompanying drawings, the embodiment of various aspects of the present invention is done further to describe in detail.
Fig. 1 illustrates the structural representation according to the gate driver circuit of an embodiment of the present invention.
With reference to Fig. 1, this gate driver circuit 1 comprises a pulse input circuit 10, a level shift circuit 20 and an output buffer 30.Particularly, level shift circuit 20 and pulse input circuit 10 cascades, output buffer 30 and level shift circuit cascade.
Wherein, pulse input circuit 10 is used to receive an input pulse, and exports one first control signal and one second control signal according to this input pulse, and this first control signal is opposite with this second control signal polarity.For example, input pulse is made up of a plurality of rect.p.s (or being called square-wave pulse), the noble potential corresponding voltage V of pulse signal
DD, the electronegative potential corresponding voltage Vss of pulse signal.In Fig. 1, first control signal that pulse input circuit 10 is exported is corresponding to input pulse, and second control signal that pulse input circuit 10 is exported is corresponding to the signal of input pulse after via the phase inverter anti-phase.
In one embodiment, first control signal is high-potential voltage V
DD, then second control signal is low-potential voltage Vss.In another embodiment, second control signal is high-potential voltage V
DD, then first control signal is low-potential voltage Vss.
In one embodiment, level shift circuit 20 comprises PMOS transistor M1, PMOS transistor M3, nmos pass transistor M2 and nmos pass transistor M4.
Concrete circuit connecting relation can be described below: the source electrode of PMOS transistor M1 is electrically connected to first threshold voltage V
GH, the grid of PMOS transistor M1 is electrically connected to the source electrode of nmos pass transistor M4, and the drain electrode of PMOS transistor M1 is electrically connected to the source electrode of nmos pass transistor M2.The source electrode of PMOS transistor M3 is electrically connected to first threshold voltage V
GH, the grid of PMOS transistor M3 is electrically connected to the source electrode of nmos pass transistor M2, and the drain electrode of PMOS transistor M3 is electrically connected to the source electrode of nmos pass transistor M4.The grid of nmos pass transistor M2 is used to receive first control signal, and the source electrode of nmos pass transistor M2 is electrically connected to the grid of the PMOS transistor M5 of output buffer 30, and the drain electrode of nmos pass transistor M2 is electrically connected to earth terminal GND.The grid of nmos pass transistor M4 is used to receive second control signal, and the drain electrode of nmos pass transistor M4 is electrically connected to earth terminal GND, and the source electrode of nmos pass transistor M4 is electrically connected to the drain electrode of grid and the PMOS transistor M3 of PMOS transistor M1.
When first control signal is a high level, and second control signal is when being low level, and PMOS transistor M1 is in off state; PMOS transistor M3 is in opening state, and nmos pass transistor M2 is in opening state, and nmos pass transistor M4 is in off state; At this moment, the source electrode of nmos pass transistor M2 is ground voltage GND, thereby; The PMOS transistor M5 of output buffer 30 is in opening state, gate driver circuit output high-potential voltage V
GH
When first control signal is a low level; And when second control signal was high level, PMOS transistor M1 was in opening state, and PMOS transistor M3 is in off state; Nmos pass transistor M2 is in off state; Nmos pass transistor M4 is in opening state, and at this moment, the source electrode of nmos pass transistor M2 is high-potential voltage V
GH, thereby the PMOS transistor M5 of output buffer 30 is in off state, gate driver circuit output ground voltage GND.
The circuits built mode that it will be understood by those of skill in the art that above-mentioned PMOS transistor M1, M3 and nmos pass transistor M2 and M4 only is an illustrative examples of level shift circuit 20, yet the present invention has more than and is confined to this.For example, also can adopt other circuit form to realize the same function of level shift circuit 20.
Circuit theory synoptic diagram when Fig. 2 illustrates the gate driver circuit that uses Fig. 1 and comes drive thin film transistors to open.Circuit theory synoptic diagram when Fig. 3 illustrates the gate driver circuit that uses Fig. 1 and comes drive thin film transistors to turn-off.
With reference to Fig. 2 and Fig. 3, flat-panel display devices of the present invention comprises gate driver circuit 1 (at this, Fig. 2 and Fig. 3 only illustrate the output buffer 30 that is associated with flat-panel display devices), a pel array 40 and a plurality of current-limiting resistance R.For example, this flat-panel display devices is a LCD.
In one embodiment, elect the resistance R of output buffer 30 as mega-ohms, and elect current-limiting resistance R as a kilo-ohm level.Therefore, when the PMOS of output buffer 30 transistor M5 opens, first threshold voltage V
GHVia PMOS transistor M5, current-limiting resistance R and the second threshold voltage V
GLForm a current return (shown in the dotted arrow among Fig. 2), this moment, thin film transistor (TFT) was in opening state.
In addition, when the PMOS of output buffer 30 transistor M5 turn-offs, the second threshold voltage V
GLResistance R via current-limiting resistance R and output buffer 30 forms another current return (shown in the dotted arrow among Fig. 3), and this moment, thin film transistor (TFT) was in off state.
The flat-panel display devices that adopts gate driver circuit of the present invention and comprise this gate driver circuit; Output buffer is designed to PMOS transistor AND gate resistance series connection ways of connecting; Make the transistorized source electrode of PMOS be connected to first threshold voltage; And an end of resistance is connected to earth terminal, and same exportable TFT opens or turn-off required driving voltage.Than prior art, gate driver circuit of the present invention need not the extra threshold voltage that negative polarity is provided, thereby can reduce the complexity of circuit design.In addition,,, circuit manufacture procedure can not only be optimized, the shared cloth board space of printed circuit board (PCB) can also be reduced to replace existing nmos pass transistor through resistance serial connection PMOS transistor.
In the preceding text, illustrate and describe embodiment of the present invention.But those skilled in the art can understand, and under situation without departing from the spirit and scope of the present invention, can also specific embodiments of the invention do various changes and replacement.These changes and replacement all drop in claims of the present invention institute restricted portion.
Claims (10)
1. a gate driver circuit is characterized in that, said gate driver circuit comprises:
One pulse input circuit is used to receive an input pulse, and exports one first control signal and one second control signal according to said input pulse, and said first control signal is opposite with the said second control signal polarity;
One level shift circuit is used to receive said first control signal and said second control signal, and exports a shift signal; And
One output buffer; Comprise a PMOS transistor and a resistance; The transistorized grid of said PMOS is used to receive said shift signal; The transistorized source electrode of said PMOS is connected to a first threshold voltage, and the node that said PMOS transistor drain links to each other with an end of said resistance is electrically connected to the grid of thin film transistor (TFT), and the other end of said resistance is connected to an earth terminal.
2. gate driver circuit according to claim 1 is characterized in that said pulse input circuit also comprises a phase inverter, and the input end of said phase inverter receives said pulse signal and exports said second control signal.
3. gate driver circuit according to claim 1 is characterized in that, said level shift circuit also comprises:
One the one PMOS transistor, its source electrode are electrically connected to said first threshold voltage, and its grid is electrically connected to the source electrode of said second nmos pass transistor, and its drain electrode is electrically connected to the source electrode of said first nmos pass transistor;
One the 2nd PMOS transistor, its source electrode are electrically connected to said first threshold voltage, and its grid is electrically connected to the source electrode of said first nmos pass transistor, and its drain electrode is electrically connected to the source electrode of said second nmos pass transistor;
One first nmos pass transistor, its grid are used to receive said first control signal, and its source electrode is electrically connected to the transistorized grid of PMOS of said output buffer, and its drain electrode is electrically connected to said earth terminal; And
One second nmos pass transistor, its grid are used to receive said second control signal, and its drain electrode is electrically connected to said earth terminal.
4. gate driver circuit according to claim 3 is characterized in that, when said first control signal is high level and said second control signal when being low level, the PMOS transistor of said output buffer is in opening state.
5. gate driver circuit according to claim 3 is characterized in that, when said first control signal is low level and said second control signal when being high level, the PMOS transistor of said output buffer is in off state.
6. a flat-panel display devices is characterized in that, said flat-panel display devices comprises:
Like each described a plurality of gate driver circuits in the claim 1 to 5;
One pel array comprises:
Many gate lines, the parallel setting of along continuous straight runs;
Many data lines, vertically parallel setting; And
A plurality of thin film transistor (TFT)s, each thin film transistor (TFT) are arranged at the crossover location of said gate line and corresponding data line; And
A plurality of current-limiting resistances, an end of each current-limiting resistance are electrically connected to a plurality of thin film transistor (TFT)s grid separately on the same gate line, and the other end is electrically connected to one second outside threshold voltage, and wherein, said second threshold voltage is a negative voltage.
7. flat-panel display devices according to claim 6 is characterized in that, the resistance of said output buffer is mega-ohms, and said current-limiting resistance is a kilo-ohm level.
8. flat-panel display devices according to claim 7; It is characterized in that; When the PMOS of said output buffer transistor is opened; Said first threshold voltage forms one first current return via said PMOS transistor, said current-limiting resistance and said second threshold voltage, and said thin film transistor (TFT) is opened.
9. flat-panel display devices according to claim 7; It is characterized in that; When the PMOS of said output buffer transistor turn-offed, said second threshold voltage formed one second current return via the resistance of said current-limiting resistance and said output buffer, and said thin film transistor (TFT) turn-offs.
10. flat-panel display devices according to claim 6 is characterized in that, said flat-panel display devices is a LCD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101885516A CN102708829A (en) | 2012-06-06 | 2012-06-06 | Gate driving circuit and flat panel display equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101885516A CN102708829A (en) | 2012-06-06 | 2012-06-06 | Gate driving circuit and flat panel display equipment |
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| CN102708829A true CN102708829A (en) | 2012-10-03 |
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| CN2012101885516A Pending CN102708829A (en) | 2012-06-06 | 2012-06-06 | Gate driving circuit and flat panel display equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020223970A1 (en) * | 2019-05-09 | 2020-11-12 | 京东方科技集团股份有限公司 | Gate drive circuit and current adjustment method therefor, and display apparatus |
-
2012
- 2012-06-06 CN CN2012101885516A patent/CN102708829A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020223970A1 (en) * | 2019-05-09 | 2020-11-12 | 京东方科技集团股份有限公司 | Gate drive circuit and current adjustment method therefor, and display apparatus |
| CN112384967A (en) * | 2019-05-09 | 2021-02-19 | 京东方科技集团股份有限公司 | Grid driving circuit, current adjusting method thereof and display device |
| US11295693B2 (en) | 2019-05-09 | 2022-04-05 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Gate driving circuit, current adjusting method thereof and display device |
| CN112384967B (en) * | 2019-05-09 | 2022-06-07 | 京东方科技集团股份有限公司 | Grid driving circuit, current adjusting method thereof and display device |
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Application publication date: 20121003 |