CN102708793A - Pixel unit driving circuit and method as well as pixel unit - Google Patents

Pixel unit driving circuit and method as well as pixel unit Download PDF

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Publication number
CN102708793A
CN102708793A CN2012100478936A CN201210047893A CN102708793A CN 102708793 A CN102708793 A CN 102708793A CN 2012100478936 A CN2012100478936 A CN 2012100478936A CN 201210047893 A CN201210047893 A CN 201210047893A CN 102708793 A CN102708793 A CN 102708793A
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thin film
film transistor
tft
drain electrode
oled
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CN2012100478936A
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CN102708793B (en
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青海刚
祁小敬
高永益
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to CN201210047893.6A priority Critical patent/CN102708793B/en
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Priority to PCT/CN2012/084015 priority patent/WO2013127189A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes

Abstract

The invention provides a pixel unit driving circuit and method as well as a pixel unit. The pixel unit driving circuit comprises a driving thin film transistor, a first switching element, a storage capacitor, a driving control unit and a charging control unit; a grid electrode of the driving thin film transistor is connected with the first end of the storage capacitor, and is further connected with a drain electrode of the driving thin film transistor through the charging control unit; a source electrode of the driving thin film transistor is connected with an OLED (Organic Light Emitting Diode), and is connected with the second end of the storage capacitor through the driving control unit; the drain electrode of the driving thin film transistor is connected with a driving power supply through the first switching element; the second end of the storage capacitor Cs is connected with the driving power supply through the charging control unit; the driving control unit is connected with the driving power supply and the OLED respectively; and the charging control unit is connected with a data wire and the OLED respectively. With the adoption of the pixel unit driving circuit provided by the invention, critical voltage of the driving thin film transistor is compensated, and the fall of driving current, caused by boosting of critical voltage due to material aging of the OLED, can be compensated.

Description

Pixel cell driving circuit, pixel cell driving method and pixel cell
Technical field
The present invention relates to the organic light emitting display field, relate in particular to a kind of pixel cell driving circuit, pixel cell driving method and pixel cell.
Background technology
AMOLED (Active Matrix Organic Light Emitting Diode; The active matrix organic light-emitting diode) can luminously be to drive by the electric current that drive TFT produces when the state of saturation; Because when importing identical gray scale voltage; Different critical voltages can produce different drive currents, causes the inconsistency of electric current.The non-constant of homogeneity of Vth (transistor threshold voltage) on LTPS (low temperature polycrystalline silicon) processing procedure, Vth also has drift simultaneously, and so traditional 2T1C circuit brightness uniformity is very poor always.
Traditional 2T1C pixel cell driving circuit is as shown in Figure 1, and circuit only contains two TFT, and T1 is as switch, and DTFT is used for pixel drive.Traditional 2T1C pixel cell driving circuit operation is also fairly simple; Control timing figure to this 2T1C pixel cell driving circuit is as shown in Figure 2, when the scanning level Vscan of sweep trace Scan output when low, T1 opens; Gray scale voltage on the data line Data charges to capacitor C; When scanning level when being high, T1 closes, and capacitor C is used for preserving gray scale voltage.Because VDD (voltage of driving power high level output terminal output) is higher, so DTFT is in state of saturation, the drive current I=K (Vsg-|Vth|) of OLED 2=K (VDD-Vdata-|Vth|) 2, Vsg is the source electrode of DTFT and the voltage difference between the grid, and Vdata is the gray scale voltage on the data line Data, and K is a constant relevant with transistor size and carrier mobility, in case TFT size and technology confirm that K confirms.Comprised Vth in the drive current formula of this 2T1C pixel cell driving circuit; As previously mentioned, because LTPS technology immature, even if same technological parameter; The Vth of the TFT of the panel diverse location of making also has than big-difference; Caused the drive current of OLED under the same gray scale voltage different, so the panel diverse location brightness meeting under this drive scheme is variant, the brightness homogeneity is poor.The prolongation of using along with oled panel simultaneously, OLED material are aging gradually, cause the luminous critical voltage of OLED to rise, and under the same electric current, the OLED material luminous efficiency descends, and panel luminance reduces.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of pixel cell driving circuit, pixel cell driving method and pixel cell; Can compensate the critical voltage of drive thin film transistors, compensate the drive current decline that OLED material aging critical voltage rises and causes simultaneously.
In order to achieve the above object, the invention provides a kind of pixel cell driving circuit, be used for driving OLED, comprise drive thin film transistors, first on-off element, MM CAP, driving control unit and charging control unit, wherein,
The grid of said drive thin film transistors is connected with first end of said MM CAP, also is connected with the drain electrode of said drive thin film transistors through said charging control unit;
The source electrode of said drive thin film transistors is connected with said OLED, and is connected with second end of said MM CAP through said driving control unit;
The drain electrode of said drive thin film transistors is connected with driving power through said first on-off element;
Second end of said MM CAP Cs also is connected with said driving power through said charging control unit;
Said driving control unit also is connected with said OLED with said driving power respectively;
Said charging control unit also is connected with said OLED with data line respectively.
During enforcement, said drive thin film transistors is a p type thin film transistor (TFT);
The source electrode of said drive thin film transistors is connected with the negative electrode of said OLED;
The drain electrode of said drive thin film transistors is connected with the low level output terminal of driving power through said first on-off element;
Second end of said MM CAP is connected with the low level output terminal of said driving power through said charging control unit.
During enforcement, said first on-off element is the first film transistor, and said driving control unit comprises second thin film transistor (TFT) and the 3rd thin film transistor (TFT), and said charging control unit comprises the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the low level output terminal of said driving power, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said second thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the high level output terminal of said driving power, and drain electrode is connected with the anode of said OLED;
Said the 3rd thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the source electrode of said drive thin film transistors, and drain electrode is connected with second end of said MM CAP;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with first end of said MM CAP, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said the 5th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the low level output terminal of said driving power, and drain electrode is connected with second end of said MM CAP;
Said the 6th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the anode of said OLED, and drain electrode is connected with data line;
Said the first film transistor, said second thin film transistor (TFT) and said the 3rd thin film transistor (TFT) all are p type thin film transistor (TFT)s, and said the 4th on-off element, said the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are n type thin film transistor (TFT)s.
During enforcement, said first on-off element is the first film transistor, and said driving control unit comprises second thin film transistor (TFT) and the 3rd thin film transistor (TFT), and said charging control unit comprises the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the low level output terminal of said driving power, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said second thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the high level output terminal of said driving power, and drain electrode is connected with the anode of said OLED;
Said the 3rd thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the source electrode of said drive thin film transistors, and drain electrode is connected with second end of said MM CAP;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with first end of said MM CAP, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said the 5th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the high level output terminal of driving power;
Said the 6th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the anode of said OLED, and drain electrode is connected with data line;
Said the first film transistor, said second thin film transistor (TFT) and said the 3rd thin film transistor (TFT) all are p type thin film transistor (TFT)s, and said the 4th on-off element, said the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are n type thin film transistor (TFT)s.
During enforcement, said drive thin film transistors is a n type thin film transistor (TFT);
The source electrode of said drive thin film transistors is connected with the anode of said OLED;
The drain electrode of said drive thin film transistors is connected with the high level output terminal of driving power through said first on-off element;
Second end of said MM CAP is connected with the high level output terminal of said driving power through said charging control unit.
During enforcement, said first on-off element is the first film transistor, and said charging control unit comprises second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT), and said driving control unit comprises the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the high level output terminal of driving power;
Said second thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the high level output terminal of said driving power;
Said the 3rd thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the grid of said drive thin film transistors;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with data line, and drain electrode is connected with the negative electrode of said OLED;
Said the 5th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the source electrode of said drive thin film transistors;
Said the 6th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the negative electrode of said OLED, and drain electrode is connected with the low level output terminal of said driving power;
Said second thin film transistor (TFT), said the 3rd thin film transistor (TFT) and said the 4th thin film transistor (TFT) are n type thin film transistor (TFT), and said the first film transistor, the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are p type thin film transistor (TFT).
During enforcement, said first on-off element is the first film transistor, and said charging control unit comprises second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT), and said driving control unit comprises the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the high level output terminal of driving power;
Said second thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the low level output terminal of said driving power, and drain electrode is connected with second end of said MM CAP;
Said the 3rd thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the grid of said drive thin film transistors;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with data line, and drain electrode is connected with the negative electrode of said OLED;
Said the 5th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the source electrode of said drive thin film transistors;
Said the 6th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the negative electrode of said OLED, and drain electrode is connected with the low level output terminal of said driving power;
Said second thin film transistor (TFT), said the 3rd thin film transistor (TFT) and said the 4th thin film transistor (TFT) are n type thin film transistor (TFT), and said the first film transistor, the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are p type thin film transistor (TFT).
The present invention also provides a kind of pixel cell driving method, and it is applied to above-mentioned pixel cell driving circuit, and said pixel cell driving method may further comprise the steps:
The pixel charge step: charging control unit at first controlling and driving thin film transistor (TFT) is opened, and control charges to MM CAP, is increased to until the grid potential of drive thin film transistors to make said drive thin film transistors close;
The luminous step display of driving OLED: driving control unit is controlled said drive thin film transistors conducting and its grid is in vacant state, with the luminous demonstration of driving OLED and make the gate source voltage of said drive thin film transistors compensate the threshold voltage of said drive thin film transistors.
The present invention also provides a kind of pixel cell, comprises OLED and above-mentioned pixel cell driving circuit;
The source electrode of the drive thin film transistors that said pixel cell driving circuit comprises is connected with the negative electrode of said OLED; The anode of said OLED is connected with the high level output terminal of driving power through said driving control unit, and the drain electrode of said drive thin film transistors is connected with the low level output terminal of said driving power through said charging control unit.
The present invention also provides a kind of pixel cell, comprises OLED and above-mentioned pixel cell driving circuit;
The source electrode of the drive thin film transistors that said pixel cell driving circuit comprises is connected with the anode of said OLED; The negative electrode of said OLED is connected with the low level output terminal of driving power through said charging control unit, and the drain electrode of said drive thin film transistors is connected with the high level output terminal of said driving power through said driving control unit.
Compared with prior art; Pixel cell driving circuit of the present invention, pixel cell driving method and pixel cell; Through the source electrode input of data voltage Vdata from DTFT; Utilize the diode of DTFT to connect self discharge with Vth (threshold voltage of DTFT), Vdata (data voltage), Vth_oled (the luminescence threshold voltage of OLED) deposits among the MM CAP Cs; The critical voltage of compensation drive thin film transistors, the drive current that utilizes the rising of voltage back coupling mechanism compensation OLED material aging critical voltage to cause simultaneously descends.
Description of drawings
Fig. 1 is the circuit diagram of traditional 2T1C pixel cell driving circuit;
Fig. 2 is the control timing figure to this traditional 2T1C pixel cell driving circuit;
Fig. 3 is the circuit diagram of the described pixel cell driving circuit of first embodiment of the invention;
Fig. 4 is the circuit diagram of the described pixel cell driving circuit of second embodiment of the invention;
Fig. 5 is the circuit diagram of the described pixel cell driving circuit of third embodiment of the invention;
Fig. 6 is the circuit diagram of the described pixel cell driving circuit of fourth embodiment of the invention;
Fig. 7 is the circuit diagram of the described pixel cell driving circuit of fifth embodiment of the invention;
Fig. 8 is the circuit diagram of the described pixel cell driving circuit of sixth embodiment of the invention;
The sequential chart of each signal when Fig. 9 is the described pixel cell drive circuit works of second embodiment of the invention;
Figure 10 A is the equivalent circuit diagram of the described pixel cell driving circuit of second embodiment of the invention in very first time section;
Figure 10 B is the equivalent circuit diagram of the described pixel cell driving circuit of second embodiment of the invention in second time period;
Figure 10 C is the equivalent circuit diagram of the described pixel cell driving circuit of second embodiment of the invention in the 3rd time period;
Figure 11 A is the equivalent circuit diagram of the described pixel cell driving circuit of third embodiment of the invention in very first time section;
Figure 11 B is the equivalent circuit diagram of the described pixel cell driving circuit of third embodiment of the invention in second time period;
Figure 11 C is the equivalent circuit diagram of the described pixel cell driving circuit of third embodiment of the invention in the 3rd time period;
The sequential chart of each signal when Figure 12 is the described pixel cell drive circuit works of described pixel cell driving circuit of fifth embodiment of the invention and the 6th embodiment.
Embodiment
As shown in Figure 3, the described pixel cell driving circuit of first embodiment of the invention is used for driving OLED, comprises drive thin film transistors DTFT, first on-off element 10, MM CAP Cs, driving control unit 11 and charging control unit 12, wherein,
The grid of said drive thin film transistors DTFT is connected with first end of said MM CAP Cs, also is connected with the drain electrode of said drive thin film transistors DTFT through said charging control unit 12;
The source electrode of said drive thin film transistors DTFT is connected with the negative electrode of said OLED, and is connected with second end of said MM CAP Cs through said driving control unit 11;
The drain electrode of said drive thin film transistors DTFT is connected with the low level output terminal of driving power through said first on-off element 10;
Second end of said MM CAP Cs is connected with the low level output terminal of said driving power through said charging control unit 12;
The anode of said OLED is connected with the high level output terminal of said driving power through said driving control unit 11, also is connected with data line through said charging control unit 12;
Said drive thin film transistors DTFT is a p type thin film transistor (TFT);
Said data line output data voltage Vdata;
The output voltage of the high level output terminal of said driving power is VDD, and the output voltage of the low level output terminal of said driving power is VSS;
The P point is the node that is connected with second end of said MM CAP Cs, and the G point is the node that is connected with first end of said MM CAP Cs.
The described pixel cell driving circuit of first embodiment of the invention is when work:
In very first time section, i.e. incipient stage, being connected between the grid of said charging control unit 12 conducting DTFT and the drain electrode, being connected between second end of conducting Cs and the low level output terminal of driving power, and being connected between the anode of conducting OLED and the data line; If a stage driving tube DTFT is a closed condition before this, then G point (node that promptly is connected with the grid of DTFT) is in vacant state, and the conducting of said charging control unit 12; Will make unsettled G point current potential seriously drop-down, make DTFT open, if open before this by a stage itself for DTFT; Then can get into the duty in this stage, DTFT is in the diode connection status, and data line is through OLED, DTFT and 12 pairs of MM CAP Cs chargings of said charging control unit; The current potential that makes G order raises gradually; Up to G point current potential Vg=Vdata-Vth_oled-|Vth|, then DTFT closes, P point (node that promptly is connected with second end of said MM CAP) current potential Vp=VSS; The voltage difference Vc=Vg-Vp=Vdata-Vth_oled-|Vth|-VSS at MM CAP Cs two ends; Wherein, Vth_oled is the luminous critical cross-pressure of OLED, and Vth is the threshold voltage of DTFT;
In second time period, i.e. being connected between the buffer stage, the drain electrode of said first on-off element, 10 conducting DTFT and the low level output terminal of driving power; DTFT also closes; Be in the work halted state, because the switching of switch produces unnecessary noise, P point and G point are in vacant state to avoid; The voltage Vc at MM CAP Cs two ends is still constant, Vc=Vg-Vp=Vdata-Vth_oled-|Vth|-VSS;
In the 3rd time period; Being connected between the drain electrode of said first on-off element, 10 conducting DTFT and the low level output terminal of driving power, between the source electrode of said driving control unit 11 conducting DTFT and second end of Cs be connected and the high level output terminal of the anode of the said OLED of conducting and said driving power between be connected; (Voled is the WV of OLED under the GTG for this reason to VDD-Voled because P point current potential is by the VSS saltus step; With Vth_oled and inconsistent); And the grid of DTFT is in vacant state; Therefore the voltage jump of Vg is Vdata-Vth_oled-|Vth|-VSS+VDD-Voled, at this moment the source electrode of DTFT and voltage difference Vsg=VDD-Voled-Vg=VDD-Voled-(the Vdata-Vth_oled-|Vth|-VSS+VDD-Voled)=VSS+Vth_oled+|Vth|-Vdata between the grid; DTFT works, and flows through electric current I=K (Vsg-|Vth|) of DTFT 2=K (VSS+Vth_oled+|Vth|-Vdata-|Vth|) 2=K (VSS+Vth_oled-Vdata) 2, OLED begins luminous, up to next frame; Wherein, K is the current coefficient of DTFT;
K = C ox × μ × W L ;
μ, C OX, W, L be respectively the field-effect mobility of DTFT, gate insulation layer unit-area capacitance, channel width, length;
It doesn't matter can to find to flow through the electric current I of DTFT and the threshold voltage vt h of DTFT, so can improve the homogeneity of electric current, reaches the even of brightness; Comprised Vth_oled and flow through simultaneously in the computing formula of electric current I of DTFT; Prolongation along with service time; OLED material aging luminescence efficiency descends; Vth_oled can rise, and the rising of Vth_oled makes the corresponding increase of working current, has so improved the panel luminance reduction that material aging causes.
As shown in Figure 4, the described pixel cell driving circuit of second embodiment of the invention is based on the described pixel cell driving circuit of first embodiment of the invention; In the described pixel cell driving circuit of second embodiment of the invention; Said first on-off element 10 is a first film transistor T 1; Said driving control unit 11 comprises the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3, and said charging control unit 12 comprises the 4th thin film transistor (TFT) T4, the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6;
Said the first film transistor T 1, grid is connected with first control line of the output first control signal S1, and drain electrode is connected with the low level output terminal of said driving power, and source electrode is connected with the drain electrode of said drive thin film transistors DTFT;
The said second thin film transistor (TFT) T2, grid is connected with second control line of the output second control signal S2, and source electrode is connected with the high level output terminal of said driving power, and drain electrode is connected with the anode of said OLED;
Said the 3rd thin film transistor (TFT) T3, grid is connected with second control line, and source electrode is connected with the source electrode of said drive thin film transistors DTFT, and drain electrode is connected with second end of said MM CAP Cs;
Said the 4th thin film transistor (TFT) T4, grid is connected with first control line, and drain electrode is connected with first end of said MM CAP Cs, and source electrode is connected with the drain electrode of said drive thin film transistors DTFT;
Said the 5th thin film transistor (TFT) T5, grid is connected with first control line, and source electrode is connected with the low level output terminal of said driving power, and drain electrode is connected with second end of said MM CAP Cs;
Said the 6th thin film transistor (TFT) T6, grid is connected with first control line, and source electrode is connected with the anode of said OLED, and drain electrode is connected with data line;
Said the first film transistor T 1, the said second thin film transistor (TFT) T2 and said the 3rd thin film transistor (TFT) T3 are p type thin film transistor (TFT)s, and said the 4th on-off element T4, said the 5th thin film transistor (TFT) T5 and said the 6th thin film transistor (TFT) T6 are n type thin film transistor (TFT)s;
The output voltage of the high level output terminal of said driving power is VDD, and the output voltage of the low level output terminal of said driving power is VSS;
The P point is the node that is connected with second end of said MM CAP Cs, and the G point is the node that is connected with first end of said MM CAP Cs.
As shown in Figure 5, the described pixel cell driving circuit of third embodiment of the invention is based on the described pixel cell driving circuit of first embodiment of the invention; In the described pixel cell driving circuit of third embodiment of the invention; Said first on-off element 10 is a first film transistor T 1; Said driving control unit 11 comprises the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3, and said charging control unit 12 comprises the 4th thin film transistor (TFT) T4, the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6;
Said the first film transistor T 1, grid is connected with first control line of the output first control signal S1, and drain electrode is connected with the low level output terminal of said driving power, and source electrode is connected with the drain electrode of said drive thin film transistors DTFT;
The said second thin film transistor (TFT) T2, grid is connected with second control line of the output second control signal S2, and source electrode is connected with the high level output terminal of said driving power, and drain electrode is connected with the anode of said OLED;
Said the 3rd thin film transistor (TFT) T3, grid is connected with second control line, and source electrode is connected with the source electrode of said drive thin film transistors DTFT, and drain electrode is connected with second end of said MM CAP Cs;
Said the 4th thin film transistor (TFT) T4, grid is connected with first control line, and drain electrode is connected with first end of said MM CAP Cs, and source electrode is connected with the drain electrode of said drive thin film transistors DTFT;
Said the 5th thin film transistor (TFT) T5, grid is connected with first control line, and source electrode is connected with second end of said MM CAP Cs, and drain electrode is connected with the high level output terminal of driving power;
Said the 6th thin film transistor (TFT) T6, grid is connected with first control line, and source electrode is connected with the anode of said OLED, and drain electrode is connected with data line;
Said the first film transistor T 1, the said second thin film transistor (TFT) T2 and said the 3rd thin film transistor (TFT) T3 are p type thin film transistor (TFT)s, and said the 4th on-off element T4, said the 5th thin film transistor (TFT) T5 and said the 6th thin film transistor (TFT) T6 are n type thin film transistor (TFT)s;
The output voltage of the high level output terminal of said driving power is VDD, and the output voltage of the low level output terminal of said driving power is VSS;
The P point is the node that is connected with second end of said MM CAP Cs, and the G point is the node that is connected with first end of said MM CAP Cs.
As shown in Figure 6, the described pixel cell driving circuit of fourth embodiment of the invention is used for driving OLED, comprises drive thin film transistors DTFT, first on-off element 20, MM CAP Cs, driving control unit 21 and charging control unit 22, wherein,
The grid of said drive thin film transistors DTFT is connected with first end of said MM CAP Cs, also is connected with the drain electrode of said drive thin film transistors DTFT through said charging control unit 22;
The source electrode of said drive thin film transistors DTFT is connected with the anode of said OLED, and is connected with second end of said MM CAP Cs through said driving control unit 21;
The drain electrode of said drive thin film transistors DTFT is connected with the high level output terminal of driving power through said first on-off element 20;
Second end of said MM CAP Cs is connected with the high level output terminal of said driving power through said charging control unit 22;
The negative electrode of said OLED is connected with data line through said charging control unit 22, also is connected with the low level output terminal of said driving power through said driving control unit 21;
Said drive thin film transistors DTFT is a n type thin film transistor (TFT);
Said data line output data voltage Vdata;
The output voltage of the high level output terminal of said driving power is VDD, and the output voltage of the low level output terminal of said driving power is VSS.
As shown in Figure 7, the described pixel cell driving circuit of fifth embodiment of the invention is based on the described pixel cell driving circuit of fourth embodiment of the invention; In the described pixel cell driving circuit of fifth embodiment of the invention; Said first on-off element 20 is a first film transistor T 1; Said charging control unit 22 comprises the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4, and said driving control unit 21 comprises the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6;
Said the first film transistor T 1, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors DTFT, and source electrode is connected with the high level output terminal of driving power;
The said second thin film transistor (TFT) T2, grid is connected with first control line, and source electrode is connected with second end of said MM CAP Cs, and drain electrode is connected with the high level output terminal of said driving power;
Said the 3rd thin film transistor (TFT) T3, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors DTFT, and source electrode is connected with the grid of said drive thin film transistors DTFT;
Said the 4th thin film transistor (TFT) T4, grid is connected with first control line, and source electrode is connected with data line, and drain electrode is connected with the negative electrode of said OLED;
Said the 5th thin film transistor (TFT) T5, grid is connected with second control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the source electrode of said drive thin film transistors DTFT;
Said the 6th thin film transistor (TFT) T6, grid is connected with second control line, and source electrode is connected with the negative electrode of said OLED, and drain electrode is connected with the low level output terminal of said driving power;
The said second thin film transistor (TFT) T2, said the 3rd thin film transistor (TFT) T3 and said the 4th thin film transistor (TFT) T4 are n type thin film transistor (TFT), and said the first film transistor T 1, the 5th thin film transistor (TFT) T5 and said the 6th thin film transistor (TFT) T6 are p type thin film transistor (TFT);
The output voltage of the high level output terminal of said driving power is VDD, and the output voltage of the low level output terminal of said driving power is VSS;
The P point is the node that is connected with second end of said MM CAP Cs, and the G point is the node that is connected with first end of said MM CAP Cs.
As shown in Figure 8, the described pixel cell driving circuit of sixth embodiment of the invention is based on the described pixel cell driving circuit of fourth embodiment of the invention; In the described pixel cell driving circuit of sixth embodiment of the invention; Said first on-off element 20 is a first film transistor T 1; Said charging control unit 22 comprises the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4, and said driving control unit 21 comprises the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6;
Said the first film transistor T 1, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors DTFT, and source electrode is connected with the high level output terminal of driving power;
The said second thin film transistor (TFT) T2, grid is connected with first control line, and source electrode is connected with the low level output terminal of said driving power, and drain electrode is connected with second end of said MM CAP Cs;
Said the 3rd thin film transistor (TFT) T3, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors DTFT, and source electrode is connected with the grid of said drive thin film transistors DTFT;
Said the 4th thin film transistor (TFT) T4, grid is connected with first control line, and source electrode is connected with data line, and drain electrode is connected with the negative electrode of said OLED;
Said the 5th thin film transistor (TFT) T5, grid is connected with second control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the source electrode of said drive thin film transistors DTFT;
Said the 6th thin film transistor (TFT) T6, grid is connected with second control line, and source electrode is connected with the negative electrode of said OLED, and drain electrode is connected with the low level output terminal of said driving power;
The said second thin film transistor (TFT) T2, said the 3rd thin film transistor (TFT) T3 and said the 4th thin film transistor (TFT) T4 are n type thin film transistor (TFT), and said the first film transistor T 1, the 5th thin film transistor (TFT) T5 and said the 6th thin film transistor (TFT) T6 are p type thin film transistor (TFT);
The output voltage of the high level output terminal of said driving power is VDD, and the output voltage of the low level output terminal of said driving power is VSS;
The P point is the node that is connected with second end of said MM CAP Cs, and the G point is the node that is connected with first end of said MM CAP Cs.
Below in conjunction with the described pixel cell driving circuit of second embodiment of the invention as shown in Figure 4 its course of work is introduced:
As shown in Figure 9, during the described pixel cell drive circuit works of this second embodiment, the sequential chart of the output signal Vdata of the first control signal S1, the second control signal S2 and said data line;
Figure 10 A is the equivalent circuit diagram of the described pixel cell driving circuit of this second embodiment in very first time section;
Figure 10 B is the equivalent circuit diagram of the described pixel cell driving circuit of this second embodiment in second time period;
Figure 10 C is the equivalent circuit diagram of the described pixel cell driving circuit of this second embodiment in the 3rd time period;
Shown in Figure 10 A, in very first time section, i.e. the incipient stage, T1, T2, T3 all close; T4, T5, T6 are for opening, if a stage driving tube DTFT is a closed condition before this, then G point (node that promptly is connected with the grid of DTFT) is in vacant state, and the unlatching of T5; Will make unsettled G point current potential seriously drop-down, make DTFT open, if open before this by a stage itself for DTFT; Then can get into the duty in this stage, owing to opening of T4, DTFT is in the diode connection status; To MM CAP Cs charging, the current potential that makes G order raises data line gradually, up to G point current potential Vg=Vdata-Vth_oled-|Vth| through OLED, DTFT and T4; Then DTFT closes, P point (node that promptly is connected) current potential Vp=VSS with second end of said MM CAP, and the voltage difference at MM CAP Cs two ends is Vc=Vg-Vp=Vdata-Vth_oled-|Vth|-VSS; Wherein, Vth_oled is the luminous critical cross-pressure of OLED, and Vth is the threshold voltage of DTFT;
Shown in Figure 10 B, at second time period, i.e. buffer stage; T1 opens, and T2, T3, T4, T5, T6 close, and DTFT also closes; Be in the work halted state, because the switching of switch produces unnecessary noise, P point and G point are in vacant state to avoid; The voltage Vc at MM CAP Cs two ends is still constant, Vc=Vg-Vp=Vdata-Vth_oled-|Vth|-VSS;
Shown in Figure 10 C; In the 3rd time period; T4, T5, T6 close, and T1, T2, T3 open, and (Voled is the WV of OLED under the GTG for this reason to VDD-Voled because P point current potential is by the VSS saltus step; With Vth_oled and inconsistent); And the grid of DTFT is in vacant state, so the voltage jump of Vg is Vdata-Vth_oled-|Vth|-VSS+VDD-Voled, this moment DTFT source electrode and voltage difference Vsg=VDD-Voled-Vg=VDD-Voled-(the Vdata-Vth_oled-|Vth|-VSS+VDD-Voled)=VSS+Vth_oled+|Vth|-Vdata between the grid; DTFT works, and flows through electric current I=K (Vsg-|Vth|) of DTFT 2=K (VSS+Vth_oled+|Vth|-Vdata-|Vth|) 2=K (VSS+Vth_oled-Vdata) 2, OLED begins luminous, up to next frame; Wherein, K is the current coefficient of DTFT;
K = C ox × μ × W L ;
μ, C OX, W, L be respectively the field-effect mobility of DTFT, gate insulation layer unit-area capacitance, channel width, length;
It doesn't matter can to find to flow through the electric current I of DTFT and the threshold voltage vt h of DTFT, so can improve the homogeneity of electric current, reaches the even of brightness; Comprised Vth_oled and flow through simultaneously in the computing formula of electric current I of DTFT; Prolongation along with service time; OLED material aging luminescence efficiency descends; Vth_oled can rise, and the rising of Vth_oled makes the corresponding increase of working current, has so improved the panel luminance reduction that material aging causes.
Figure 11 A is the equivalent circuit diagram of the described pixel cell driving circuit of the 3rd embodiment in very first time section;
Figure 11 B is the equivalent circuit diagram of the described pixel cell driving circuit of the 3rd embodiment in second time period;
Figure 11 C is the equivalent circuit diagram of the described pixel cell driving circuit of the 3rd embodiment in the 3rd time period.
In the described pixel cell driving circuit of second embodiment of the invention; Vdata must be that the bigger negative voltage of absolute value just can make entire circuit luminous; Otherwise DTFT can't open; In the described pixel cell driving circuit of third embodiment of the invention, then should not limit, Vdata only needs less positive voltage that DTFT is opened and operate as normal.The time sequential routine of the described pixel cell driving circuit of second embodiment of the invention stands good in the described pixel cell driving circuit of third embodiment of the invention; The operation of circuit also is just the same; Just the described pixel cell driving circuit of third embodiment of the invention is when the 3rd time period; P point current potential is that (Voled is the WV of OLED under the GTG for this reason for VDD-Voled by the VDD saltus step; With Vth_oled and inconsistent), and the grid of DTFT is in vacant state), so G point current potential Vg saltus step is Vdata-Vth_oled-|Vth|-Voled; Thereby voltage difference Vsg=Vs-Vg=VDD-Voled-(the Vdata-Vth_oled-|Vth|-Voled)=VDD-Vdata+Vth_oled+|Vth| between the source electrode of DTFT and the grid flows through electric current I=K (Vsg-|Vth|) of DTFT 2=I=K (VDD-Vdata+Vth_oled) 2K is the current coefficient of DTFT;
K = C ox × μ × W L ;
μ, C OX, W, L be respectively the field-effect mobility of DTFT, gate insulation layer unit-area capacitance, channel width, length.
Shown in figure 12; Described pixel cell driving circuit of fifth embodiment of the invention and the described pixel cell driving circuit of sixth embodiment of the invention be in when work, the sequential chart of the output signal Vdata of the first control signal S1, the second control signal S2 and said data line.
The described pixel cell driving circuit of fifth embodiment of the invention is compared with the described pixel cell driving circuit of second embodiment of the invention; Just DTFT is become n type thin film transistor (TFT); And the anode of OLED moved to negative electrode; The course of work of circuit also is just the same, but the luminous problem that has aperture opening ratio in the end.
In the described pixel cell driving circuit of fifth embodiment of the invention; Vdata also must could open DTFT for bigger positive voltage; The described pixel cell driving circuit of sixth embodiment of the invention has then overcome this problem; In the described pixel cell driving circuit of sixth embodiment of the invention, Vdata only needs less positive voltage just can DTFT be opened, and makes the circuit operate as normal.
The operating process of the described pixel cell driving circuit of circuit the 5th embodiment of the present invention is following:
In very first time section, T2, T3, T4 open, and T1, T5, T6 close, Vg=Vdata+Vth_oled+Vth;
In second time period, T2, T3, T4, T5, T6 close, and T1 opens, the circuit buffering;
In the 3rd time period; T1, T5, T6 open, and T2, T3, T4 close, and Vp is VSS+Voled by the VDD saltus step; The Vg saltus step is Vdata+Vth_oled+Vth+VSS+Voled-VDD; The source potential Vs=VSS+Voled of DTFT, thereby the voltage difference Vsg=Vdata+Vth_oled+Vth-VDD between the grid of the source electrode of DTFT and DTFT flow through electric current I=K (Vsg-|Vth|) of drive thin film transistors DTFT 2=K (Vdata+Vth_oled-VDD) 2Wherein, K is the current coefficient of DTFT;
K = C ox × μ × W L ;
μ, C OX, W, L be respectively the field-effect mobility of DTFT, gate insulation layer unit-area capacitance, channel width, length.
The operating process of the described pixel cell driving circuit of circuit the 6th embodiment of the present invention is following:
In very first time section, T2, T3, T4 open, and T1, T5, T6 close, Vg=Vdata+Vth_oled+Vth;
In second time period, T2, T3, T4, T5, T6 close, and T1 opens, the circuit buffering;
In the 3rd time period, T1, T5, T6 open, and T2, T3, T4 close; Vp is VSS+Voled by the VSS saltus step, and the Vg saltus step is Vdata+Vth_oled+Vth+Voled, Vs=VSS+Voled; Vgs=Vdata+Vth_oled+Vth-VSS flows through electric current I=K (Vgs-|Vth|) of DTFT 2=K (Vdata+Vth_oled-VSS) 2Wherein, K is the current coefficient of DTFT;
K = C ox × μ × W L ;
μ, C OX, W, L be respectively the field-effect mobility of DTFT, gate insulation layer unit-area capacitance, channel width, length.
Than the described pixel cell driving circuit of second embodiment of the invention, the described pixel cell driving circuit of fifth embodiment of the invention; The described pixel cell driving circuit of third embodiment of the invention, the described pixel cell driving circuit of sixth embodiment of the invention have reduced the magnitude of voltage of data voltage Vdata; When having reduced the pixel cell drive circuit power consumption, also reduced the complexity of pixel cell driving circuit.
The maximum characteristics of pixel cell driving circuit of the present invention are the source electrode input of data voltage Vdata from DTFT; Utilize the diode of DTFT to connect self discharge with Vth (threshold voltage of DTFT); Vdata (data voltage); Vth_oled (the luminescence threshold voltage of OLED) deposits among the MM CAP Cs, the critical voltage of the drive thin film transistors of compensation OLED, and the drive current that utilizes the rising of voltage back coupling mechanism compensation OLED material aging critical voltage to cause simultaneously descends.
The present invention also provides a kind of pixel cell driving method, and it is applied to above-mentioned pixel cell driving circuit, and said pixel cell driving method may further comprise the steps:
The pixel charge step: charging control unit at first controlling and driving thin film transistor (TFT) is opened, and control charges to MM CAP, is increased to until the grid potential of drive thin film transistors to make said drive thin film transistors close;
The luminous step display of driving OLED: driving control unit is controlled said drive thin film transistors conducting and its grid is in vacant state, with the luminous demonstration of driving OLED and make the gate source voltage of said drive thin film transistors compensate the threshold voltage of said drive thin film transistors.
The present invention also provides a kind of pixel cell, comprises OLED and this first embodiment, this second embodiment and the described pixel cell driving circuit of the 3rd embodiment;
The source electrode of the drive thin film transistors that said pixel cell driving circuit comprises is connected with the negative electrode of said OLED; The anode of said OLED is connected with the high level output terminal of driving power through said driving control unit, and the drain electrode of said drive thin film transistors is connected with the low level output terminal of said driving power through said charging control unit.
The present invention also provides a kind of pixel cell, comprises OLED and the 4th embodiment, the 5th embodiment and the described pixel cell driving circuit of the 6th embodiment;
The source electrode of the drive thin film transistors that said pixel cell driving circuit comprises is connected with the anode of said OLED; The negative electrode of said OLED is connected with the low level output terminal of driving power through said charging control unit, and the drain electrode of said drive thin film transistors is connected with the high level output terminal of said driving power through said driving control unit.
More than explanation is just illustrative for the purpose of the present invention; And nonrestrictive, those of ordinary skills understand, under the situation of spirit that does not break away from accompanying claims and limited and scope; Can make many modifications, variation or equivalence, but all will fall in protection scope of the present invention.

Claims (10)

1. a pixel cell driving circuit is used for driving OLED, it is characterized in that, comprises drive thin film transistors, first on-off element, MM CAP, driving control unit and charging control unit, wherein,
The grid of said drive thin film transistors is connected with first end of said MM CAP, also is connected with the drain electrode of said drive thin film transistors through said charging control unit;
The source electrode of said drive thin film transistors is connected with said OLED, and is connected with second end of said MM CAP through said driving control unit;
The drain electrode of said drive thin film transistors is connected with driving power through said first on-off element;
Second end of said MM CAP Cs also is connected with said driving power through said charging control unit;
Said driving control unit also is connected with said OLED with said driving power respectively;
Said charging control unit also is connected with said OLED with data line respectively.
2. pixel cell driving circuit as claimed in claim 1 is characterized in that,
Said drive thin film transistors is a p type thin film transistor (TFT);
The source electrode of said drive thin film transistors is connected with the negative electrode of said OLED;
The drain electrode of said drive thin film transistors is connected with the low level output terminal of driving power through said first on-off element;
Second end of said MM CAP is connected with the low level output terminal of said driving power through said charging control unit.
3. pixel cell driving circuit as claimed in claim 2 is characterized in that,
Said first on-off element is the first film transistor, and said driving control unit comprises second thin film transistor (TFT) and the 3rd thin film transistor (TFT), and said charging control unit comprises the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the low level output terminal of said driving power, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said second thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the high level output terminal of said driving power, and drain electrode is connected with the anode of said OLED;
Said the 3rd thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the source electrode of said drive thin film transistors, and drain electrode is connected with second end of said MM CAP;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with first end of said MM CAP, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said the 5th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the low level output terminal of said driving power, and drain electrode is connected with second end of said MM CAP;
Said the 6th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the anode of said OLED, and drain electrode is connected with data line;
Said the first film transistor, said second thin film transistor (TFT) and said the 3rd thin film transistor (TFT) all are p type thin film transistor (TFT)s, and said the 4th on-off element, said the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are n type thin film transistor (TFT)s.
4. pixel cell driving circuit as claimed in claim 2 is characterized in that,
Said first on-off element is the first film transistor, and said driving control unit comprises second thin film transistor (TFT) and the 3rd thin film transistor (TFT), and said charging control unit comprises the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the low level output terminal of said driving power, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said second thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the high level output terminal of said driving power, and drain electrode is connected with the anode of said OLED;
Said the 3rd thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the source electrode of said drive thin film transistors, and drain electrode is connected with second end of said MM CAP;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with first end of said MM CAP, and source electrode is connected with the drain electrode of said drive thin film transistors;
Said the 5th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the high level output terminal of driving power;
Said the 6th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the anode of said OLED, and drain electrode is connected with data line;
Said the first film transistor, said second thin film transistor (TFT) and said the 3rd thin film transistor (TFT) all are p type thin film transistor (TFT)s, and said the 4th on-off element, said the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are n type thin film transistor (TFT)s.
5. pixel cell driving circuit as claimed in claim 1 is characterized in that,
Said drive thin film transistors is a n type thin film transistor (TFT);
The source electrode of said drive thin film transistors is connected with the anode of said OLED;
The drain electrode of said drive thin film transistors is connected with the high level output terminal of driving power through said first on-off element;
Second end of said MM CAP is connected with the high level output terminal of said driving power through said charging control unit.
6. pixel cell driving circuit as claimed in claim 5 is characterized in that,
Said first on-off element is the first film transistor, and said charging control unit comprises second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT), and said driving control unit comprises the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the high level output terminal of driving power;
Said second thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the high level output terminal of said driving power;
Said the 3rd thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the grid of said drive thin film transistors;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with data line, and drain electrode is connected with the negative electrode of said OLED;
Said the 5th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the source electrode of said drive thin film transistors;
Said the 6th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the negative electrode of said OLED, and drain electrode is connected with the low level output terminal of said driving power;
Said second thin film transistor (TFT), said the 3rd thin film transistor (TFT) and said the 4th thin film transistor (TFT) are n type thin film transistor (TFT), and said the first film transistor, the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are p type thin film transistor (TFT).
7. pixel cell driving circuit as claimed in claim 5 is characterized in that,
Said first on-off element is the first film transistor, and said charging control unit comprises second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT), and said driving control unit comprises the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT);
Said the first film transistor, grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the high level output terminal of driving power;
Said second thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with the low level output terminal of said driving power, and drain electrode is connected with second end of said MM CAP;
Said the 3rd thin film transistor (TFT), grid is connected with first control line, and drain electrode is connected with the drain electrode of said drive thin film transistors, and source electrode is connected with the grid of said drive thin film transistors;
Said the 4th thin film transistor (TFT), grid is connected with first control line, and source electrode is connected with data line, and drain electrode is connected with the negative electrode of said OLED;
Said the 5th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with second end of said MM CAP, and drain electrode is connected with the source electrode of said drive thin film transistors;
Said the 6th thin film transistor (TFT), grid is connected with second control line, and source electrode is connected with the negative electrode of said OLED, and drain electrode is connected with the low level output terminal of said driving power;
Said second thin film transistor (TFT), said the 3rd thin film transistor (TFT) and said the 4th thin film transistor (TFT) are n type thin film transistor (TFT), and said the first film transistor, the 5th thin film transistor (TFT) and said the 6th thin film transistor (TFT) are p type thin film transistor (TFT).
8. pixel cell driving method, it is applied to pixel cell driving circuit as claimed in claim 1, it is characterized in that, and said pixel cell driving method may further comprise the steps:
The pixel charge step: charging control unit at first controlling and driving thin film transistor (TFT) is opened, and control charges to MM CAP, is increased to until the grid potential of drive thin film transistors to make said drive thin film transistors close;
The luminous step display of driving OLED: driving control unit is controlled said drive thin film transistors conducting and its grid is in vacant state, with the luminous demonstration of driving OLED and make the gate source voltage of said drive thin film transistors compensate the threshold voltage of said drive thin film transistors.
9. a pixel cell is characterized in that, comprises OLED and like the described pixel cell driving circuit of arbitrary claim in the claim 1 to 4;
The source electrode of the drive thin film transistors that said pixel cell driving circuit comprises is connected with the negative electrode of said OLED; The anode of said OLED is connected with the high level output terminal of driving power through said driving control unit, and the drain electrode of said drive thin film transistors is connected with the low level output terminal of said driving power through said charging control unit.
10. a pixel cell is characterized in that, comprises OLED and like claim 1,5,6 or 7 described pixel cell driving circuits;
The source electrode of the drive thin film transistors that said pixel cell driving circuit comprises is connected with the anode of said OLED; The negative electrode of said OLED is connected with the low level output terminal of driving power through said charging control unit, and the drain electrode of said drive thin film transistors is connected with the high level output terminal of said driving power through said driving control unit.
CN201210047893.6A 2012-02-27 2012-02-27 Pixel unit driving circuit and method as well as pixel unit Active CN102708793B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201210047893.6A CN102708793B (en) 2012-02-27 2012-02-27 Pixel unit driving circuit and method as well as pixel unit
PCT/CN2012/084015 WO2013127189A1 (en) 2012-02-27 2012-11-02 Pixel unit driving circuit, pixel unit driving method and pixel unit

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CN113450695A (en) * 2020-05-07 2021-09-28 重庆康佳光电技术研究院有限公司 MicroLED pixel circuit, time sequence control method and display
CN113516942A (en) * 2020-05-14 2021-10-19 合肥联宝信息技术有限公司 Display control method and driving circuit

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WO2013127189A1 (en) * 2012-02-27 2013-09-06 京东方科技集团股份有限公司 Pixel unit driving circuit, pixel unit driving method and pixel unit
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CN104575393A (en) * 2015-02-03 2015-04-29 深圳市华星光电技术有限公司 AMOLED (active matrix organic light emitting display) pixel driving circuit and pixel driving method
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CN106531083A (en) * 2016-12-15 2017-03-22 上海天马有机发光显示技术有限公司 Pixel circuit compensation method, OLED display panel and compensation method thereof
CN108446051A (en) * 2018-03-16 2018-08-24 深圳市华星光电技术有限公司 Array substrate and touch control display apparatus
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CN113450695A (en) * 2020-05-07 2021-09-28 重庆康佳光电技术研究院有限公司 MicroLED pixel circuit, time sequence control method and display
CN113516942A (en) * 2020-05-14 2021-10-19 合肥联宝信息技术有限公司 Display control method and driving circuit
CN113516942B (en) * 2020-05-14 2022-05-13 合肥联宝信息技术有限公司 Display control method and driving circuit

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