CN102693977B

CN102693977B - The self-checkout gear of high voltage electrostatic discharge protective and manufacture method thereof

Info

Publication number: CN102693977B
Application number: CN201110072048.XA
Authority: CN
Inventors: 陈信良; 杜硕伦; 陈永初; 吴锡垣
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2011-03-22
Filing date: 2011-03-22
Publication date: 2015-09-30
Anticipated expiration: 2031-03-22
Also published as: CN102693977A

Abstract

The invention discloses the defensive self-checkout gear of high voltage static discharge (ESD) and manufacture method thereof.ESD protector can comprise a substrate, a N-type well region and a P type trap zone.N-type well region configuration corresponds to a Part I of substrate and has the N+ section that two are configured at its a surface.P type trap zone is configured to the Part II close to substrate and has a P+ section and a N+ section.Two N+ sections can spaced and each anode being associated to device.N+ section can be associated to a negative electrode of device.One contact site is configurable is connected to P+ section in the space between two N+ sections.Contact site can form a parasitic capacitance, and it is associated to a dead resistance of associating N+ section formation and provides self-sensing to protect use for high voltage ESD.

Description

The self-checkout gear of high voltage electrostatic discharge protective and manufacture method thereof

Technical field

Embodiments of the invention generally relate to semiconductor device and manufacture method thereof, and relate to the defensive self-checkout gear of a kind of high voltage static discharge (ESD) and manufacture method thereof especially.

Background technology

In the nearly all enforcement pattern manufactured at electronic installation at present, have one towards the ongoing trend of reduction means size.When less with larger two devices have ability identical in fact, less electronic installation tends to larger and huger electronic installation and comparatively receives an acclaim.Therefore, less element can be manufactured and will clearly tend to the production compared with dingus helping to merge those elements.But most Modern Electronic devices needs electronic circuit to perform actuation function (such as, switching device shifter) and data processing or other function determined.Using may not necessarily come practical about low voltage complementary formula metal-oxide semiconductor (MOS) (CMOS) technology of these dual-use functions.Therefore, high voltage (or high power) device is also developed to process most application, in this low voltage operating and impracticable.

Static discharge (ESD) performance of typical high voltage device often depends on overall width and laterally rule that is surperficial or corresponding device.Therefore, ESD performance may generally be come more crucial for comparatively dingus.High voltage device generally has the feature comprising low on-state resistance (Rdson), high-breakdown-voltage and low maintenance voltage.Low on-state resistance may be tended to during an esd event, makes an ESD electric current more likely concentrate on surface or the drain edge of a device.High electric current and high electric field may result in the physical destruction of a surperficial engaging zones of this kind of device.Based on the exemplary requirement of low on-state resistance, surperficial or horizontal rule seems to be increased.Therefore, ESD protection can be a challenge.

The high-breakdown-voltage feature of high voltage device generally means that puncture voltage is higher than operating voltage, and trigger voltage (Vtl) is higher than puncture voltage.Therefore, during an esd event, the internal circuit of high voltage device, before high voltage device conducting is used for ESD protection, may be in the risk of damage.The low maintenance voltage characteristic of high voltage device, does not also also solve the crest voltage or the relevant unnecessary noise of a surge voltage may be triggered or a locking may produce possibility in the normal operation period of being energized to.Because Electric Field Distribution may be responsive to distribution (routing), with the fact that ESD electric current can be made during an esd event may to concentrate on surface or drain edge, high voltage device also can experience field plate effect (field plate effect).

In order to improve the high voltage device performance being relevant to esd event, effective technology relates to the additional use of mask and other technique to build the diode of a large-size within two-carrier junction transistors (BJT) element, and/or increases the surface or laterally regular of MOS transistor.Other trial in order to improving SNR has comprised the use of outside ESD circuit for detecting.

Therefore, the structure developing a kind of improvement may be needed to provide ESD resistance.

Summary of the invention

Some embodiment therefore has about the defensive self-checkout gear of a kind of high voltage ESD.In some cases, ESD can be provided to protect by a self-checkout gear, self-checkout gear can by standard BCD (two-carrier complementary metal oxide semiconductors (CMOS) (BiCMOS) diffused metal oxide emiconductor (DMOS)) manufacture technics.In some embodiment, ESD protection can relate to a kind of EPI technique.

In an embodiment, provide a kind of high voltage static discharge (ESD) protector (be used in this " demonstration ", refer to " being used as example, example or an illustration ").High voltage ESD protector can comprise a substrate, a N-type well region and a P type trap zone.N-type well region configuration corresponds to a Part I of substrate and has the N+ section that two are configured at its a surface, and P type trap zone configures the Part II close to substrate and has a P+ section and a N+ section.Two N+ sections spaced and each section can be associated to an anode of device.N+ section can be associated to a negative electrode of device.One contact site is configurable is connected to P+ section in the space between two N+ sections.Contact site can form a parasitic capacitance, its dead resistance formed in conjunction with an associating N+ section, provides self-sensing to protect with high voltage ESD and uses.

In another embodiment, provide a kind of method.Method comprises following steps.One substrate is provided.One N-type well region is provided, is configured to the Part I corresponding to substrate and there is the N+ section that two are configured at its a surface.Spaced and each anode being associated to device of two N+ sections.One P type trap zone is provided, is configured to the Part II close to substrate and there is a P+ section and a N+ section.N+ section is associated to a negative electrode of device.There is provided a contact site to be configured in a space between two N+ sections and be connected to P+ section.Contact site forms a parasitic capacitance, its be formed at a dead resistance that N+ section associates and be connected and provide self-sensing to protect for high voltage ESD and use.

In order to have better understanding, preferred embodiment cited below particularly to above-mentioned and other side of the present invention, and coordinating institute's accompanying drawings (not necessarily according to scale), being described in detail below.

Accompanying drawing explanation

Fig. 1 display may be utilized in the calcspar of the exemplary circuit of typical ESD detecting structure.

The calcspar that Fig. 2 shows may be utilized to provide ESD protection of a kind of foundation one embodiment and do not need the exemplary circuit of outer member.

Fig. 3 shows use one self-sensing ESD device to the profile of the structure of the embodiment providing high voltage ESD to protect.

Fig. 4 shows use one self-sensing ESD device to the profile of the structure of the alternate embodiment providing high voltage ESD to protect.

Fig. 5 display is about the vertical view of the illustration layout of the embodiment of Fig. 3.

Fig. 6 display is about the vertical view of the illustration layout of the embodiment of Fig. 4.

Fig. 7 display provides the high pressure ESD method of protector.

[main element symbol description]

10: outside ESD circuit for detecting

12: electric capacity

14: resistance

16: trigger input

20:ESD device

30:ESD device

40: parasitic capacitance

42: dead resistance

50:P shaped material substrate or P type epitaxially grown layer

52:N+ buried horizon

54:N type trap

56:P type trap

60: anode

62: negative electrode

70,72,74,76:N+ section

80,82:P+ section

84,86: field oxide film (FOX)

88:N+ section

90: oxide layer

92: contact site

100: parasitic capacitance

110、112、114、116：BJT

120: dead resistance

140:N+ section

144: dead resistance

150: contact site

152: oxide-film

200,210,220,230,240: step

Embodiment

Some embodiment of the present invention will be described with reference to accompanying drawing more completely now, in wherein showing some and not all embodiments of the present invention.Really, various embodiment of the present invention multiple different pattern can be specialized and should not be construed as limited to the embodiment being set forth in this; Otherwise providing of these embodiments to make this disclosure meet the legal provisions be suitable for.

Some embodiment of the present invention can provide a kind of BCD technique, in order to provide the defensive self-checkout gear of high voltage ESD.In addition, some embodiment can provide this protection and not need additional masks or technique.Therefore, for example, the removable demand with outside ESD protection circuit of some embodiment.

Fig. 1 display may be utilized in the calcspar of the exemplary circuit of typical ESD detecting structure.As shown in Figure 1, a kind of known structure can adopt a kind of outside ESD circuit for detecting 10, and it is positioned at the outside of an ESD device 20 but is also connected to ESD device 20 and protects to provide ESD.Outside ESD circuit for detecting can comprise electric capacity 12 and a resistance 14, its be connected to one another at treat protector (such as, between the anode and negative electrode of protector) terminal between.As shown in Figure 1, outside ESD circuit for detecting 10 provides trigger input 16 to an ESD device 20 to trigger ESD protection.Therefore, in order to provide the structure of Fig. 1, outer member must be used to set up trigger input 16 to trigger ESD device 20.

In order to avoid using external structure, some embodiment can adopt the structure being shown in Fig. 2.Fig. 2 display may be utilized to provide ESD protect and do not need the calcspar of the exemplary circuit of outer member.So, Fig. 2 shows the defensive self-checkout gear of a kind of high voltage ESD.The self-sensing structure of Fig. 2 also may be employed in treat protector terminal (such as, anode and negative electrode) between, but can provide a circuit for detecting within a device.As shown in Figure 2, an ESD device 30 can be provided in conjunction with a parasitic capacitance 40 and a dead resistance 42.ESD device 30 more can comprise two-carrier junction transistors (BJT), such as a NPN BJT, to form a kind of protection circuit not needing outer member.Therefore, for example, do not need an External input terminals to trigger ESD device 30.The substitute is, ESD device 30 is triggered by entirety by the function of inner member (in the case, setting parasitic capacitance 40 and the dead resistance 42 of the triggering of the operation of ESD device 30).Therefore, the metal wiring manufacturing a high voltage switching device shifter can be reduced, and also can reduce ESD device layout area.In addition, some embodiment finally may become quite insensitive to distribution subject under discussion, and possibly cannot be subject to field plate effect.Embodiment also can have a gross area, and it can be less than the use combining and have the BJT of identical ESD performance characteristic or the diode of metal-oxide semiconductor (MOS) (MOS).

In this, some embodiment can provide the quite undersized structure of one to protect use for high voltage ESD.In addition, some embodiment can provide this structure make it be included within a self-checkout gear but not rest against outer member.Therefore, can be high voltage device in circuit provides high voltage ESD to protect.But some embodiment also can be useful to low voltage application.In this, for example, during general DC circuit operation, also can detect energising crest voltage and the surge voltage of noise induction generation, and not need outer member.Embodiment also can have one close to the puncture voltage and of high voltage device operating voltage lower than the trigger voltage of high voltage device puncture voltage.Moreover a quite high maintenance voltage can be provided, can more easily avoid locking to occur compared to utilizing a thyristor (SCR).In some cases, embodiment can provide standard BCD technique, and it does not need mask or the technique of extra increase number.

Fig. 3 shows use one self-sensing ESD device to improve the profile of the structure of the embodiment of voltage ESD protection.As seen from Figure 3, a P-type material substrate or a P type epitaxially grown layer (epitaxially-grown P-layer; P-EPI) 50 configuration N+ buried horizon 52 thereon can be provided with.One N-type trap 54 is configurable on outward flange to surround a P type trap 56.The anode 60 of device can be associated to N-type trap 54 via the N+ section 70,72,74 and 76 of correspondence.In an embodiment, each N-type trap 54 can have two respective N+ sections (such as, N+ section 70 and 72 and N+ section 74 and 76).N+ section is separated with 82 with other P+ section 80 individual by field oxide film (FOX) 84, and field oxide film (FOX) 84 may correspond to the edge between N-type trap 54 and P type trap 56.Another group FOX element (such as, FOX 86) configurable in a surface of device P+ section 80,82 to be located away from a N+ section 88 of the negative electrode 62 corresponding to device.

As shown in Figure 3, between an oxide layer 90 and the configurable N+ section in being associated to N-type trap 54 of contact site 92.Therefore, for example, oxide layer 90 and contact site 92 configurable between N+ section 70 and 72 and between N+ section 74 and 76.Oxide layer 90 and contact site 92 can be connected to P+ section 80 and 82, and thus corresponding P+ section 80 and 82 can be connected to the base stage of BJT 110,112,114 and 116.In each N-type trap 54 with corresponding N+ section (such as, section 70 and 72 or section 74 and 76), a parasitic capacitance 100 can be formed between oxide layer 90 and contact site 92.One dead resistance 120 also can be formed at P+ section 80 and 82 and be connected between the N+ section 88 of negative electrode 62.Therefore, the knot between parasitic capacitance 100 and dead resistance 120 can be located in the base stage of each BJT 110,112,114 and 116.Each BJT 110,112,114 with 116 collector can be communicated with anode 60 with 76 via N+ section 70,72,74, and each BJT 110,112,114 with 116 emitter-base bandgap grading can be communicated with negative electrode 62 via N+ section 88.Therefore, when needs ESD protects, parasitic capacitance 100 and dead resistance 120 can set a voltage in the base stage of BJT 110,112,114 and 116, to trigger ESD protection, and do not need to use any external circuit elements to provide this triggering.

Fig. 4 shows use one self-sensing ESD device to the profile of the structure of the alternate embodiment providing high voltage ESD and protect.Do not need outer member about setting ESD protection, the embodiment of Fig. 4 is the example being similar to Fig. 3.In addition, about most architectural feature, the structure of the example of Fig. 4 also similar Fig. 3.The N+ section 88 that some exceptions comprise Fig. 3 is divided into the fact of the N+ section 140 of the distribution of Fig. 4.The dead resistance 144 of Fig. 4 is the contact site 150 between the N+ section 140 by being configured at each distribution and the formation of corresponding oxide-film 152, and is arranged between each N+ section 140 distributed.Contact site 150 and 92 is also connected to each other and is connected to the negative electrode 62 of Fig. 4.Although there is the difference of these structures, the example of Fig. 4 also utilizes parasitic capacitance 100 and dead resistance 144 to set a voltage and protects to trigger ESD in the base stage of BJT 110,112,114 and 116, and does not need to use any external circuit elements to provide this triggering.

Fig. 5 shows the vertical view of the illustration layout of the embodiment of above-mentioned Fig. 3.Meanwhile, Fig. 6 shows the vertical view of the illustration layout of the embodiment of above-mentioned Fig. 4.Each illustration layout provides the defensive self-checkout gear of a kind of high voltage ESD, and it can be applied to any technique and be subjected to any operating voltage.Embodiment also can by standard BCD manufacture technics, and not need to use additional masks.In certain embodiments, removable N+ buried horizon 52, and embodiment can be applied to a twin well process.Some embodiment also can be applied to the non-EPI technique with triple-well process, or in single poly process.

Fig. 7 display provides the high pressure ESD method of protector.As shown in Figure 7, method can be included in step 200 and provide substrate.Method can more be included in step 210 and provide N-type well region, is configured to the Part I corresponding to substrate and has the N+ section that two are configured at its a surface.Two N+ sections can spaced and each anode being associated to device.Method can more be included in step 220 and provide P type trap zone, is configured to the Part II close to substrate and has P+ section and N+ section.N+ section can be associated to the negative electrode of device.In an embodiment, method more can be included in the space that step 230 provides contact site to be configured between two N+ sections and to be connected to P+ section.Contact site can form parasitic capacitance, its be formed at dead resistance that N+ section associates and be connected and provide self-sensing to protect for high voltage ESD in response to esd event and use.In certain situation, method can comprise other optional step (being shown in the dotted line in Fig. 7).For example, in some embodiments, method more can be included in step 240 provides the N+ buried horizon that adulterates to be configured between substrate and N-type well region and P type trap zone.

Be set forth in this most variation of the present invention and other embodiment, the benefit with the instruction being presented in above-mentioned explanation and correlative type will be understood for those skilled in the art.Therefore, we it will be appreciated that the present invention is not limited to disclosed specific embodiment, and variation and other embodiment are intended to be comprised within the category of the right of enclosing.In addition, although above-mentioned explanation and correlative type are illustrated in certain and illustrate embodiment in the context of element and/or the function combined, but we should understand that the element of various combination and/or function under the category not deviating from the right of enclosing, can be provided by alternate embodiment.In this, for example, be different from the element of those combination of above-mentioned detailed description and/or function also to consider to be set forth in some of the right of enclosing.Although adopt specific term in this, their use only has common name and descriptive cognition and unrestriced object.

In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.There is usual knowledge in the technical field of the invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.

Claims

1. an electrostatic discharge protective device, comprises:

One substrate;

One N-type well region, is configured to correspond to a Part I of this substrate and has the N+ section that two are configured at its a surface, the spaced and each anode being associated to this device of these two N+ sections;

One P type trap zone, be configured to the Part II corresponding to this substrate and have a P+ section and a N+ section, this N+ section is associated to a negative electrode of this device,

Wherein this Part II is positioned at the centre of this substrate, this Part I is positioned at the both sides of this Part II, one contact site is configured in a space between two N+ sections of this N-type well region and is connected to this P+ section, this contact site forms a parasitic capacitance, and the dead resistance that itself and this N+ section being formed at this P type trap zone associate is connected and provides self-sensing to protect for high voltage ESD to be used.

2. electrostatic discharge protective device according to claim 1, wherein this N-type well region comprises two parts be configured on the opposite side of this P type trap zone.

3. electrostatic discharge protective device according to claim 1, more comprise a N+ and to adulterate buried horizon, it is configured between this substrate and this N and P type trap zone.

4. electrostatic discharge protective device according to claim 1, wherein this dead resistance is formed between this N+ section of this P type trap zone and this P+ section.

5. electrostatic discharge protective device according to claim 1, this N+ section being wherein associated to this negative electrode is scattered in multiple N+ district.

6. electrostatic discharge protective device according to claim 5, wherein this dead resistance is between each of those N+ districts of the N+ section being formed at this distribution.

7. electrostatic discharge protective device according to claim 6, more comprises multiple contact site, its be arranged at correspond to this dead resistance those N+ districts each between multiple spaces in.

8. electrostatic discharge protective device according to claim 5, wherein this P+ section and this contact site are also associated to this negative electrode.

9. electrostatic discharge protective device according to claim 1, wherein multiple two-carrier junction transistors is formed in this device to protect to provide this high voltage ESD with the triggering that should provide in this parasitic capacitance and this dead resistance, and do not need outer member.

10. electrostatic discharge protective device according to claim 1, wherein this device does not need manufactured by additional masks via a standard technology.

11. electrostatic discharge protective devices according to claim 1, wherein this substrate comprises P type substrate material.

12. electrostatic discharge protective devices according to claim 1, wherein this substrate comprises the P-type material that extension is formed.

13. 1 kinds of methods manufacturing electrostatic discharge protective device, comprise:

One substrate is provided;

One N-type well region is provided, is configured to correspond to a Part I of this substrate and there is the N+ section that two are configured at its a surface, the spaced and each anode being associated to this device of these two N+ sections;

One P type trap zone is provided, be configured to the Part II corresponding to this substrate and there is a P+ section and a N+ section, this N+ section is associated to a negative electrode of this device, and wherein this Part II is positioned at the centre of this substrate, and this Part I is positioned at the both sides of this Part II; And

There is provided a contact site to be configured in a space between two N+ sections of this N-type well region and be connected to this P+ section, this contact site forms a parasitic capacitance, and the dead resistance that itself and this N+ section being formed at this P type trap zone associate is connected and provides self-sensing to protect for high voltage ESD to be used.

14. methods according to claim 13, wherein providing this N-type well region to comprise provides two parts be configured on the opposite side of this P type trap zone.

15. methods according to claim 13, more comprise and provide a N+ to adulterate buried horizon between this substrate and this N-type well region and this P type trap zone.

16. methods according to claim 13, wherein this dead resistance is formed between this N+ section of this P type trap zone and this P+ section.

17. methods according to claim 13, this N+ section being wherein associated to this negative electrode is scattered in multiple N+ district.

18. methods according to claim 17, wherein this dead resistance is between each of those N+ districts of the N+ section being formed at this distribution.

19. methods according to claim 18, more comprise provide multiple contact site in correspond to this dead resistance those N+ districts each between multiple spaces in.

20. methods according to claim 13, wherein multiple two-carrier junction transistors is formed in this device to protect to provide this high voltage ESD with the triggering that should provide in this parasitic capacitance and this dead resistance, and do not need outer member.