CN102693197A - Method for calculating minimum unit of read strobe enable fine tuning register of memory controller - Google Patents
Method for calculating minimum unit of read strobe enable fine tuning register of memory controller Download PDFInfo
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- CN102693197A CN102693197A CN2012101383187A CN201210138318A CN102693197A CN 102693197 A CN102693197 A CN 102693197A CN 2012101383187 A CN2012101383187 A CN 2012101383187A CN 201210138318 A CN201210138318 A CN 201210138318A CN 102693197 A CN102693197 A CN 102693197A
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Abstract
Aiming to realize configuration of a read strobe enable register, the invention discloses a method for calculating a minimum unit of a read strobe enable fine tuning register of a memory controller. A fundamental theory utilized by the calculating method of the invention is that the memory controller sends out postponing time of a read command, wherein the postponing time equals latest opportunity postponing time of the corresponding memory controller read strobe enable. The method of the invention comprises the steps of: calculating configurable maximum values of the read strobe enable fine tuning register under conditions of different clock signal postponing values firstly, then adopting the theory for calculation to a final result. According to the invention, some DDR3 memory controllers that have not been given a specific value of a minimum unit of a read strobe enable fine tuning register are enabled to finish the configuration of read strobe enable opportunity.
Description
Technical field
The present invention relates to the Memory Controller Hub field of computing machine, especially DDR3 Memory Controller Hub read gate enables to finely tune the minimum unit computing method of register.
Background technology
In Double Data Rate 2 (DDR2), on the internal memory module, clock signal (Clock), address signal, command signal and control signal adopt T type cabling mode.In the printing board PCB design, strict isometric between data set and the data set.In read operation, Memory Controller Hub sends after the read command, can arrive each memory chip on the main memory access simultaneously; Each memory chip is received read command, sends at interval data strobe signal after the identical time, and finally the data strobe signal that sends of each memory chip can arrive Memory Controller Hub simultaneously.Like this, Memory Controller Hub just can be configured to the read gate of each data set the opportunity of enabling equal values.Therefore in the register design of the Memory Controller Hub of DDR2, have only a read gate to enable the coarse adjustment register usually, and do not have read gate to enable to finely tune register, and unified all data sets of configuration.
In Double Data Rate 3 (DDR3), on the internal memory module, clock signal, address signal, command signal and control signal adopt and leap bus (Fly-By Bus) cabling mode.The design of this cabling mode, in read operation, Memory Controller Hub sends after the read command, on the same main memory access each memory chip receive the time point of read command maybe be all different.The memory chip that leaps bus cabling elder generation process receives read command at first, and this memory chip can send data at first; In like manner, last memory chip of process is received read command at last, and this memory chip can send data at last.That is to say, the corresponding memory chip of each data set in the read operation on the same passage, the data of sending possibly can reach Memory Controller Hub at the different time point respectively.Therefore Memory Controller Hub must be provided with the read gate enable register to each data set separately, and the read gate enable register of DDR3 enables coarse adjustment register and read gate by read gate usually and enables to finely tune register and form jointly.
In DDR3, Memory Controller Hub is to carry out coarse adjustment by read gate being enabled the coarse adjustment register to the configuration of the read gate enable register of individual data group, then read gate is enabled to finely tune register and finely tunes common accomplish.The common stride of coarse adjustment is bigger, and read gate enables the minimum unit (T of coarse adjustment register
G0), be generally 1/2 clock period or 1/4 clock period; It is less to finely tune common stride, and read gate enables to finely tune the minimum unit (T of register
F0), be generally 1/64 clock period or 1/128 clock period.In the Memory Controller Hub register design, read gate enables to finely tune the maximal value that register can be provided with and is generally equal to the minimum unit value that read gate enables the coarse adjustment register.Like this, the value of read gate enable register can dispose arbitrarily.
Memory Controller Hub is to the configuration of the read gate enable register of individual data group, and current in the industry way is, with the value of read gate enable register by a very big value, to reduce the minimum unit (T that read gate enables to finely tune register at every turn
F0) stride, reduce one by one to do experiment, be tested to very little value always.It correctly is decision condition that the value of writing into this data set reads out, read gate enable register maximal value and minimum value that statistics satisfies condition, with the arithmetic mean of maximal value and minimum value as this data set read gate enable register end value.But in some DDR3 Memory Controller Hub, read gate enables the minimum unit (T of coarse adjustment register
G0) be known, but read gate enables to finely tune the minimum unit (T of register
F0) be unknown, promptly in the Memory Controller Hub relevant documentation and undeclared read gate enable to finely tune the minimum unit (T of register
F0) concrete size, only explain that this minimum unit is a set time length value and irrelevant with the clock period, this makes read gate enable the difficulty that is configured as on opportunity.
Summary of the invention
In order to address the above problem; Enable to finely tune the unknown DDR3 Memory Controller Hub of minimum unit of register to read gate; The invention provides the minimum unit computing method that a kind of Memory Controller Hub read gate enables to finely tune register, to accomplish configuration to the read gate enable register.The principle of utilization of the present invention is that Memory Controller Hub sends the time that read command is postponed, and equals the time of postponing on opportunity the latest that correspondence memory controller read gate enables.
The inventive method mainly comprises the steps:
(1) in passage, selects a data set at random, be used for testing;
(2) read gate enables the coarse adjustment register and is set to (CL+1) * T
CK, wherein CL is the logical time-delay of column selection, T
CKBe the clock period;
(3) delay register of the employed clock signal of memory chip at this data set place is set to 0, and the delay register minimum unit value of clock signal is T
C0
(4) delay value of calculating clock signal is set at 0 o'clock, and read gate enables to finely tune the configurable maximal value 0 of register
MAX, this moment, read gate enable register maximal value was (CL+1) * T
CK+ 0
MAX* T
F0, T wherein
F0Enable to finely tune the minimum unit of register for read gate;
(5) delay register of the employed clock signal of memory chip at this data set place is set to N;
When (6) delay value of calculating clock signal was set to N, read gate enabled to finely tune the configurable maximal value N of register
MAX, this moment, read gate enable register maximal value was (CL+1) * T
CK+ N
MAX* T
F0
When the delay register of (7) establishing clock signal became N by 0, Memory Controller Hub sent the time retardation T of read command
D, i.e. T
D=N* T
C0, the opportunity the latest that the Memory Controller Hub read gate enables also can corresponding postponement T
D, then have:
T
D?=?{（CL+1）*?T
CK?+N
MAX*?T
F0}-{（CL+1）*?T
CK?+0
MAX*?T
F0}=T
F0*(?N
MAX?-0
MAX)；
Therefore obtain N* T
C0=T
F0* (N
MAX-0
MAX);
Thereby T
F0=N* T
C0/ (N
MAX-0
MAX).
Further, said read gate enables to finely tune the configurable maximal value 0 of register
MAXWith N
MAXComputing method be:
(1) read gate that this data set is corresponding enables to finely tune register value and is set to 0;
(2) send write operation;
(3) send read operation again and go the value reading just to write into;
(4) whether correct in inspection if reading out this data set respective value;
(5) read gate that this data set is corresponding enables to finely tune register value and increases one by one, increases 1 at every turn, enables to finely tune that register itself can be provided with and effective maximal value M until read gate; Whenever establish a read gate and enable to finely tune register value, execution in step (2) is to (4);
(6) write into to satisfy this data set respective value that to read out be condition correctly again, the read gate that obtains this data set enables to finely tune the configurable maximal value of register.
Further, the value of said N should satisfy N
MAXLess than M.
The present invention is through enabling to finely tune the calculating of register minimum unit to read gate, the DDR3 Memory Controller Hub that makes some directly not provide this minimum unit occurrence also can be accomplished the configuration that read gate enables opportunity, and makes configuration result more accurate.
Description of drawings
Fig. 1 is the computing method schematic flow sheet that read gate enables to finely tune the minimum unit of register.
Fig. 2 is that read gate enables to finely tune register Computation of Maximal Waiting method flow synoptic diagram.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
The ultimate principle that the inventive method is used is, Memory Controller Hub early sends read command to the internal memory module, and the data that from memory chip, read out will early arrive Memory Controller Hub; Memory Controller Hub sends read command to the internal memory module evening, and the data that from memory chip, read out will arrive Memory Controller Hub evening.In the inventive method, utilize Memory Controller Hub to send the time that read command is postponed, equal time of postponing on opportunity the latest that correspondence memory controller read gate enables, also equal the time of postponing on opportunity the earliest that correspondence memory controller read gate enables.Here, the opportunity the latest that read gate enables, the maximal value of corresponding read gate enable register; The opportunity the earliest that read gate enables, the minimum value of corresponding read gate enable register.The inventive method utilizes Memory Controller Hub to send the time that read command is postponed, and equals the time of postponing on opportunity the latest that correspondence memory controller read gate enables.Suppose Memory Controller Hub is sent the time retardation T of read command
D, the data sent of memory chip will be postponed T so
DArrive Memory Controller Hub, the opportunity the latest that correspondence memory controller read gate enables also can corresponding postponement T
D
As shown in Figure 1, enable to finely tune the minimum unit of register in order to try to achieve the Memory Controller Hub read gate, the inventive method step is following:
(1) in passage, selects a data set at random, be used for testing;
(2) read gate enables the coarse adjustment register and is set to (CL+1) * T
CK, wherein CL is the logical time-delay of column selection (CAS Latency), T
CKBe the clock period;
(3) delay register of the employed clock signal of memory chip at this data set place is set to 0, and the delay register minimum unit of clock signal (Clock) is T
C0
(4) enable to finely tune register Computation of Maximal Waiting method according to read gate, the delay value that obtains clock signal (Clock) is set at 0 o'clock, and it is 0 that read gate enables to finely tune the configurable maximal value of register
MAX, this moment, read gate enable register maximal value was (CL+1) * T
CK+ 0
MAX* T
F0
(5) delay register of the employed clock signal of memory chip (Clock) at this data set place is set to N;
(6) enable to finely tune register Computation of Maximal Waiting method according to read gate, when the delay value that obtains clock signal (Clock) was set to N, it was N that read gate enables to finely tune the configurable maximal value of register
MAX, this moment, read gate enable register maximal value was (CL+1) * T
CK+ N
MAX* T
F0
(7) calculate the minimum unit (T that read gate enables to finely tune register
F0) size, according to the ultimate principle of the inventive method, suppose Memory Controller Hub is sent the time retardation T of read command
D, the data sent of memory chip will be postponed T so
DArrive Memory Controller Hub, the opportunity the latest that correspondence memory controller read gate enables also can corresponding postponement T
D
(a) delay register of clock signal (Clock) becomes N by 0, and according to register description, the minimum unit value of the delay register of clock signal (Clock) is T
C0, so if Memory Controller Hub sends the time retardation T of read command
D, i.e. T
D=N* T
C0, the opportunity the latest that correspondence memory controller read gate enables also can corresponding postponement T
D, then have:
T
D?=?{（CL+1）*?T
CK?+N
MAX*?T
F0}-{（CL+1）*?T
CK?+0
MAX*?T
F0}=T
F0*(?N
MAX?-0
MAX)；
(b) therefore obtain N* T
C0=T
F0* (N
MAX-0
MAX);
(c) so, read gate enables to finely tune the minimum unit T of register
F0For:
T
F0=N*?T
C0/?(?N
MAX-0
MAX)。
When the inventive method selects data set to be used for testing in step (1), be not strict with, can carry out correlation test by data set of picked at random.
In step (2), read gate enables the coarse adjustment register and is set to (CL+1) * T
CKReason be, read gate enable the time computes starting point be to send the read command signal.According to the definition of solid state technology association (JEDEC), confidential being selected in read to prepare in (Read Preamble) process when the Memory Controller Hub read gate enabled.That is to say, the maximal value of read gate enable register, the time corresponding point is exactly the time that data-signal (DQ) arrives Memory Controller Hub.Describe below from Memory Controller Hub and send read command arrives Memory Controller Hub to data-signal process: at first the Memory Controller Hub read command of sending is through chip time-delay (comprising Memory Controller Hub and memory chip internal delay time), and arrives memory chip after the time-delay of printed circuit board (pcb) cabling; Memory chip is at CL* T
CKSend data-signal afterwards, data-signal arrives Memory Controller Hub after the time-delay through chip time-delay (comprising Memory Controller Hub and memory chip internal delay time) and printed circuit board traces once more.Comprehensive above factor, read gate enables the coarse adjustment register and is set to (CL+1) * T
CKCertainly in actual debug process; If enabling the coarse adjustment register, this read gate is provided with down; Read gate enables to finely tune in the process of register maximum value calculation, all values occurs and all can not satisfy this data set respective value and write into and read out under the correct situation again, and it is big or turn the minimum unit of a coarse adjustment register down to consider that then read gate is enabled the corresponding accent of coarse adjustment register value.
Fig. 2 shows read gate and enables after the coarse adjustment register sets, and read gate enables to finely tune the maximal value of register and confirms method.As shown in Figure 2, concrete steps are following:
(1) read gate that this data set is corresponding enables to finely tune register value and is set to 0;
(2) send write operation;
(3) send read operation again and go the value reading just to write into;
(4) whether correct in inspection if reading out this data set respective value;
(5) read gate that this data set is corresponding enables to finely tune register value and increases one by one, increases 1 at every turn, until M value (the M value be read gate enable to finely tune register itself can be provided with and effective maximal value); Whenever establish a read gate and enable to finely tune register value, execution in step (2) is to (4);
(6) write into to satisfy this data set respective value that to read out correctly be condition again, the read gate that obtains this data set at last enables to finely tune the configurable maximal value of register.
Among the present invention, N
MAXWith 0
MAXAll be that read gate enables to finely tune the maximal value of register under certain specified conditions, and should satisfy between the M value: 0≤0
MAX＜N
MAX＜M; Wherein, N
MAXCan not equal M, work as N
MAXWhen equaling M, explain that meeting with read gate enables to finely tune that register itself can be provided with and effective maximum value boundary, this moment N
MAXInvalid.
In addition, N should also will satisfy N when value
MAX＜M, and the N value had better not be too little, otherwise can cause bigger error.
Claims (3)
1. a Memory Controller Hub read gate enables to finely tune the minimum unit computing method of register, comprises the steps:
(1) in passage, selects a data set at random, be used for testing;
(2) read gate enables the coarse adjustment register and is set to (CL+1) * T
CK, wherein CL is the logical time-delay of column selection, T
CKBe the clock period;
(3) delay register of the employed clock signal of memory chip at this data set place is set to 0, and the delay register minimum unit value of clock signal is T
C0
(4) delay value of calculating clock signal is set at 0 o'clock, and read gate enables to finely tune the configurable maximal value 0 of register
MAX, this moment, read gate enable register maximal value was (CL+1) * T
CK+ 0
MAX* T
F0, T wherein
F0Enable to finely tune the minimum unit of register for read gate;
(5) delay register of the employed clock signal of memory chip at this data set place is set to N;
When (6) delay value of calculating clock signal was set to N, read gate enabled to finely tune the configurable maximal value N of register
MAX, this moment, read gate enable register maximal value was (CL+1) * T
CK+ N
MAX* T
F0
When the delay register of (7) establishing clock signal became N by 0, Memory Controller Hub sent the time retardation T of read command
D, i.e. T
D=N* T
C0, the opportunity the latest that the Memory Controller Hub read gate enables also can corresponding postponement T
D, then have:
T
D?=?{（CL+1）*?T
CK?+N
MAX*?T
F0}-{（CL+1）*?T
CK?+0
MAX*?T
F0}=T
F0*(?N
MAX?-0
MAX)；
Therefore obtain N* T
C0=T
F0* (N
MAX-0
MAX);
Thereby T
F0=N* T
C0/ (N
MAX-0
MAX).
2. method according to claim 1 is characterized in that said read gate enables to finely tune the configurable maximal value 0 of register
MAXWith N
MAXComputing method be:
(1) read gate that this data set is corresponding enables to finely tune register value and is set to 0;
(2) send write operation;
(3) send read operation again and go the value reading just to write into;
(4) whether correct in inspection if reading out this data set respective value;
(5) read gate that this data set is corresponding enables to finely tune register value and increases one by one, increases 1 at every turn, enables to finely tune that register itself can be provided with and effective maximal value M until read gate; Whenever establish a read gate and enable to finely tune register value, execution in step (2) is to (4);
(6) write into to satisfy this data set respective value that to read out be condition correctly again, the read gate that obtains this data set enables to finely tune the configurable maximal value of register.
3. method according to claim 2 is characterized in that the value of said N should satisfy N
MAXLess than M.
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Cited By (1)
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| CN112468803A (en) * | 2020-11-06 | 2021-03-09 | 昆山丘钛光电科技有限公司 | Exposure calibration method, device, equipment and medium for camera module |
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