CN102684625B - Signal amplifying system and signal amplifying method - Google Patents
Signal amplifying system and signal amplifying method Download PDFInfo
- Publication number
- CN102684625B CN102684625B CN201210183028.4A CN201210183028A CN102684625B CN 102684625 B CN102684625 B CN 102684625B CN 201210183028 A CN201210183028 A CN 201210183028A CN 102684625 B CN102684625 B CN 102684625B
- Authority
- CN
- China
- Prior art keywords
- amplification
- signal
- control
- amplifying
- cpld
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
Abstract
The invention relates to the technical field of signal amplification, and discloses a signal amplifying system and a signal amplifying method. The signal amplifying system comprises a complex programmable logic device (CPLD) and a sectional amplifying circuit, wherein the CPLD is used for transmitting an amplifying control instruction; and the sectional amplifying circuit is used for receiving a signal to be amplified and an amplifying control instruction sent from the CPLD, and sectionally amplifying the signal to be amplified by corresponding times according to the amplifying control instrument. The signal amplifying method comprises the steps as follows: sending the amplifying control instruction via the CPLD; and receiving and analyzing the amplifying control instruction according to the sectional amplifying circuit, and amplifying the signal to be amplified by the corresponding times according to the analyzed amplifying control instruction. According to the invention, the whole sectional amplifying circuit is controlled by the CPLD, and the CPLD is a logic device, and the control data of the CPLD is preset, therefore, the operation speed of the CPLD is faster than the operation speed controlled by a single-chip with a program, the amplifying efficiency of signal is improved.
Description
Technical field
The present invention relates to signal amplification technique field, especially relate to a kind of signal amplifying system and amplification method thereof.
Background technology
At present, signal amplifies is all generally adopt single-chip programming control amplifier.In this amplifier, the step of being amplified by the program control signal installed in single-chip microcomputer.
But because all control processes all will be run on single-chip microcomputer, expend the more time, therefore, each amplification cycle all can expend the more time, causes the shortcoming that signal amplification efficiency is low.
Summary of the invention
The present invention proposes a kind of signal amplifying system and method thereof, the efficiency that signal amplifies can be improved.
In order to achieve the above object, technical scheme of the present invention is achieved in that
Signal amplifying system, comprising:
Complex programmable logic device (CPLD), for sending amplification steering order;
Segmentation amplifying circuit, for receiving the amplification steering order that signal to be amplified and described CPLD sends, and amplifies corresponding multiple according to described amplification steering order by described segmentation signal to be amplified.
Further, described CPLD comprises:
Amplify control counter: for according to time counting, every Preset Time, counting adds 1; Initialization after amplification controls output module output amplification steering order;
Multiple amplification control register: for preserving default amplification control time segment information; Connect successively between described multiple amplification control register;
Amplify and control output module: for the amplification control time segment information preserved in count value current for described amplification control counter and described amplification control register being compared when amplifying the change of control counter count value;
Wherein, described compare be according to described multiple amplification control register between the order of connection, first the amplification control time segment information preserved in count value current for described amplification control counter and first amplification control register is compared, if identical, export and amplify steering order accordingly, otherwise again compare etc. after control counter numerical value change to be amplified, until identical;
Export after amplifying steering order, count value current for described amplification control counter is continued to amplify with the next one amplification control time segment information preserved in control register compare, until the amplification control time segment information preserved in all amplification control registers is all compared.
Further, described segmentation amplifying circuit comprises:
Analog multiplexer: for receiving and resolving described amplification steering order, gating resistance;
Resistance: be connected between described analog multiplexer and programmable amplifier, for the operation according to described analog multiplexer gating resistance, realizes different resistances, determines the enlargement factor of described amplification steering order;
Programmable amplifier: for according to after parsing, and determine that the amplification steering order of enlargement factor is by amplification signal to be amplified.
Preferably, described signal amplifying system also includes:
Signal transmitter, for the synchro control instruction sent according to CPLD, launches signal to be amplified;
Described CPLD comprises further:
Emission control module, for sending described synchro control instruction to described signal transmitter.
Further described emission control module comprises:
Synchro control counter: for according to time counting, described synchro control counter and described amplification control counter synchronous counting, and initialization after synchro control output module exports synchro control instruction;
Synchro control register: for preserving default synchro control time period information;
Synchro control output module: comprise multiple output channel, exports synchro control instruction for the synchro control time period information of preserving according to synchro control counter and described synchro control register;
Wherein, its of including in multiple output channel of described synchro control output module gating exports high level signal, is compared by the amplification control time segment information preserved when synchro control counter changes in count value current for described synchro control counter and described synchro control register; When described synchro control counter count value with preserve in described synchro control register the synchro control time period, information was identical time, output low level signal is as described synchro control instruction; In the process, the equal output low level signal of output channel of non-gating on described synchro control output module; Described multiple output channel is rotated use.
Preferably, described signal amplifying system also comprises:
Host computer, for sending setting data to described CPLD, is arranged described CPLD; By sending enable control signal to CPLD, starting CPLD and carrying out work;
Analog to digital converter: for receiving the amplifying signal that described segmentation amplifying circuit exports, and by this amplifying signal be converted to digital signal, import described host computer into.
Method for amplifying signal, comprises step:
Sent by CPLD and amplify steering order;
Received by segmentation amplifying circuit and resolve described amplification steering order, and according to the amplification steering order after resolving, segmentation signal to be amplified being amplified to corresponding multiple.
Described by CPLD send amplify steering order be specially:
Carry out amplification control time segment information to amplification control register to preset;
Control counter initialization will be amplified;
Make amplification control counter according to time counting, every Preset Time, counting adds 1;
The amplification control time segment information preserved in the current count value of described amplification control counter and described first amplification control register is made to compare;
If difference, again compare etc. after control counter numerical value change to be amplified, until identical;
If identical, export and amplify steering order accordingly, and control counter initialization will be amplified;
Count value current for described amplification control counter is continued to amplify with the next one amplification control time segment information preserved in control register compare, until the amplification control time segment information preserved in all amplification control registers is all compared;
Wherein, described compare be according to described multiple amplification control register between the order of connection.
When signal amplifying system comprises signal transmitter, the method comprises further:
Send synchro control instruction to signal transmitter by described CPLD, be specially:
Carry out synchro control time period information to synchro control register to preset;
By synchro control counter initialization;
Make described synchro control counter and amplify control counter synchronous counting;
One that from synchro control output module gating, it includes multiple output channel exports high level signal, is compared by the amplification control time segment information preserved when synchro control counter changes in count value current for described synchro control counter and described synchro control register;
If difference, again compare, until identical after waiting for the change of synchro control counter values;
If identical by described output channel output low level signal as synchro control instruction;
By synchro control counter initialization and change output channel repeat said process;
Wherein, in the process, the equal output low level signal of output channel of non-gating on described synchro control output module; Described multiple output channel is rotated use.
Before described CPLD sends amplification steering order and synchro control instruction, also comprise:
By host computer, data setting is carried out to described CPLD;
Host computer sends enable steering order to described CPLD, starts CPLD and carries out work;
After described segmentation amplifying circuit is by amplification signal to be amplified, also comprise:
Signal after described amplification is converted to digital signal by analog to digital converter, and imports described host computer into.。
Signal amplifying system proposed by the invention and method thereof, have the following advantages:
1, amplification efficiency is high.Each design parameter of CPLD is all set in advance by host computer, in the process of amplifying, the control that all signals amplify, all come by CPLD, CPLD is logical device, can output signal in a short period of time, compared to prior art, during Single-chip Controlling, the operation of program is shorter for service time, thus improves the efficiency of amplification.
2, real-time is had more.Because enlargement factor steering order and the two groups of control informations of signal firing order are dealt into segmentation amplifying circuit and signal transmitter by CPLD simultaneously, after signal transmitter receives signal firing order, signal to be amplified can be sent to segmentation amplifying circuit, amplify via segmentation amplifying circuit, two groups of control informations ensure that and the time synchronized that signal sends and amplifies have more real-time.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, introduce doing one to the accompanying drawing used required in embodiment or description of the prior art simply below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural drawing of the signal amplifying system that one embodiment of the invention proposes;
Fig. 2 is the concrete structure figure of CPLD and the segmentation amplifying circuit proposed in the embodiment of the present invention;
Fig. 3 is the structural drawing of the emission control module that proposes of another embodiment of the present invention and signal transmitter
Fig. 4 is the structural drawing of the signal amplifying system that another embodiment of the present invention proposes;
Fig. 5 be the embodiment of the present invention the process flow diagram of the method for amplifying signal of is proposed;
Fig. 6 is that the CPLD proposed in the embodiment of the present invention sends the process flow diagram amplifying steering order;
Fig. 7 is the process flow diagram of the CPLD transmission synchro control instruction that another embodiment of the present invention proposes;
Fig. 8 is the process flow diagram of the method for amplifying signal that another embodiment of the present invention proposes.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
See Fig. 1, signal amplifying system provided by the invention, comprising:
Complex programmable logic device (CPLD) 1 and segmentation amplifying circuit 2;
Wherein, CPLD1 is for sending amplification steering order; The amplification steering order that segmentation amplifying circuit 2 sends for receiving signal to be amplified and described CPLD1, and according to described amplification steering order, corresponding multiple is amplified in described segmentation signal to be amplified.
The signal amplifying system that above-described embodiment proposes, amplify steering order to be controlled by CPLD1, both the enlargement factor of segmentation amplifying circuit 2 had been controlled, and this amplification steering order is produced in real time by the information pre-set in CPLD1, and due to CPLD1 be logical device, amplify the time used when steering order in generation few.And in prior art, when using monolithic processor controlled, single-chip microcomputer will complete multiple different control command simultaneously, the process of control command can be divided into multiple thread, in section sometime, only complete a certain thread of some processes, and the thread of multiple process, alternately complete, the steering order completed is more, expends time in more of a specified duration.Therefore, the signal amplifying system that the present invention proposes, the efficiency that signal amplifies is higher.
See Fig. 2, in another embodiment, described CPLD1 comprises: amplify control counter 3, amplify control register 4 and amplify control output module 5;
Wherein, described amplification control counter 3 is for according to time counting, and every Preset Time, counting adds 1, and initialization after amplification controls output module 5 output amplification steering order;
Amplifying control register 4 has multiple, for preserving default amplification control time segment information, and connects successively between multiple amplification control register 4;
Described amplification controls output module 5 for being compared by the amplification control time segment information preserved in count value current for described amplification control counter 3 and described amplification control register 4 when amplifying the change of control counter 3 count value;
Wherein, described compare be according to described multiple amplification control register 4 between the order of connection, first the amplification control time segment information preserved in count value current for described amplification control counter 3 and first amplification control register 4 is compared, if identical, export and amplify steering order accordingly, otherwise again compare etc. after control counter 3 numerical value change to be amplified, until identical;
Export after amplifying steering order, count value current for described amplification control counter 3 is continued to amplify with the next one amplification control time segment information preserved in control register 4 compare, until the amplification control time segment information preserved in all amplification control registers 4 is all compared.
Such as, amplification steering order is two path control signal, is respectively control0 and control1; Described amplification control register 4 has four, is respectively time1, time2, time3 and time4, and connects successively between time1, time2, time3 and time4; Four amplification control registers 4 are preset with four different amplification control time segment informations respectively.Such as, respectively time1, time2, time3 and time4 are set to 04,03,05 and 07, amplify control counter 3 and start according to time counting, every Preset Time, described amplification control counter counting adds 1, when amplifying control counter 4 count value and being identical with time1 numerical value 04, the value of gating control0 and control1 is 00, amplify control output module 5 and send corresponding level signal to amplification control circuit, control counter 3 is amplified in initialization, start again to count, and will the numeric ratio preserved in the count value of control counter 3 and time2 be amplified comparatively, when counter 3 count value is identical with time2 numerical value 03, the value of gating control0 and control1 is 01, amplify control output module 5 and send corresponding level signal to amplification control circuit, until time1, time2, time3 and time4 is all by completeer, send end signal.Segmentation signal to be amplified can be amplified to four different multiples according to above-mentioned four level signals by segmentation amplifying circuit 2.
In like manner, when amplification steering order is three tunnel control signals, when being respectively control0, control1 and control2, corresponding amplification control register 5 has 8, be respectively time1, time2, time3, time4, time5, time6, time7 and time8, respectively time1, time2, time3, time4, time5, time6, time7 and time8 be set to 02,05,04,05,04,05,04 and 06.To control counter 4 count value be amplified and compare with the numerical value preserved in amplification control register 5time1, time2, time3, time4, time5, time6, time7 and time8 successively; Now, segmentation signal to be amplified can be amplified to eight different multiples by amplification control circuit.
It should be noted that, the numerical value in above time1, time2, time3, time4, time5, time6, time7 and time8 is not limited to the numerical value that the embodiment of the present invention provides, and is all pre-set by actual needs.
Segmentation amplifying circuit 2 comprises: analog multiplexer 6, resistance 7 and programmable amplifier 8;
Wherein, described analog multiplexer 6 amplifies steering order for receiving and resolving, and the corresponding resistance 7 of gating;
Resistance 7 is connected between described analog multiplexer 6 and described programmable amplifier 8, for the operation according to described analog multiplexer 6 gating resistance 7, realizes different resistances, determines the enlargement factor of described amplification steering order;
Programmable amplifier 8: for according to after parsing, and determine that the amplification steering order of enlargement factor is by amplification signal to be amplified.
The present embodiment is by multiple resistance 7, and the signal subsection achieving different amplitude amplifies.Programmable amplifier 8 adjustable gain, multiplexer 6 receives the amplification steering order that CPLD1 sends, and pass through after the parsing of this instruction, the corresponding resistance 7 of gating, and pass through the resistance 7 of this gating, amplification steering order after resolving is input in described programmable amplifier 8, realizes the amplification of different multiples signal.The number of described resistance 7 is identical with the number of described amplification control register 4.Such as, when described amplification control register 4 is four, resistance 7 is respectively R1, R2, R3 and R4, when the numerical value of the amplification steering order of input multiplexer is respectively 00,01,10 and 11, R1, R2, R3 and R4 of corresponding of gating respectively, signal is amplified to corresponding multiple by programmable amplifier 8.Such as the enlargement factor of segmentation amplifying circuit can be set to respectively 1 times, 10 times 100 times and 1000 times respectively, this multiple is relevant with the resistance of external resistance 7, can according to actual needs, the resistance of change resistance 7, thus the enlargement factor regulating segmentation amplifying circuit 2 different.
See Fig. 3, in another embodiment in the present invention, described signal amplifying system also includes signal transmitter 9;
Described signal transmitter 9, for the synchro control instruction sent according to CPLD1, is launched signal to be amplified;
Now described CPLD1 comprises emission control module 10 further: for launching described synchro control instruction to described signal transmitter 9.
Emission control module 10 comprises: synchro control counter 11, synchro control register 12 and synchronous output module 13;
Wherein, synchro control counter 11 for according to time counting, described synchro control counter 11 and described amplification control counter 3 synchronous counting, and initialization after synchro control output module 13 exports synchro control instruction;
Synchro control register 12 is for preserving default synchro control time period information;
Described synchro control output module 13 comprises multiple output channel, exports synchro control instruction for the synchro control time period information of preserving according to synchro control counter 11 count value and described synchro control register 12;
Wherein, its of including in multiple output channel of described synchro control output module 13 gating exports high level signal, is compared by the amplification control time segment information preserved when synchro control counter 11 count value changes in count value current for described synchro control counter 11 and described synchro control register 12; When described synchro control counter 11 count value with preserve in described synchro control register 12 the synchro control time period, information was identical time, output low level signal is as described synchro control instruction; In the process, the equal output low level signal of the output channel of non-gating on described synchro control output module 13, the use and multiple output channel is rotated.
Such as, synchro control instruction is two-way PWM(width modulation) signal, be respectively pwm0 and pwm1, correspond, described output channel has two, synchro control register 12 is preset with synchro control time period information, synchro control counter 11 starts and amplifies control counter 3 synchronous counting, gating pwm0 exports high level signal, when synchro control counter 11 count value with preserve in synchro control register 12 the synchro control time period, information was identical time, pwm0 output low level signal is as synchronizing signal; Initial synchronization control counter 11; In the process, pwm1 output low level signal that is 0.Gating pwm1 exports high level signal and repeats said process.Two-way pwm signal is rotated use.
Identical, the PWM(width modulation when synchro control instruction) signal, when being respectively pwm0, pwm1 and pwm2, three road pwm signals are rotated use.
Preferably, described analog multiplexer 12 can adopt model to be the analog multiplexer of ADG409, and programmable amplifier 13 can adopt model to be the programmable amplifier of AD625.
See Fig. 4, in another one embodiment of the present invention, signal amplifying system also includes:
Host computer 14, for sending setting data to described CPLD1, is arranged described CPLD1; By sending enable control signal to CPLD1, starting CPLD1 and carrying out work;
Analog to digital converter 15: for receiving the amplifying signal that segmentation amplifying circuit 2 exports, and by this amplifying signal be converted to digital signal, import described host computer 14 into.
See Fig. 5, the embodiment of the present invention also provides a kind of method for amplifying signal, comprising:
Step 101: sent by CPLD and amplify steering order;
Step 102: received by segmentation amplifying circuit and resolve described amplification steering order, and according to the amplification steering order after resolving, segmentation signal to be amplified is amplified to corresponding multiple.
See Fig. 6, in the above-described embodiments, send amplification steering order by CPLD to be specially:
Step 201: amplification control time segment information is carried out to amplification control register and presets;
Step 202: control counter initialization will be amplified;
Step 203: make amplification control counter according to time counting, every Preset Time, counting adds 1;
Step 204: make the amplification control time segment information preserved in the current count value of described amplification control counter and first amplification control register compare;
Step 205: if difference, again compare etc. after control counter numerical value change to be amplified, until identical;
Step 206: if identical, export and amplify steering order accordingly, and control counter initialization will be amplified;
Step 207: count value current for described amplification control counter is continued to amplify with the next one amplification control time segment information preserved in control register and compares, until the amplification control time segment information preserved in all amplification control registers is all compared.
In above-mentioned steps, described compare be according to described multiple amplification control register between the order of connection, the amplification control time segment information preserved to all amplification control register is all compared.
See Fig. 7, in another embodiment, when signal amplifying system comprises signal transmitter, method for amplifying signal comprises further: send synchro control instruction to signal transmitter by CPLD.
Send synchro control instruction by CPLD to be specially to signal transmitter:
Step 301: synchro control time period information is carried out to synchro control register and presets;
Step 302: by synchro control counter initialization;
Step 303: make described synchro control counter and amplify control counter synchronous counting;
Step 304: one that it includes multiple output channel from synchro control output module gating exports high level signal, compared by the amplification control time segment information preserved when synchro control counter changes in count value current for described synchro control counter and described synchro control register;
Step 305: if difference, compares, again until identical after waiting for the change of synchro control counter values;
Step 306: if identical by described output channel output low level signal as synchro control instruction;
Step 307: by synchro control counter initialization and change output channel repeat said process;
In above process, the equal output low level signal of output channel of non-gating on described synchro control output module; Described multiple output channel is rotated use; Institute's synchro control counter and amplification control counter synchronous counting.
See Fig. 8, in another one embodiment of the present invention, when signal amplifying system also includes host computer and analog to digital converter, method for amplifying signal is:
Step 401: data setting is carried out to described CPLD by host computer;
Step 402: send enable steering order to described CPLD by host computer, starts CPLD and carries out work;
Step 403: sent by CPLD and amplify steering order and synchro control instruction;
Step 404: receive described synchro control instruction by signal transmitter, and send signal to be amplified to segmentation amplifying circuit;
Step 405: received by segmentation amplifying circuit and resolve described amplification steering order, and be amplified to corresponding multiple according to the amplification steering order after resolving by signal to be amplified;
Step 406: amplifying signal is converted to digital signal by analog to digital converter, and imports described host computer into.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (5)
1. signal amplifying system, is characterized in that, comprising:
Complex programmable logic device (CPLD), for sending amplification steering order;
Segmentation amplifying circuit, for receiving the amplification steering order that signal to be amplified and described CPLD sends, and amplifies corresponding multiple according to described amplification steering order by described segmentation signal to be amplified;
Described segmentation amplifying circuit comprises:
Analog multiplexer: for receiving and resolving described amplification steering order, gating resistance;
Resistance: be connected between described analog multiplexer and programmable amplifier, for the operation according to described analog multiplexer gating resistance, realizes different resistances, determines the enlargement factor of described amplification steering order;
Programmable amplifier: for according to after parsing, and determine that the amplification steering order of enlargement factor is by amplification signal to be amplified.
2. signal amplifying system according to claim 1, is characterized in that, described CPLD comprises:
Amplify control counter: for according to time counting, every Preset Time, counting adds 1; Initialization after amplification controls output module output amplification steering order;
Multiple amplification control register: for preserving default amplification control time segment information; Connect successively between described multiple amplification control register;
Amplify and control output module: for the amplification control time segment information preserved in count value current for described amplification control counter and described amplification control register being compared when amplifying the change of control counter count value;
Wherein, described compare be according to described multiple amplification control register between the order of connection, first the amplification control time segment information preserved in count value current for described amplification control counter and first amplification control register is compared, if identical, export and amplify steering order accordingly, otherwise again compare etc. after control counter numerical value change to be amplified, until identical;
Export after amplifying steering order, count value current for described amplification control counter is continued to amplify with the next one amplification control time segment information preserved in control register compare, until the amplification control time segment information preserved in all amplification control registers is all compared.
3. signal amplifying system according to claim 2, is characterized in that, also includes:
Signal transmitter, for the synchro control instruction sent according to CPLD, launches signal to be amplified;
Described CPLD comprises further:
Emission control module, for sending described synchro control instruction to described signal transmitter.
4. signal amplifying system according to claim 3, is characterized in that, described emission control module comprises:
Synchro control counter: for according to time counting, described synchro control counter and described amplification control counter synchronous counting, and initialization after synchro control output module exports synchro control instruction;
Synchro control register: for preserving default synchro control time period information;
Synchro control output module: comprise multiple output channel, exports synchro control instruction for the synchro control time period information of preserving according to synchro control counter and described synchro control register;
Wherein, its of including in multiple output channel of described synchro control output module gating exports high level signal, is compared by the amplification control time segment information preserved when synchro control counter changes in count value current for described synchro control counter and described synchro control register; When described synchro control counter count value with preserve in described synchro control register the synchro control time period, information was identical time, output low level signal is as described synchro control instruction; In the process, the equal output low level signal of output channel of non-gating on described synchro control output module; Described multiple output channel is rotated use.
5. signal amplifying system according to claim 1 and 2, is characterized in that, also comprises:
Host computer, for sending setting data to described CPLD, is arranged described CPLD; By sending enable control signal to CPLD, starting CPLD and carrying out work;
Analog to digital converter: for receiving the amplifying signal that described segmentation amplifying circuit exports, and by this amplifying signal be converted to digital signal, import described host computer into.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210183028.4A CN102684625B (en) | 2012-06-05 | 2012-06-05 | Signal amplifying system and signal amplifying method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210183028.4A CN102684625B (en) | 2012-06-05 | 2012-06-05 | Signal amplifying system and signal amplifying method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102684625A CN102684625A (en) | 2012-09-19 |
| CN102684625B true CN102684625B (en) | 2015-02-04 |
Family
ID=46816097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210183028.4A Expired - Fee Related CN102684625B (en) | 2012-06-05 | 2012-06-05 | Signal amplifying system and signal amplifying method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102684625B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86102014B (en) * | 1986-03-28 | 1988-08-31 | 中国人民解放军空军后勤部工程设计局 | Multifunctional automatic microdeformation monitor |
| CN1296705C (en) * | 2003-06-11 | 2007-01-24 | 宇东科技股份有限公司 | Control circuit for adjustable biological sensor and measuring method thereof |
| CN100535654C (en) * | 2006-07-12 | 2009-09-02 | 广东汕头超声电子股份有限公司 | Gain compensating method for flaw detector |
-
2012
- 2012-06-05 CN CN201210183028.4A patent/CN102684625B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN102684625A (en) | 2012-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100561539C (en) | A kind of automatization test system and method for simulating Infrared remote controller | |
| CN105426299A (en) | Workflow technology-based testing data real-time interpretation system | |
| CN102175965B (en) | Automatic testing method for magnetic card decoding circuit | |
| CN103453983A (en) | Industrial data acquisition method and system based on time diversion multiplexing and multiple channels | |
| CN112270152B (en) | Chip IO pin verification system and method | |
| CN108227539B (en) | Configurable multi-channel high-speed analog quantity acquisition system and method | |
| CN107014432B (en) | A kind of analog signal monitoring system and method | |
| CN102684625B (en) | Signal amplifying system and signal amplifying method | |
| CN105117566A (en) | Method and device of analyzing PCIe eye patterns | |
| CN115765743B (en) | Multichannel ADC synchronous acquisition device and method based on ZYNQ | |
| CN204165946U (en) | Multichannel ultrasonic signal synchronous | |
| CN106531217B (en) | FLASH device programming method and system for programmable logic device | |
| CN103595445A (en) | Gain control method and gain control device for demodulation signals and microcontroller | |
| US11558065B2 (en) | Reconfigurable analog to digital converter (ADC) | |
| CN109510624B (en) | High-voltage digital-to-analog conversion and inspection device for airborne equipment | |
| CN107809222A (en) | A kind of pulse signal generator | |
| CN109855746B (en) | Temperature value transmission device and method thereof | |
| CN105099396A (en) | Filter switching method, filter switching device and medical device | |
| CN112350893A (en) | Ethernet port consistency test method and system | |
| CN105353645A (en) | Solenoid valve testing device and method | |
| CN204991102U (en) | Eliminate circuit structure of high density LED display screen scanning ghost | |
| CN201368860Y (en) | Flaw detection system | |
| CN108536061A (en) | A kind of driving method for kinetic control system | |
| CN105320623A (en) | Multi-channel data processor and method thereof | |
| CN209167863U (en) | A kind of multi-channel wide dynamic range high-speed signal acquisition processing unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150204 Termination date: 20160605 |