CN102684625B - Signal amplifying system and signal amplifying method - Google Patents

Abstract

The invention relates to the technical field of signal amplification, and provides a signal amplification system and an amplification method thereof. The signal amplification system includes: a complex programmable logic device CPLD, which is used to send amplification control instructions; a segmented amplification circuit, which is used to receive the signal to be amplified and the amplification control instructions sent by the CPLD, and convert the amplification control instructions according to the amplification control instructions. Describe the corresponding multiplier for segmental amplification of the signal to be amplified. In the signal amplification method, the amplification control instruction is sent through the CPLD; the amplification control instruction is received and analyzed through the segmented amplification circuit, and the signal to be amplified is amplified to a corresponding multiple according to the analyzed amplification control instruction. The present invention uses CPLD to control the entire segmented amplifying circuit. Because CPLD is a logic device, its control data is pre-set, and its operating speed is faster than that controlled by a single-chip microcomputer, thereby improving the efficiency of signal amplification.

Description

Signal amplifying system and its amplifying method

technical field

The invention relates to the technical field of signal amplification, in particular to a signal amplification system and an amplification method thereof.

Background technique

At present, signal amplification generally adopts a single-chip microcomputer program-controlled amplifier. In this amplifier, the steps of signal amplification are controlled by a program installed in a microcontroller.

However, since all control processes must be run on the single-chip microcomputer, it takes a lot of time. Therefore, each amplification cycle will take a lot of time, resulting in the disadvantage of low signal amplification efficiency.

Contents of the invention

The invention provides a signal amplification system and a method thereof, which can improve the efficiency of signal amplification.

In order to achieve the above object, the technical solution of the present invention is achieved in that:

Signal amplification system, including:

Complex programmable logic device CPLD, used to send amplification control instructions;

The segmental amplification circuit is used to receive the signal to be amplified and the amplification control instruction sent by the CPLD, and amplify the signal to be amplified by a corresponding multiple according to the amplification control instruction.

Further, the CPLD includes:

Amplification control counter: used for counting according to time, every preset time, the count is increased by 1; it is initialized after the amplification control output module outputs the amplification control command;

A plurality of amplification control registers: used to save preset amplification control time period information; the plurality of amplification control registers are sequentially connected;

Amplification control output module: used to compare the current count value of the amplification control counter with the amplification control time period information stored in the amplification control register when the count value of the amplification control counter changes;

Wherein, the comparison is to compare the current count value of the amplification control counter with the amplification control time period information stored in the first amplification control register according to the connection sequence between the plurality of amplification control registers, if If they are the same, output the corresponding amplification control command, otherwise wait for the value of the amplification control counter to change and then compare again until they are the same;

After the amplification control command is output, the current count value of the amplification control counter is continuously compared with the amplification control time period information stored in the next amplification control register until all the amplification control time period information stored in all amplification control registers are compared .

Further, the segmented amplification circuit includes:

An analog multiplexer: used to receive and analyze the amplification control command and gate resistor;

Resistor: connected between the analog multiplexer and the program-controlled amplifier, used to realize different resistance values according to the operation of the gate resistor of the analog multiplexer, and determine the amplification factor of the amplification control command ;

Program-controlled amplifier: used to amplify the signal to be amplified according to the amplified control command after analysis and to determine the magnification factor.

Preferably, the signal amplification system also includes:

The signal transmitter is used to transmit the signal to be amplified according to the synchronous control command sent by the CPLD;

Described CPLD further comprises:

A transmission control module, configured to send the synchronization control instruction to the signal transmitter.

Further described emission control modules include:

Synchronous control counter: used for counting according to time, the synchronous control counter counts synchronously with the amplification control counter, and is initialized after the synchronous control output module outputs the synchronous control command;

Synchronous control register: used to save the preset synchronous control time period information;

Synchronous control output module: including a plurality of output channels, used to output synchronous control instructions according to the synchronous control counter count value and the synchronous control time period information saved by the synchronous control register;

Wherein, the synchronous control output module selects one of the multiple output channels to output a high-level signal, and compares the current count value of the synchronous control counter with the synchronous control register when the synchronous control counter count value changes. The amplification control period information saved in is compared; when the count value of the synchronous control counter is the same as the synchronous control period information preserved in the synchronous control register, output a low level signal as the synchronous control instruction; During this process, the unselected output channels on the synchronous control output module all output low-level signals; the multiple output channels are used in turn.

Preferably, the signal amplification system also includes:

The host computer is used to send setting data to the CPLD to set the CPLD; to start the CPLD to work by sending an enabling control signal to the CPLD;

Analog-to-digital converter: used to receive the amplified signal output by the segmented amplification circuit, convert the amplified signal into a digital signal, and transmit it to the upper computer.

Signal amplification method, comprising steps:

Send amplification control instructions through CPLD;

The amplifying control instruction is received and analyzed by a segmented amplification circuit, and the signal to be amplified is amplified in segments to corresponding multiples according to the amplified control instruction after analysis.

The described sending amplification control instruction by CPLD is specifically:

Preset the amplification control time period information of the amplification control register;

Initialize the amplification control counter;

Make the amplification control counter count according to the time, and add 1 to the count every preset time;

comparing the current count value of the amplification control counter with the amplification control time period information stored in the first amplification control register;

If they are different, wait for the value of the amplification control counter to change and compare again until they are the same;

If they are the same, the corresponding amplification control command is output, and the amplification control counter is initialized;

Continuing to compare the current count value of the amplification control counter with the amplification control time period information stored in the next amplification control register until all the amplification control time period information stored in all the amplification control registers are compared;

Wherein, the comparison is according to the connection sequence among the multiple amplification control registers.

When the signal amplification system includes a signal transmitter, the method further includes:

Send synchronous control instructions to the signal transmitter through the CPLD, specifically:

Preset the synchronous control period information of the synchronous control register;

Initialize the synchronous control counter;

making the synchronous control counter count synchronously with the amplification control counter;

From the synchronous control output module, it includes a high-level output signal in a plurality of output channels, and when the synchronous control counter count value changes, the current count value of the synchronous control counter is compared with the value saved in the synchronous control register. Zoom in on the control time period information for comparison;

If they are different, wait for the value of the synchronous control counter to change and compare again until they are the same;

If the same, output a low-level signal through the output channel as a synchronous control instruction;

Initialize the synchronous control counter and replace the output channel to repeat the above process;

Wherein, during this process, the ungated output channels on the synchronous control output module all output low-level signals; the multiple output channels are used in turn.

Before the CPLD sends the amplification control command and the synchronous control command, it also includes:

Carry out data setting to described CPLD by upper computer;

The host computer sends an enable control command to the CPLD, and starts the CPLD to work;

After the segmental amplification circuit amplifies the signal to be amplified, it also includes:

The analog-to-digital converter converts the amplified signal into a digital signal and transmits it to the upper computer. .

The signal amplification system and method thereof proposed by the present invention have the following advantages:

1. High amplification efficiency. The specific parameters of the CPLD are set in advance through the host computer. During the amplification process, all signal amplification control is completed through the CPLD. The CPLD is a logic device that can output signals in a short time. Compared with In the prior art, when the single-chip microcomputer is controlled, the running time of the program is shorter, thereby improving the amplification efficiency.

2. It is more real-time. Since the CPLD sends the two sets of control information of the magnification control command and the signal transmission command to the segmental amplification circuit and the signal transmitter at the same time, when the signal transmitter receives the signal transmission command, it will send the signal to be amplified to the segmental amplification The circuit is amplified through a segmented amplification circuit, and two sets of control information ensure the time synchronization of signal transmission and amplification, which is more real-time.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the structural diagram of the signal amplification system that an embodiment of the present invention proposes;

Fig. 2 is the specific structural diagram of CPLD proposed in the embodiment of the present invention and segmental amplification circuit;

Fig. 3 is the structural diagram of the emission control module and signal transmitter proposed by another embodiment of the present invention

Fig. 4 is a structural diagram of a signal amplification system proposed by another embodiment of the present invention;

FIG. 5 is a flowchart of a signal amplification method proposed by an embodiment of the present invention;

Fig. 6 is the flow chart that CPLD proposed in the embodiment of the present invention sends the amplification control order;

Fig. 7 is the flowchart that the CPLD that another embodiment of the present invention proposes sends synchronous control instruction;

Fig. 8 is a flowchart of a signal amplification method proposed by another embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Referring to Fig. 1, the signal amplification system provided by the present invention includes:

Complex programmable logic device CPLD1 and segmented amplifier circuit 2;

Wherein, CPLD1 is used for sending amplification control instruction; segmental amplification circuit 2 is used for receiving the signal to be amplified and the amplification control instruction sent by the CPLD1, and amplifies the signal to be amplified in sections according to the amplification control instruction. multiple.

In the signal amplification system proposed in the foregoing embodiments, the amplification control command is controlled by CPLD1, which has both controlled the amplification factor of the segmented amplification circuit 2, and the amplification control command is generated in real time by information preset in CPLD1, and because CPLD1 is The logic device takes less time to generate the amplification control command. In the prior art, when using a single-chip microcomputer to control, the single-chip microcomputer will complete a plurality of different control commands at the same time, and the process of the control command will be divided into multiple threads. In a certain period of time, only a certain thread of a certain process will be completed. , and the threads of multiple processes are completed alternately, the more control instructions are completed, the longer it takes. Therefore, the signal amplification system proposed by the present invention has higher signal amplification efficiency.

Referring to Fig. 2, in another embodiment, described CPLD1 comprises: amplification control counter 3, amplification control register 4 and amplification control output module 5;

Wherein, the amplification control counter 3 is used for counting according to time, every preset time, the count is increased by 1, and initialized after the amplification control output module 5 outputs the amplification control command;

There are multiple amplification control registers 4, which are used to store preset amplification control time period information, and multiple amplification control registers 4 are sequentially connected;

The amplification control output module 5 is used to compare the current count value of the amplification control counter 3 with the amplification control time period information stored in the amplification control register 4 when the count value of the amplification control counter 3 changes;

Wherein, the comparison is performed according to the connection sequence between the plurality of amplification control registers 4, and the current count value of the amplification control counter 3 is first compared with the amplification control time period information stored in the first amplification control register 4 Compare, if they are the same, output the corresponding amplification control command, otherwise wait for the value of the amplification control counter 3 to change and then compare again until they are the same;

After outputting the amplification control instruction, the current count value of the amplification control counter 3 is continuously compared with the amplification control time period information preserved in the next amplification control register 4 until the amplification control time period information preserved in all the amplification control registers 4 are compared.

For example, the amplification control command is two control signals, respectively control0 and control1; the amplification control register 4 has four, respectively time1, time2, time3 and time4, and time1, time2, time3 and time4 are connected in sequence; The four amplification control registers 4 are respectively preset with four different amplification control time period information. For example, time1, time2, time3 and time4 are set to 04, 03, 05 and 07 respectively, and the amplification control counter 3 starts counting according to the time, and at every preset time, the counting of the amplification control counter adds 1; when the amplification control counter 4 When the count value is the same as the time1 value 04, the value of strobe control0 and control1 is 00, the amplification control output module 5 sends the corresponding level signal to the amplification control circuit, initializes the amplification control counter 3, starts counting again, and sets the amplification control counter The count value of 3 is compared with the value saved in time2. When the count value of counter 3 is the same as the value 03 of time2, the value of gate control0 and control1 is 01, and the amplification control output module 5 sends a corresponding level signal to the amplification control circuit. Until time1, time2, time3 and time4 are all compared; send the end signal. The segmental amplification circuit 2 can segmentally amplify the signal to be amplified to four different multiples according to the above four level signals.

Similarly, when the amplification control command is three control signals, respectively control0, control1 and control2, there are 8 corresponding amplification control registers 5, which are time1, time2, time3, time4, time5, time6, time7 and time8, Set time1, time2, time3, time4, time5, time6, time7, and time8 to 02, 05, 04, 05, 04, 05, 04, and 06, respectively. The magnification control counter 4 count value is compared with the numerical value preserved in the amplification control register 5time1, time2, time3, time4, time5, time6, time7 and time8 in turn; at this moment, the amplification control circuit can amplify the signal segment to be amplified to Eight different multiples.

It should be noted that the above values of time1, time2, time3, time4, time5, time6, time7 and time8 are not limited to the values provided in the embodiment of the present invention, and are all preset according to actual needs.

The segmented amplification circuit 2 includes: an analog multiplexer 6, a resistor 7 and a program-controlled amplifier 8;

Wherein, the analog multiplexer 6 is used to receive and analyze the amplification control instruction, and gate the corresponding resistor 7;

Resistor 7 is connected between described analog multiplexer 6 and described programmable amplifier 8, is used for according to the operation of described analog multiplexer 6 gating resistance 7, realizes different resistance value, determines described Amplify the magnification of the control command;

Programmable amplifier 8: used for amplifying the signal to be amplified according to the amplified control instruction after analysis and determining the magnification factor.

In this embodiment, multiple resistors 7 are used to realize segmental amplification of signals with different amplitudes. The gain of the program-controlled amplifier 8 is adjustable, and the multiplexer 6 receives the amplification control instruction sent by the CPLD1, and after analyzing the instruction, selects the corresponding resistor 7, and through the selected resistor 7, the analyzed The amplification control command is input into the program-controlled amplifier 8 to realize the amplification of signals with different multiples. The number of the resistors 7 is the same as the number of the amplification control registers 4 . For example, when there are four amplification control registers 4, the resistors 7 are R1, R2, R3 and R4 respectively, and when the values of the amplification control instructions input to the multiplexer are 00, 01, 10 and 11 respectively, The corresponding R1, R2, R3 and R4 are selected respectively, and the program-controlled amplifier 8 amplifies the signal to the corresponding multiple. For example, the magnification of the segmented amplification circuit can be set to 1 times, 10 times, 100 times and 1000 times respectively. This multiple is related to the resistance value of the external resistor 7. The resistance value of the resistor 7 can be changed according to actual needs, so that Different amplification factors of the sub-amplification circuit 2 are adjusted.

Referring to Fig. 3, in another embodiment of the present invention, the signal amplification system also includes a signal transmitter 9;

The signal transmitter 9 is used to transmit a signal to be amplified according to the synchronous control instruction sent by the CPLD1;

At this time, the CPLD1 further includes a transmission control module 10 : configured to transmit the synchronization control instruction to the signal transmitter 9 .

The emission control module 10 includes: a synchronous control counter 11, a synchronous control register 12 and a synchronous output module 13;

Wherein, the synchronous control counter 11 is used for counting according to time, and the synchronous control counter 11 counts synchronously with the amplification control counter 3, and is initialized after the synchronous control output module 13 outputs a synchronous control command;

The synchronous control register 12 is used to save the preset synchronous control time period information;

The synchronous control output module 13 includes a plurality of output channels, which are used to output synchronous control instructions according to the synchronous control counter 11 count value and the synchronous control period information saved by the synchronous control register 12;

Wherein, the synchronous control output module 13 selects one of the multiple output channels to output a high-level signal, and compares the current count value of the synchronous control counter 11 with the synchronous control counter 11 when the count value changes. The amplification control period information preserved in the synchronous control register 12 compares; When the count value of the synchronous control counter 11 is identical with the synchronous control period information preserved in the synchronous control register 12, output a low level signal as the The synchronous control instruction; during this process, the output channels that are not selected on the synchronous control output module 13 all output low-level signals, and multiple output channels are used in turn.

For example, the synchronous control instruction is two PWM (pulse width modulation) signals, respectively pwm0 and pwm1, and correspondingly, there are two output channels, and the synchronous control register 12 is preset with synchronous control time period information, synchronous The control counter 11 starts counting synchronously with the amplification control counter 3, and the strobe pwm0 outputs a high level signal. When the count value of the synchronous control counter 11 is the same as the synchronous control period information stored in the synchronous control register 12, the pwm0 outputs a low power The flat signal is used as a synchronous signal; the synchronous control counter 11 is initialized; during this process, pwm1 outputs a low level signal, that is, 0. Strobe pwm1 output high level signal to repeat the above process. The two PWM signals are used alternately.

Similarly, when the PWM (pulse width modulation) signals of the synchronous control command are respectively pwm0, pwm1 and pwm2, the three PWM signals are used alternately.

Preferably, the analog multiplexer 12 can be an analog multiplexer of model ADG409, and the program-controlled amplifier 13 can be a program-controlled amplifier of model AD625.

Referring to Fig. 4, in another embodiment of the present invention, the signal amplification system also includes:

The upper computer 14 is used to send setting data to the CPLD1 to set the CPLD1; to start the CPLD1 to work by sending an enabling control signal to the CPLD1;

Analog-to-digital converter 15 : used to receive the amplified signal output by the sub-amplification circuit 2 , convert the amplified signal into a digital signal, and transmit it to the host computer 14 .

Referring to FIG. 5, an embodiment of the present invention also provides a signal amplification method, including:

Step 101: sending an amplification control command through the CPLD;

Step 102: Receive and analyze the amplification control instruction through a segmented amplification circuit, and amplify the signal to be amplified in segments to a corresponding multiple according to the analyzed amplification control instruction.

Referring to Fig. 6, in the foregoing embodiment, the amplification control instruction sent by the CPLD is specifically:

Step 201: Presetting the amplification control period information of the amplification control register;

Step 202: Initialize the amplification control counter;

Step 203: Make the amplification control counter count according to the time, and add 1 to the count every preset time;

Step 204: comparing the current count value of the amplification control counter with the amplification control time period information stored in the first amplification control register;

Step 205: If they are different, wait for the value of the amplification control counter to change and compare again until they are the same;

Step 206: if they are the same, output the corresponding amplification control command, and initialize the amplification control counter;

Step 207: Continue to compare the current count value of the amplification control counter with the amplification control time period information stored in the next amplification control register until all the amplification control time period information stored in the amplification control registers are compared.

In the above steps, the comparison is performed according to the connection sequence among the multiple amplification control registers, until the amplification control time period information stored in all the amplification control registers are compared.

Referring to FIG. 7 , in another embodiment of the present invention, when the signal amplification system includes a signal transmitter, the signal amplification method further includes: sending a synchronization control command to the signal transmitter through the CPLD.

Send synchronous control instructions to the signal transmitter through CPLD, specifically:

Step 301: Presetting the synchronous control period information of the synchronous control register;

Step 302: Initialize the synchronous control counter;

Step 303: making the synchronous control counter count synchronously with the amplification control counter;

Step 304: select one of the multiple output channels from the synchronous control output module to output a high-level signal, and compare the current count value of the synchronous control counter with the synchronous control register when the synchronous control counter count value changes Compare the zoom-in control time period information saved in the

Step 305: If they are different, wait for the value of the synchronous control counter to change and then compare again until they are the same;

Step 306: If they are the same, output a low-level signal through the output channel as a synchronous control instruction;

Step 307: Initialize the synchronous control counter and replace the output channel to repeat the above process;

In the above process, the ungated output channels on the synchronous control output module all output low-level signals; the multiple output channels are used in turn; the synchronous control counter and the amplification control counter count synchronously.

Referring to Fig. 8, in another embodiment of the present invention, when the signal amplification system also includes a host computer and an analog-to-digital converter, the signal amplification method is:

Step 401: Perform data setting on the CPLD through the host computer;

Step 402: sending an enable control command to the CPLD through the host computer, and starting the CPLD to work;

Step 403: sending an amplification control command and a synchronization control command through the CPLD;

Step 404: Receive the synchronous control command through the signal transmitter, and send the signal to be amplified to the segmented amplifying circuit;

Step 405: receiving and analyzing the amplification control instruction through the segmented amplification circuit, and amplifying the signal to be amplified to a corresponding multiple according to the analyzed amplification control instruction;

Step 406: The analog-to-digital converter converts the amplified signal into a digital signal, and transmits it to the host computer.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (5)

1. The signal amplification system is characterized in that, comprising: Complex programmable logic device CPLD, used to send amplification control instructions; A segmented amplification circuit, configured to receive the signal to be amplified and the amplification control instruction sent by the CPLD, and amplify the signal to be amplified by a corresponding multiple according to the amplification control instruction; The segmented amplification circuit includes: An analog multiplexer: used to receive and analyze the amplification control command and gate resistor; Resistor: connected between the analog multiplexer and the program-controlled amplifier, used to realize different resistance values according to the operation of the gate resistor of the analog multiplexer, and determine the amplification factor of the amplification control command ; Program-controlled amplifier: used to amplify the signal to be amplified according to the amplified control command after analysis and to determine the magnification factor. 2. signal amplification system according to claim 1, is characterized in that, described CPLD comprises: Amplification control counter: used for counting according to time, every preset time, the count is increased by 1; it is initialized after the amplification control output module outputs the amplification control command; A plurality of amplification control registers: used to save preset amplification control time period information; the plurality of amplification control registers are sequentially connected; Amplification control output module: used to compare the current count value of the amplification control counter with the amplification control time period information stored in the amplification control register when the count value of the amplification control counter changes; Wherein, the comparison is to compare the current count value of the amplification control counter with the amplification control time period information stored in the first amplification control register according to the connection sequence between the plurality of amplification control registers, if If they are the same, output the corresponding amplification control command, otherwise wait for the value of the amplification control counter to change and then compare again until they are the same; After the amplification control command is output, the current count value of the amplification control counter is continuously compared with the amplification control time period information stored in the next amplification control register until all the amplification control time period information stored in all amplification control registers are compared . 3. The signal amplification system according to claim 2, further comprising: The signal transmitter is used to transmit the signal to be amplified according to the synchronous control command sent by the CPLD; Described CPLD further comprises: A transmission control module, configured to send the synchronization control instruction to the signal transmitter. 4. The signal amplification system according to claim 3, wherein the emission control module comprises: Synchronous control counter: used for counting according to time, the synchronous control counter counts synchronously with the amplification control counter, and is initialized after the synchronous control output module outputs the synchronous control instruction; Synchronous control register: used to save the preset synchronous control time period information; Synchronous control output module: including a plurality of output channels, used to output synchronous control instructions according to the synchronous control counter count value and the synchronous control time period information saved by the synchronous control register; Wherein, the synchronous control output module selects one of the multiple output channels to output a high-level signal, and compares the current count value of the synchronous control counter with the synchronous control register when the synchronous control counter count value changes. The amplification control period information saved in is compared; when the count value of the synchronous control counter is the same as the synchronous control period information preserved in the synchronous control register, output a low level signal as the synchronous control instruction; During this process, the ungated output channels on the synchronous control output module all output low-level signals; the multiple output channels are used in turn. 5. The signal amplification system according to claim 1 or 2, further comprising: The host computer is used to send setting data to the CPLD to set the CPLD; to start the CPLD to work by sending an enabling control signal to the CPLD; Analog-to-digital converter: used to receive the amplified signal output by the segmented amplification circuit, convert the amplified signal into a digital signal, and transmit it to the upper computer.