CN102665202A

CN102665202A - Secure coprocessor circuit structure applied to ZigBee protocol and control method thereof

Info

Publication number: CN102665202A
Application number: CN2012101099284A
Authority: CN
Inventors: 吴宁; 张肖强; 黎建华; 周芳; 吕青松; 王旭
Original assignee: Nanjing University of Aeronautics and Astronautics
Current assignee: Nanjing University of Aeronautics and Astronautics
Priority date: 2012-04-16
Filing date: 2012-04-16
Publication date: 2012-09-12
Anticipated expiration: 2032-04-16
Also published as: CN102665202B

Abstract

The invention discloses a secure coprocessor circuit structure applied to a ZigBee protocol and a control method thereof. According to the secure coprocessor circuit structure, on the basis of a single AES (Advanced Encryption Standard) encipher, the parallel processing function generated by an encryption/authentication code adopting a CCM (Counter with Cipher block-changing Message authentication code)* mode in the ZigBee protocol and the parallel processing function acknowledged by the encryption/authentication code adopting the CCM * mode can be achieved and the CTR (Counter Mode) encryption/decryption function adopting the CCM * mode and the CBC-MAC (Cipher Block Chaining-Message Authentication Code) generating/acknowledge functions adopting the CCM * mode can be independently achieved. In addition, the circuit also achieves the function of the MMO (Matyas-Meyer-Oseas) Hash function. According to the secure coprocessor circuit structure and the control method thereof disclosed by the invention, the AES-CCM*security mode and the MMOHASH function are achieved by completely using a hardware circuit, so that the load of CPU (Central Processing Unit) in a ZigBee system is reduced and unnecessary software attack is also avoided.

Description

Be applied to the security coprocessor circuit structure and the control method thereof of ZigBee agreement

Technical field

The invention belongs to the encryption and decryption technology field, particularly relate to a kind of security coprocessor circuit structure and control method thereof of the ZigBee of being applied to agreement.

Background technology

1.ZigBee protocol security is machine-processed

The ZigBee technology is a kind of standard wireless network agreement for the design of low rate Control Network; Have characteristics such as low complex degree, low-power consumption, low rate, low cost; It is operated on the ISM band of 2.4GHz, and transmission rate is 20kb/s ~ 250kb/s, and transmission range is 10m ~ 75m.The ZigBee protocol stack comprises physical layer, MAC layer, network layer, application layer, and defined security service provide mechanism.

The ZigBee standard is to be based upon on the IEEE 802.15.4 standard base, and what its physical layer, MAC layer adopted is IEEE 802.15.4 standard, so the ZigBee Security Architecture is to be based upon on the security service basis of IEEE 802.15.4.ZigBee utilizes these security services that the data of transmission are carried out encryption, and functions such as authentication to the equipment of access network, key management are provided, and the network layer and the application layer of ZigBee definition all comprise this security system.

IEEE 802.15.4 security service is based on the AES-CCM* safe mode and generates a series of security mechanism.The encryption function that uses in the IEEE 802.15.4 regulation AES-CCM* safe mode is the AES AES of the grouping of 128 bit data and 128 keys, i.e. AES-128 AES.The CCM* pattern is the expansion of CCM (Counter with Cipher block chaining-Message authentication code) encryption mode.The CCM pattern has combined CTR data encryption pattern (Counter Mode) and CBC-MAC authentication pattern (Cipher Block Chaining-Message Authentication Code) and the safe mode of deriving out; Both comprise the enciphering/deciphering functional mode, comprised the authentication pattern again.The CCM* pattern can also use the CTR data to add/close pattern (Counter Mode) and CBC-MAC authentication pattern (Cipher Block Chaining-Message Authentication Code) separately except can using the CCM pattern.

2.AES AES

(Advanced Encryption Standard AES), is published on FIPS PUB 197 by National Institute of Standards and Technology (NIST), and becomes effective standard on May 26th, 2002 Advanced Encryption Standard in the cryptography November 26 calendar year 2001.The AES AES is called the Rijndael AES again, and this algorithm is designed by Belgian cryptologist Joan Daemen and Vincent Rijmen, and this standard is used for substituting original DES, analyzed in many ways and widely the whole world use.

AES is the password that an iteration, symmetric key divide into groups, and it can use 128,192 and 256 keys, and with 128 (16 byte) block encryption and data decryptions.ZigBee/IEEE 802.15.4 adopts 128 fixing keys, is designated as AES-128.No matter for AES AES or decipherment algorithm, all be to use the operation of round transformation.The round transformation number of operations is relevant with the figure place of key, and AES-128 wheel number is 10 to take turns.Only used the AES-128 AES in the ZigBee/IEEE 802.15.4 agreement, AES-128 AES flow process is as shown in Figure 1, expressly at first carries out the operation that a round key adds, and carries out 10 then and takes turns the round transformation operation.Fig. 2 is the round transformation schematic flow sheet, and is as shown in Figure 2, and round transformation comprises four operations: byte replacement, row displacement, row mix replacement and round key adds, and wherein the 10th take turns and do not comprise row in the round transformation and mix replacement operation.

3.CBC-MAC authentication pattern

The CBC-MAC pattern can be used following formulate:

X ₀?:=?0 ¹²⁸;

X _i+1?:=? E _Key( X _i⊕ B _i),?for? i=0,?…,? n;

T?:=? First_M_Bytes( X _n+1).

In the formula E _Key() for key does KeyThe AES-128 encryption function, 0 ¹²⁸Represent complete 0 character string of 128 bits.Fig. 3 is a CBC-MAC authentication code production process sketch map, among the figure FMBBefore intercepting MIndividual byte is promptly in the formula First_M_Bytes() function.

As shown in Figure 3, transmit leg is the aided verification data set of 128 bits according to packet B ₀~ B _nProduce MThe byte identifying code T, data set B ₀Be plaintext additional information, data set B ₁~ B _tBe the additional identification information data a, data set B _T+1~ B _nBe the information data plaintext bThe recipient forms data set according to the plaintext additional information B ₀, the additional identification information data aForm data set B ₁~ B _t, and the plaintext of information data that receive, after the deciphering B 'Form the aided verification data set B _T+1~ B _n, produce one according to process shown in Figure 3 with transmit leg is the same MThe byte identifying code T ', will T 'With transmit leg identifying code that receive and through deciphering TCompare, if T 'With TIdentical, then think the plaintext of information data that receive, after the deciphering B 'Plaintext with the transmission information data of transmit leg bIdentical, if T 'With TInequality, think that then the data that receive were distorted.

4.CTR data enciphering/deciphering pattern

CTR data encryption expression formula is:

S ₀:=? E _Key( A ₀);? U?:=? T⊕ First_M_Bytes( S ₀);

C _j:=? E _Key( A _j)⊕ M _j,?for? j=1,?…,? m.

Fig. 4 is a CTR enciphering/deciphering schematic flow sheet.As shown in Figure 4, transmit leg is at first with identifying code TBe encrypted as U, then expressly with information data bBe grouped into M _j, every group leader is 128 bits, if last group less than 128 bits are then filled 0 and supplied, AES-128 encrypts one group of data at every turn, generates information encrypt data group C _j A _jBe the secondary encryption data set, by plaintext additional information and count value jForm count value jBe 0 ~ mTransmit leg sends according to following order: C ₁..., C _m, U

CTR data decryption expression formula is:

S ₀:=? E _Key( A ₀);? T?:=? U⊕ First_M_Bytes( S ₀);

M _j:=? E _Key( A _j)⊕ C _j,?for? j=1,?…,? m.

As shown in Figure 4, the recipient is at first with the encrypted authentication sign indicating number UDecipher and do T, then to information encrypt data group C _jDecipher.

5. aided verification data set

The aided verification data set B ₀~ B _nMainly containing three parts forms: comprise the expressly data set of additional information 1. B ₀2. comprise the additional identification information data aData set B ₁~ B _t3. comprise information data expressly bData set B _{t+ 1}~ B _n

1. B ₀Data burst structure

B ₀Data burst structure is as shown in Figure 5.Can know by Fig. 5 B ₀Data set is made up of following data:

B ₀=Flags || NONCE|| LM, || be bound symbol;

Flags=Reserved wherein || Adata || ( M-2)/2|| L

The definition of each field among the Flags:

Reserved: keep the position, should be made as ' 0 ' state.

Adata: additional identification information data aFlag bit, if Adata=' 1 ', then showing has the additional identification information data a, and data set B ₁~ B _tBe the additional identification information data aIf Adata=' 0 ', then showing does not have the additional identification information data a, data set B ₁~ B _nBe information data clear data group M ₁~ M _m, at this moment m= n

( M-2 )/ 2: MAuthentication code TLength is unit with the byte.When M>0, the numerical value of these three bits be ( M-2 )/ 2, if M=0, the numerical value of these three bits is 0.Stipulate among the ZigBee/IEEE 802.15.4 MSpan is 0,4,8,16.

L: LMLength, bitwise, stipulate among the ZigBee/IEEE 802.15.4 L=2.

B ₀The definition of each field of data burst structure:

NONCE: this field data is by the information source address, and information such as frame counter and safe class are formed.

LM: information data is expressly bLength, be unit with the byte, span is 0≤ LM≤2 ^{8

L}

2. B ₁~ B _tData burst structure

B ₁~ B _tData set comprises the additional identification information data aWith and length information LA, be about to LA|| aBe grouped into B ₁~ B _t, every group 128 bit is if last group less than 128 bits are then filled ' 0 ' polishing.

3. B _{t+ 1}~ B _nData burst structure

B _{t+ 1}~ B _nData set is an information data clear data group M ₁~ M _m

6. secondary encryption data set A _j

The secondary encryption data set A _j( j=0 ..., m) structure is as shown in Figure 6, can be known data set by Fig. 6 A _jStructure and data set B ₀Structure is very similar, B ₀Data set has comprised A _jAll information of structure are except count value Counter jTherefore A _jCan be according to data set B ₀With a Counter Value jConstitute.

7.CCM* parallel running pattern

Because B _{t+ 1}~ B _nData set is exactly an information data clear data group M ₁~ M _m, so CBC-MAC arithmetic operation and CTR arithmetic operation can parallel runnings.Fig. 7 is a CCM* parallel running schematic flow sheet, and dotted portion is the CTR deciphering among the figure, and identifying code is confirmed part. FWZB(being Filled With ' 0 ' Bite) act as, UThe back fills 0, is filled to 16 bytes (128 bit) data set U|| 0.

As shown in Figure 7, when transmit leg carries out data encryption/authentication code and produces parallel running, at first to data set B ₀~ B _tCarry out the CBC-MAC arithmetic operation, right then B _{t+ 1}~ B _nData set carries out CBC-MAC arithmetic operation and the operation of CTR cryptographic calculation simultaneously.For the CTR arithmetic operation, with identifying code TCryptographic calculation operation be put into last, and to before the intercepting MThe operation of individual byte is put into after the encryption, xThe perhaps arbitrary value Bit String formed of ' 1 ' bit of ' 0 ' bit of serving as reasons.

The recipient carries out data decryption/authentication code when confirming parallel running, also is at first to data set B ₀~ B _tCarry out the CBC-MAC arithmetic operation, right then C ₁..., C _mCarry out CTR decrypt operation operation, simultaneously to after the deciphering B _{t+ 1}~ B _nData set carries out the CBC-MAC arithmetic operation.For the operation of CTR decrypt operation, with identifying code UDecrypt operation operation be put into last, and will before arithmetic operation MByte UBe filled to 16 bytes (128 bit) data set U|| 0.Will U|| 0 deciphering does T||xAnd with CBC-MAC arithmetic operation result T'||xCarry out XOR, get behind the XOR before MIf byte is preceding MByte is 0 entirely, then TWith T'Identical, if be not 0 entirely, then TWith T'Inequality.

(8.MMO Matyas-Meyer-Oseas) Hash function

ZigBee agreement regulation, the key of AES-CCM* pattern is set up SKKE (Symmetric-Key Key Establishment) agreement by the symmetric key key and is set up.The SKKE agreement is used Hash message authentication mechanism HMAC(Hash Message Authentication Code) mechanism provides key confirmation, and the Hash function that the ZigBee standard is used is MMO Hash function, and regulation adopts the AES-128 AES to construct MMO Hash function.

MMO Hash function expression formula:

Hash ₀?: =0 ¹²⁸;

Hash _k: =E( Hash _k-1,? I _k)⊕ I _k, for?k=1,?…,? s;

HMAC: =Hash _s.

In the formula E( Key, x)= E _Key( x), i.e. AES-128 encryption function.Fig. 8 is a MMO Hash functional operation operational flowchart.As shown in Figure 8, the HASH function is according to the input data set I ₁~ I _sGenerate HMAC

9. relevant open source literature

About the circuit implementation of CCM* pattern, many open source literatures are also arranged both at home and abroad, the open source literature close with the present invention has:

(1) in the U.S. Pat 007831039B2 that has authorized, proposed to realize the circuit structure of CCM* encrypted/authenticated sign indicating number generation and the circuit structure that CCM* deciphering/authentication code is confirmed respectively, and realized the circuit structure of CCM* encrypted/authenticated sign indicating number generation and the circuit structure that CCM* deciphering/authentication code is confirmed respectively based on single AES encryption equipment based on two AES encryption equipments.

【ST?Microelectronics?Inc.?(Guido?Bertoni;?Jefferson?E.?Owen).? AES?ENCRYPTION?CIRCUITRY?WITH?CCM .?US007831039B2.?2010】。

In above-mentioned open source literature, produce circuit based on the CCM* encrypted/authenticated sign indicating number of single AES encryption equipment, with circuit based on the CCM* deciphering/authentication code affirmation of single AES encryption equipment be different circuits.

Summary of the invention

The present invention proposes a kind of security coprocessor circuit structure and control method thereof of the ZigBee of being applied to agreement.This circuit structure is through the control of control signal; Can realize the parallel processing function of the encrypted/authenticated sign indicating number generation of CCM* pattern in the ZigBee agreement; And the parallel processing function confirmed of the deciphering of CCM* pattern/authentication code, can also realize the CTR enciphering/deciphering function of CCM* pattern and the CBC-MAC authentication code generation/affirmation function of CCM* pattern separately; In addition, this circuit has also been realized MMO Hash function performance.

In order to achieve the above object, the present invention at first provides a kind of security coprocessor circuit structure of the ZigBee of being applied to agreement, and the technical scheme that is adopted is:

ZigBee safety association treatment circuit based on single AES encryption equipment is characterized in that:

Said circuit structure comprises: counter, secondary encryption data producer, selector MUX1, XOR device XOR1, selector MUX2, AES encryption equipment, key generator, selector MUX3, selector MUX4, register, XOR device XOR2 also comprise: signal input end mouth, data-in port, key input port and data-out port;

The signal input end of said counter is connected with the signal input end mouth;

A data input of said secondary encryption data producer is connected to counter output, and another data input pin is connected to data-in port, and signal input end is connected with the signal input end mouth;

The data input of said selector MUX1 is connected to data-in port, and another data input pin is connected to the output of XOR device XOR2, selects signal input part to be connected with the signal input end mouth;

The data input of said XOR device XOR1 is connected to the output of selector MUX1, and another data input pin is connected to the output of AES encryption equipment, and signal input end is connected with the signal input end mouth;

The data input of said selector MUX2 is connected to the output of secondary encryption data producer; A data input is connected to data-in port; A data input is connected to the output of XOR device XOR1, selects signal input part to be connected with the signal input end mouth;

The data input pin of said AES encryption equipment is connected to the output of selector MUX2, and the key input is connected to the output of key generator, and signal input end is connected with the signal input end mouth;

The data input pin of said key generator is connected to the output of selector MUX3, and signal input end is connected with the signal input end mouth;

The data input of said selector MUX3 is connected to the key input port, and another data input pin is connected to the output of XOR device XOR2, selects signal input part to be connected with the signal input end mouth;

The data input of said XOR device XOR2 is connected to the output of AES encryption equipment, and another data input pin is connected to the output of register, and signal input end is connected with the signal input end mouth;

The data input pin of said register is connected to the output of selector MUX4, and signal input end is connected with the signal input end mouth;

The data input of said selector MUX4 is connected to the output of XOR2; A data input is connected to data-in port; A data input is connected to the output of AES encryption equipment, selects signal input part to be connected with the signal input end mouth;

Said data-out port is connected to the output of XOR2.

The present invention further provides the control method of foregoing circuit structure, and concrete scheme is following:

Be applied to the security coprocessor circuit structure of ZigBee agreement; It is characterized in that through signal input end mouth input control signal; Under the control of control signal; Circuit is changed between six kinds of states, and six kinds of states comprise: " idle condition ", " CTR mode of operation ", " CBC-MAC mode of operation ", " CCM encrypted state ", " CCM decrypted state " and " HASH function status ":

Described " idle condition " is the initialization state of circuit, system power on or system reset after, circuit gets into " idle condition ", each parts quit work in the circuit;

Described " CTR mode of operation "; When control port input " CTR mode of operation " control signal; Circuit gets into " CTR mode of operation "; Realize the CTR encrypt/decrypt arithmetic operation in the ZigBee agreement, after accomplishing CTR encrypt/decrypt arithmetic operation, under control signal control, return " idle condition ";

Described " CBC-MAC mode of operation "; When control port input " CBC-MAC mode of operation " control signal; Circuit gets into " CBC-MAC mode of operation "; Realize the CBC-MAC authentication code generation/affirmation arithmetic operation in the ZigBee agreement, after accomplishing CBC-MAC authentication code generation/affirmation arithmetic operation, under control signal control, return " idle condition ";

Described " CCM encrypted state "; When control port input " CCM encrypted state " control signal; Circuit gets into " CCM encrypted state "; Realize that the CCM* encrypted/authenticated sign indicating number in the ZigBee agreement produces arithmetic operation, after accomplishing CCM* encrypted/authenticated sign indicating number generation arithmetic operation, under control signal control, return " idle condition ";

Described " CCM decrypted state "; When control port input " CCM decrypted state " control signal; Circuit gets into " CCM decrypted state "; Realize the CCM* deciphering/authentication code affirmation arithmetic operation in the ZigBee agreement, after accomplishing CCM* deciphering/authentication code affirmation arithmetic operation, under control signal control, return " idle condition ";

Described " HASH function status "; When control port input " HASH function status " control signal; Circuit gets into " HASH function status "; Realize the MMO HASH functional operation operation in the ZigBee agreement, after accomplishing MMO HASH functional operation operation, under control signal control, return " idle condition ".

AES encryption equipment used in the present invention adopts pipelined circuit; Pipeline series is more than the two-stage; Circuit is when realizing that CCM* encrypted/authenticated sign indicating number produces function or CCM* deciphering/authentication code affirmation function; The AES encryption equipment is handled two groups of data simultaneously, and when first group of data arrives second level and the above streamline in the second level, first order streamline is imported second group of data.

Circuit is formed CTR enciphering/deciphering arithmetic operation circuit by counter, secondary encryption data producer, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4 under " CTR mode of operation "; Key generator becomes the initial key input circuit with selector MUX3, is used for importing initial key KeyCircuit is when realizing CTR enciphering/deciphering function, and XOR device XOR1 and selector MUX1 quit work.

Circuit is formed CBC-MAC authentication code generation/affirmation arithmetic operation circuit by selector MUX1, XOR device XOR1, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4 under " CBC-MAC mode of operation "; Key generator becomes the initial key input circuit with selector MUX3, is used for importing initial key KeyCircuit is when realizing CBC-MAC authentication code generation/affirmation function, and counter and secondary encryption data producer quit work.

Circuit is at " CCM encrypted state " and under " CCM decrypted state "; Form CBC-MAC authentication code generation/affirmation arithmetic operation circuit by selector MUX1, XOR device XOR1, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4, be used for realizing the authentication code generation/affirmation arithmetic operation in the CCM* pattern; Form CTR enciphering/deciphering arithmetic operation circuit by counter, secondary encryption data producer, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4, be used for realizing the data enciphering/deciphering arithmetic operation in the CCM* pattern; Form the initial key input circuit by selector MUX3 and key generator, be used for importing initial key Key

Circuit is under " HASH function status "; Form MMO HASH functional operation function circuit by selector MUX2, AES encryption equipment, key generator, selector MUX3, XOR device XOR2, register and selector MUX4, be used for realizing MMO HASH functional operation operation; Circuit is when realizing the HASH function performance, and counter, secondary encryption data producer, selector MUX1 and XOR device XOR1 quit work.

The present invention uses hardware circuit to realize the arithmetic operation and the MMO HASH function of AES-CCM* safe mode fully; Reduced the load of CPU in the ZigBee system; Also avoided unnecessary software attacks; Circuit proposed by the invention all both can have been realized the parallel processing function that the encrypted/authenticated sign indicating number of CCM* pattern in the ZigBee agreement produces simultaneously; And the parallel processing function of the deciphering of CCM* pattern/authentication code affirmation, the CTR enciphering/deciphering function of realization CCM* pattern, and the CBC-MAC authentication code generation/affirmation function of CCM* pattern separately.

Description of drawings

Fig. 1 AES encryption flow sketch map;

Fig. 2 encryption round shift step sketch map;

Fig. 3 CBC-MAC authentication code production process sketch map;

Fig. 4 CTR enciphering/deciphering schematic flow sheet;

Fig. 5 B ₀The data burst structure sketch map;

Fig. 6 A _jThe data burst structure sketch map;

Fig. 7 CCM* parallel running schematic flow sheet;

Fig. 8 MMO Hash functional operation operational flowchart;

Fig. 9 electrical block diagram of the present invention;

Figure 10 circuit state of a control transition diagram;

The cycling circuit structural representation of Figure 11 AES AES;

The AES encryption equipment of the serial circuit structure of Figure 12 two level production lines;

The AES encryption equipment of the cycling circuit structure of Figure 13 two level production lines;

The electrical block diagram of Figure 14 circuit working when " CTR mode of operation ";

The electrical block diagram of Figure 15 circuit working when " CBC-MAC mode of operation ";

The electrical block diagram of Figure 16 circuit working when " CCM encrypted state ";

The electrical block diagram of Figure 17 circuit working when " CCM decrypted state ";

The electrical block diagram of Figure 18 circuit working when " HASH function status ".

Embodiment

With following be to combine specific embodiment that the present invention is done further description with reference to accompanying drawing.

1. circuit structure of the present invention

Referring to Fig. 9; A kind of security coprocessor circuit structure that is applied to the ZigBee agreement comprises: counter, secondary encryption data producer, selector MUX1, XOR device XOR1, selector MUX2, AES encryption equipment, key generator, selector MUX3, selector MUX4, register, XOR device XOR2.

Circuit structure also comprises: signal input end mouth, data-in port, key input port and data-out port.

Wherein, the control signal port is connected in the circuit on each parts, and the signal of control port input comprises the enable signal of each parts and the selection signal of selector, and the dotted line among Fig. 9 is a control signal wire.

As shown in Figure 9, the signal input end of counter is connected with the signal input end mouth; A data input of secondary encryption data producer is connected to counter output, and another data input pin is connected to data-in port, and signal input end is connected with the signal input end mouth; The data input of selector MUX1 is connected to data-in port, and another data input pin is connected to the output of XOR device XOR2, selects signal input part to be connected with the signal input end mouth; The data input of XOR device XOR1 is connected to the output of selector MUX1, and another data input pin is connected to the output of AES encryption equipment, and signal input end is connected with the signal input end mouth; The data input of selector MUX2 is connected to the output of secondary encryption data producer; A data input is connected to data-in port; A data input is connected to the output of XOR device XOR1, selects signal input part to be connected with the signal input end mouth; The data input pin of AES encryption equipment is connected to the output of selector MUX2, and the key input of AES encryption equipment is connected to the output of key generator, and signal input end is connected with the signal input end mouth; The data input pin of key generator is connected to the output of selector MUX3, and signal input end is connected with the signal input end mouth; The data input of selector MUX3 is connected to the key input port, and another data input pin is connected to the output of XOR device XOR2, selects signal input part to be connected with the signal input end mouth; The data input of XOR device XOR2 is connected to the output of AES encryption equipment, and another data input pin is connected to the output of register, and signal input end is connected with the signal input end mouth; The data input pin of register is connected to the output of selector MUX4, and signal input end is connected with the signal input end mouth; The data input of selector MUX4 is connected to the output of XOR device XOR2; A data input is connected to data-in port; A data input is connected to the output of AES encryption equipment, selects signal input part to be connected with the signal input end mouth; Data-out port is connected to the output of XOR device XOR2.

Circuit is through signal input end mouth input control signal; Under the control of control signal, circuit realizes that CTR enciphering/deciphering function, CBC-MAC authentication code generation/affirmation function, CCM* encrypted/authenticated sign indicating number produce function, CCM* deciphering/authentication code is confirmed function and HASH function performance.

2. circuit working state and control method thereof

Referring to Figure 10; Under the control of the control signal that the signal input end mouth is imported, circuit of the present invention can be operated in six kinds of states: " idle condition ", " CTR mode of operation ", " CBC-MAC mode of operation ", " CCM encrypted state ", " CCM decrypted state " and " HASH function status ".

" idle condition " is the initialization state of circuit, system power on or system reset after, circuit gets into " idle condition ".Under " idle condition ", each parts quit work in the circuit.

Shown in figure 10, when the signal input end mouth provided " CTR mode of operation " control signal, circuit got into " CTR mode of operation ".Under " CTR mode of operation ", circuit is realized the CTR enciphering/deciphering arithmetic operation in the ZigBee agreement.After circuit is accomplished CTR enciphering/deciphering arithmetic operation, under control signal control, return " idle condition ".

Shown in figure 10, when the signal input end mouth provided " CBC-MAC mode of operation " control signal, circuit got into " CBC-MAC mode of operation ".Under " CBC-MAC mode of operation ", circuit is realized the CBC-MAC authentication code generation/affirmation arithmetic operation in the ZigBee agreement.After circuit is accomplished CBC-MAC authentication code generation/affirmation arithmetic operation, under control signal control, return " idle condition ".

Shown in figure 10, when the signal input end mouth provided " CCM encrypted state " control signal, circuit got into " CCM encrypted state ".Under " CCM encrypted state ", circuit realizes that the CCM* encrypted/authenticated sign indicating number in the ZigBee agreement produces arithmetic operation.After circuit is accomplished CCM* encrypted/authenticated sign indicating number generation arithmetic operation, under control signal control, return " idle condition ".

Shown in figure 10, when the signal input end mouth provided " CCM decrypted state " control signal, circuit got into " CCM decrypted state ".Under " CCM decrypted state ", circuit is realized the CCM* deciphering/authentication code affirmation arithmetic operation in the ZigBee agreement.After circuit is accomplished CCM* deciphering/authentication code affirmation arithmetic operation, under control signal control, return " idle condition ".

Shown in figure 10, when the signal input end mouth provided " HASH function status " control signal, circuit got into " HASH function status ".Under " HASH function status ", circuit is realized the MMO HASH functional operation operation in the ZigBee agreement.After circuit is accomplished MMO HASH functional operation operation, under control signal control, return " idle condition "

3.AES encryption equipment circuit structure

The AES encryption equipment is used to realize the AES-128 AES.Two kinds of circuit structures, serial circuit structure and cycling circuit structure are adopted in the realization of AES AES circuit usually.

Fig. 1 can be regarded as the serial circuit structural representation of an AES AES, and clear data to be encrypted at first gets into " round key an adds " circuit module, gets into 10 " round transformation " circuit modules then successively, exports ciphertext at last.

Figure 11 is the cycling circuit structural representation of an AES AES; As can beappreciated from fig. 11, the entire circuit of cycling circuit structure only realizes a round transformation operation; Clear data to be encrypted circulates in circuit 10 times, and completion 10 is taken turns wheel operation and added a key add operation.The clear data of input is under control signal control; At first get into " round key adds " circuit module; Control signal is sent the data of " round key adds " output into " byte replacement " circuit module then; The data of " byte replacement " circuit module output are directly given " row displacement " circuit module; Control signal is sent the data of " row is shifted " output into " being listed as the mixing replacement " circuit module afterwards, and control signal feeds back to " round key adds " circuit module with the data of " the row mixing is replaced " circuit module output afterwards.So after 9 operations of circulation; During the 10th operation; Control signal is fed to " round key adds " circuit module with the data of " row displacement " output; And do not pass through " row mix replacement " circuit module, and the dateout of this feedback " round key adds " circuit module is afterwards exported as ciphertext.Figure 11 is the AES encryption equipment of the cycling circuit structure of a round transformation operation, in existing open source literature, also has the AES encryption equipment of the cycling circuit structure of other many forms.

AES encryption equipment circuit used in the present invention; Need to adopt the pipelined circuit more than the two-stage; Figure 12 is the embodiment of AES encryption equipment of the serial circuit structure of one two level production line; This embodiment will " round key adds " and preceding 5 be taken turns the first order of " round transformation " circuit module (i.e. " round transformation 1 " ~ " round transformation 5 ") as streamline, and the second level of " round transformation " circuit module (i.e. " round transformation 6 " ~ " round transformation 10 ") as streamline is taken turns in back 5.When the AES encryption equipment need be encrypted two groups of data simultaneously, when first group of data gets into second level streamline (first group of data gets into " register 2 "), second group of data was input to first order streamline (promptly second group of data is input to " register 1 ").

There is multiple streamline implementation in the AES encryption equipment of serial circuit structure.For streamline is the AES encryption equipment of the serial circuit structure more than the two-stage, can specify first register to be " register 1 ", and other any registers are " register 2 ".When the AES encryption equipment need be encrypted two groups of data simultaneously, when first group of data got into " register 2 ", second group of data was input to " register 1 ".

Figure 13 is the embodiment of AES encryption equipment of the cycling circuit structure of one two level production line; This embodiment is with the first order of " round key adds " and " byte replacement " circuit module as streamline, with the second level of " row displacement " and " the row mixing is replaced " circuit module as streamline.When the AES encryption equipment need be encrypted two groups of data simultaneously, when first group of data gets into second level streamline (first group of data gets into " register 2 "), second group of data was input to first order streamline (promptly second group of data is input to " register 1 ").

So same, there is multiple streamline implementation in the AES encryption equipment of cycling circuit structure.For streamline is the AES encryption equipment of the cycling circuit structure more than the two-stage, can specify first register to be " register 1 ", and other any registers are " register 2 ".When the AES encryption equipment need be encrypted two groups of data simultaneously, when first group of data got into " register 2 ", second group of data was input to " register 1 ".

4. the control method of circuit working of the present invention when " CTR mode of operation "

Referring to Figure 14, Figure 14 is the electrical block diagram of circuit working of the present invention when " CTR mode of operation ".Circuit is formed CTR enciphering/deciphering arithmetic operation circuit by counter, secondary encryption data producer, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4 when realizing CTR enciphering/deciphering function; Key generator becomes the initial key input circuit with selector MUX3, is used for importing initial key KeyCircuit is when realizing CTR enciphering/deciphering function, and XOR device XOR1 and selector MUX1 quit work, so do not show out among Figure 14.Dotted line representes that the circuit on this path only at a time works among Figure 14, and the operating time is very short.

In conjunction with Fig. 4, the control method of circuit structure shown in Figure 14 is described.Circuit is when realizing CTR enciphering/deciphering function, and control method specifically may further comprise the steps:

The first step, circuit are at first imported initial key Key, and with initial key KeyRead in key generator. KeyOnly import once, so interlock circuit dots among Figure 14, concrete operations are:

(1) under control signal control, selector MUX3 is with the initial key on the key input port KeyBe sent to the key generator data input pin;

(2) under control signal control, key generator is with initial key KeyRead in its internal register;

In second step, secondly circuit imports the secondary encryption data set A ₀, need with A ₀Read in the secondary encryption data producer, be the secondary encryption data set A _jGeneration prepare, the secondary encryption data producer only reads in once A ₀, so interlock circuit dots among Figure 14.Be input to the operation of secondary encryption data producer, concrete operations are:

Under control signal control, the secondary encryption data producer is with the data set on the data-in port A ₀Read in its internal register;

In the 3rd step, circuit is imported the clear data group once more M _jOr encrypt data group C _j, wherein j=0 ..., m, mBe natural number, circuit need be accomplished the clear data group M _jCTR cryptographic calculation operation or encrypt data group C _jCTR decrypt operation operation, concrete operations are:

(1) under control signal control, the rolling counters forward value adds 1, and the counter initial value is 0, and counter is with current count value jOutput to secondary encryption data producer data input pin;

(2) under control signal control, the secondary encryption data producer is according to current count value jWith the data set in the internal register A ₀, generate current secondary encryption data set A _j, and will A _jOutput to data input of selector MUX2;

(3) under control signal control, selector MUX2 will A _jOutput to AES encryption equipment data input pin; Simultaneously, selector MUX4 is with the data set of data-in port input M _j/ C _jBe sent to the register data input;

(4) under control signal control, the AES encryption equipment is right A _jEncrypt, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to AES encryption equipment key input, the AES encryption equipment uses sub-key right A _jEncrypt encrypted result Y _jOutput to data input of XOR device XOR2;

Simultaneously, register is with data set M _j/ C _jBe sent to another data input pin of XOR2;

(5) under control signal control, XOR device XOR2 is to data set M _j/ C _jWith data set Y _jCarry out XOR, the XOR result C _j/ M _jOutput to data-out port.

5. the control method of circuit working of the present invention when " CBC-MAC mode of operation "

Referring to Figure 15, Figure 15 is the electrical block diagram of circuit working of the present invention when " CBC-MAC mode of operation ".Circuit is formed CBC-MAC authentication code generation/affirmation arithmetic operation circuit by selector MUX1, XOR device XOR1, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4 when realizing CBC-MAC authentication code generation/affirmation function; Key generator becomes the initial key input circuit with selector MUX3, is used for importing initial key KeyCircuit is when realizing CBC-MAC authentication code generation/affirmation function, and counter and secondary encryption data producer quit work, so do not show out among Figure 15.Dotted line representes that the circuit on this path only at a time works among Figure 15, and the operating time is very short.

In conjunction with Fig. 3, the control method of circuit structure shown in Figure 15 is described.Circuit is when realizing CBC-MAC authentication code generation/affirmation function, and control method specifically may further comprise the steps:

The first step, circuit are at first imported initial key Key, and with initial key KeyRead in key generator. KeyOnly import once, so interlock circuit dots among Figure 15.Initial key KeyRead in the key generator operation, concrete operations are:

In second step, secondly circuit imports data set B _i, wherein i=0 ..., n, and to the data set data set B _iCarry out the CBC-MAC arithmetic operation, concrete operations are:

(1) under control signal control, selector MUX1 is with the data set on the data-in port B _iBe sent to the data input of XOR device XOR1;

(2) under control signal control, XOR device XOR1 is to data set B _iWith data set X _iCarry out XOR, X _iBe the output valve of AES encryption equipment, wherein, the initial value of AES encryption equipment output X ₀=0 ¹²⁸, 0 ¹²⁸Represent 128 bits 0, the XOR result D _iOutput to the input of the data input AES encryption equipment of selector MUX2;

(3) under control signal control, selector MUX2 is with the dateout of XOR device XOR1 D _iSend into the data input pin of AES encryption equipment, and the data of input are encrypted, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to the key input of AES encryption equipment, the AES encryption equipment is encrypted data according to sub-key, encrypted result X _{i+ 1}Export from AES encryption equipment output;

In the 3rd step, circuit is accomplished the operation that authentication code produces or authentication code is confirmed, only carry out once because circuit is accomplished the operation that authentication code produces or authentication code is confirmed, so interlock circuit dots among Figure 15.Circuit is accomplished the operation that authentication code produces, and is different with the operation that authentication code is confirmed, wherein:

(1) if carrying out authentication code produces, concrete operations are:

1. under control signal control, with the register zero clearing;

2. under control signal control, with the last operation result of AES encryption equipment TOutput to data input of XOR device XOR2, and register register value 0 is outputed to another data input pin of XOR device XOR2;

3. under control signal control, the XOR result T=T⊕ 0 outputs to data-out port;

(2) produce affirmation if carry out authentication code, concrete operations are:

1. under control signal control, selector MUX4 is with the former authentication code of data input pin input TSend into register;

2. under control signal control, with the last operation result of AES encryption equipment T 'Output to data input of XOR device XOR2, and with the register register value TOutput to another data input pin of XOR device XOR2;

3. under control signal control, the XOR result E=T '⊕ TOutput to data-out port;

6. the control method of circuit working of the present invention when " CCM encrypted state "

Referring to Figure 16, Figure 16 is the electrical block diagram of circuit working of the present invention when " CCM encrypted state ".Circuit is when realizing that CCM* encrypted/authenticated sign indicating number produces function; Form the CBC-MAC authentication code by selector MUX1, XOR device XOR1, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4 and produce the arithmetic operation circuit, be used for realizing that the authentication code in the CCM* pattern produces arithmetic operation; Form CTR cryptographic calculation function circuit by counter, secondary encryption data producer, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4, be used for realizing the data encryption arithmetic operation in the CCM* pattern; Form the initial key input circuit by selector MUX3 and key generator, be used for importing initial key KeyDotted line representes that the circuit on this path only at a time works among Figure 16, and the operating time is very short.

In conjunction with Fig. 7, the control method of circuit structure shown in Figure 16 is described.Circuit is when realizing that CCM* encrypted/authenticated sign indicating number produces function, and control method specifically may further comprise the steps:

The first step, circuit are at first imported initial key Key, and with initial key KeyRead in key generator. KeyOnly import once, so dot among Figure 16.Initial key KeyRead in the key generator operation, concrete operations are:

In second step, circuit secondly input comprises the expressly aided verification data set of additional information B ₀With comprise additional identification information aThe aided verification data set B ₁~ B _t, tBe natural number, and t< N,This moment, circuit had two operations to carry out simultaneously, operation be with B ₀Read in the secondary encryption data producer, another operation is right B ₀~ B _tCarry out the CBC-MAC arithmetic operation.

(1) the secondary encryption data producer reads in B ₀, be the secondary encryption data set A _jGeneration prepare, the secondary encryption data producer only reads in once B ₀, so dot among Figure 16.With the aided verification data set B ₀Be input to the operation of secondary encryption data producer, concrete operations are:

Under control signal control, the secondary encryption data producer is with the data set on the data-in port B ₀Read in its internal register;

(2) aided verification data set B ₀~ B _tThe CBC-MAC arithmetic operation, concrete operations are:

1. under control signal control, selector MUX1 is with the data set on the data-in port B _iBe sent to the data input of XOR device XOR1, wherein i=0 ..., t

2. under control signal control, XOR device XOR1 is to data set B _iWith data set X _iCarry out XOR, X _iBe the output valve of AES encryption equipment, wherein, the initial value of AES encryption equipment output X ₀=0 ¹²⁸, 0 ¹²⁸Represent 128 bits 0, the XOR result D _iOutput to the input of the data input AES encryption equipment of selector MUX2;

3. under control signal control, selector MUX2 is with the dateout of XOR device XOR1 D _iSend into the data input pin of AES encryption equipment, and the data of input are encrypted, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to the key input of AES encryption equipment, the AES encryption equipment is encrypted data according to sub-key, encrypted result X _{i+ 1}Export from AES encryption equipment output;

In the 3rd step, circuit is imported once more and is comprised information data expressly bThe aided verification data set B _{t+ 1}~ B _n, nBe natural number, to data set B _{t+ 1}~ B _nOperation have two, an operation is right B _{t+ 1}~ B _nCarry out the CBC-MAC arithmetic operation, another is to carry out the operation of CTR cryptographic calculation, and two operations are carried out simultaneously, and concrete operations are:

(1) under control signal control, the rolling counters forward value adds 1, and the counter initial value is 0, and counter is with current count value jOutput to secondary encryption data producer data input pin, wherein j=1 ..., m; M=n-t

Simultaneously, under control signal control, selector MUX1 is with the data set on the data-in port B _iBe sent to the data input of XOR device XOR1, wherein i= t+ 1 ..., n

Simultaneously, under control signal control, selector MUX4 is with the data set on the data-in port B _iBe sent in the register;

(2) under control signal control, the secondary encryption data producer is according to current count value jWith the data set in the internal register B ₀, generate current secondary encryption data set A _j, and will A _jOutput to data input of selector MUX2;

Simultaneously, under control signal control, XOR device XOR1 is to data set B _iWith data set X _iCarry out XOR, X _iBe the output valve of AES encryption equipment, the XOR result D _iOutput to the data input of selector MUX2;

(3) under control signal control, MUX2 is at first with data set A _jOutput to the AES encryption equipment, and to data set A _jCarry out cryptographic operation, work as data set A _jWhen getting into the above streamline in the second level and the second level of AES encryption equipment, MUX2 is with data set D _iOutput to the first order streamline of AES encryption equipment, the AES encryption equipment is simultaneously to data set A _jAnd data set D _iCarry out cryptographic operation;

Simultaneously, under control signal control, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to AES encryption equipment key input, the AES encryption equipment uses sub-key to data set A _jAnd data set D _iEncrypt;

(4) AES encryption equipment output data groups at first A _jEncrypted result Y _j, under control signal control, the AES encryption equipment is with data set Y _jOutput to data input of XOR device XOR2; Simultaneously, register is with data set B _iBe sent to another data input pin of XOR device XOR2, XOR device XOR2 is to data set B _iWith data set Y _jCarry out XOR, the XOR result C _jOutput to data-out port; AES encryption equipment output data groups subsequently D _iEncrypted result X _{i+ 1}

The 4th step, the last identifying code that the CBC-MAC computing is produced of accomplishing of circuit TCarry out the operation of CTR cryptographic calculation, concrete operations are:

(1) under control signal control, selector MUX4 exports the AES encryption equipment X _{n+ 1}Be sent in the register, X _{n+ 1}Be data set B ₀~ B _nThe CBC-MAC operation result, X _{n+ 1}By MThe identifying code of byte TAnd 16- MAny binary bits string of byte xForm, promptly T|| x

Simultaneously, under control signal control, the zero clearing of rolling counters forward value, and current count value 0 outputed to the data input pin of secondary encryption data producer;

(2) under control signal control, the secondary encryption data producer is according to the data set in current count value 0 and the internal register B ₀, generate current secondary encryption data set A ₀, and will A ₀Output to data input of selector MUX2;

(3) under control signal control, selector MUX2 will A ₀Output to the data input pin of AES encryption equipment;

(4) under control signal control, the AES encryption equipment is right A ₀Encrypt, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to the key input of AES encryption equipment, the AES encryption equipment uses sub-key right A ₀Encrypt encrypted result Y ₀Output to data input of XOR device XOR2;

(5) under control signal control, XOR device XOR2 is to data set X _{n+ 1}With data set Y ₀Carry out XOR, the XOR result U|| xOutput to data-out port, the XOR result U|| xBy MThe encrypted authentication sign indicating number of byte UAnd 16- MAny binary bits string of byte xForm.

7. the control method of circuit working of the present invention when " CCM decrypted state "

Referring to Figure 17, Figure 17 is the electrical block diagram of circuit working of the present invention when " CCM decrypted state ".Circuit is when realizing that CCM* deciphering/authentication code is confirmed function; Form the CBC-MAC authentication code by selector MUX1, XOR device XOR1, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4 and confirm the arithmetic operation circuit, be used for realizing the authentication code affirmation arithmetic operation in the CCM* pattern; Form CTR decrypt operation function circuit by counter, secondary encryption data producer, selector MUX2, AES encryption equipment, XOR device XOR2, register and selector MUX4, be used for realizing the data decryption arithmetic operation in the CCM* pattern; Form the initial key input circuit by selector MUX3 and key generator, be used for importing initial key KeyDotted line representes that the circuit on this path only at a time works among Figure 17, and the operating time is very short.

In conjunction with Fig. 7, the control method of circuit structure shown in Figure 17 is described.Circuit is when realizing that CCM* deciphering/authentication code is confirmed function, and control method specifically may further comprise the steps:

The first step, circuit are at first imported initial key Key, and with initial key KeyRead in key generator. KeyOnly import once, so dot among Figure 17.Initial key KeyRead in the key generator operation, concrete operations are:

In second step, circuit secondly input comprises the expressly aided verification data set of additional information B ₀With comprise additional identification information aThe aided verification data set B ₁~ B _t-1, this moment, circuit had two operations to carry out simultaneously, operation be with B ₀Read in the secondary encryption data producer, another operation is right B ₀~ B _t-1Carry out the CBC-MAC arithmetic operation.

(1) the secondary encryption data producer reads in B ₀, be the secondary encryption data set A _jGeneration prepare, the secondary encryption data producer only reads in once B ₀, so dot among Figure 17.With the aided verification data set B ₀Be input to the operation of secondary encryption data producer, concrete operations are:

(2) aided verification data set B ₁~ B _t-1The CBC-MAC arithmetic operation, concrete operations are:

1. under control signal control, selector MUX1 is with the data set on the data-in port B _iBe sent to the data input of XOR device XOR1, wherein i=0 ..., t-1;

In the 3rd step, circuit is imported the aided verification data set once more B _t, information encrypt data group C ₂~ C _m, and encrypted authentication code data group U|| 0, this moment, circuit had two arithmetic operations to carry out simultaneously, and one is data set C ₁~ C _m, U|| 0 carries out the operation of CTR decrypt operation, and another is to the data set after the deciphering B _t~ B _nCarry out the CBC-MAC arithmetic operation, concrete operations are:

(1) if the current count value of counter jLess than m, wherein j=0 ..., m; M=n-t, m, n, tBe natural number, under control signal control, count value adds 1, if the current count value of counter jEqual m, under control signal control, the count value zero clearing; Count value after counter will calculate jOutput to secondary encryption data producer data input pin;

Simultaneously, under control signal control, selector MUX1 is with data set B _iBe sent to data input of XOR device XOR1, wherein i= t..., n, B _tFrom data-in port, B _{t+ 1}~ B _nOutput port from XOR device XOR2;

(2) under control signal control, the secondary encryption data producer is according to count value jWith the data set in the internal register B ₀, generate current secondary encryption data set A _j, and will A _jOutput to another data input pin of selector MUX2;

Simultaneously, under control signal control, XOR device XOR1 is to data set B _iWith data set X _iCarry out XOR, X _iBe AES encryption equipment output valve, the XOR result outputs to the data input of selector MUX2;

Simultaneously, under control signal control, selector MUX4 is with the data set on the data-in port C _j/ U|| 0 is sent in the register;

(4) AES encryption equipment output data groups at first A _jEncrypted result Y _j, under control signal control, the AES encryption equipment is with data set Y _jOutput to data input of XOR device XOR2; Simultaneously, register is with data set C _j/ U|| 0 is sent to another data input pin of XOR device XOR2, and XOR device XOR2 is to data set C _j/ U|| 0 and data set Y _jCarry out XOR, the XOR result M _j(be data set B _T+j/ T|| x) output to data-out port; AES encryption equipment output data groups subsequently D _iEncrypted result X _{i+ 1}

In the 4th step, circuit is at last to identifying code TConfirm operation, promptly to data set U|| the data set after 0 deciphering T|| xWith the CBC-MAC operation result T '|| xCompare, concrete operations are:

(1) under control signal control, selector MUX4 is with the XOR result of XOR device XOR2 output T|| xOutput in the register XOR T|| xThe result by MThe identifying code of byte TAnd 16- MAny binary bits string of byte xForm;

(2) under control signal control, XOR device XOR2 reads in the data set of AES encryption equipment output respectively X _{n+ 1}, and the data set of register output T|| x, X _{n+ 1}Be data set B ₀~ B _nThe CBC-MAC operation result, X _{n+ 1}By the identifying code that regenerates T ', and any binary bits string xForm, promptly T '|| x, T 'Length does MByte, xLength is 16- MByte, XOR device XOR2 is to data set T|| xAnd data set T '|| xCarry out XOR, and with the XOR result EOutput to the authentication result output port.

8. the control method of circuit working of the present invention when " HASH function status "

Referring to Figure 18, Figure 18 is the sketch map of circuit working of the present invention when " HASH function status ".Circuit is when realizing the HASH function performance; Form MMO HASH functional operation function circuit by selector MUX2, AES encryption equipment, key generator, selector MUX3, XOR device XOR2, register and selector MUX4, be used for realizing MMO HASH functional operation operation; Circuit is when realizing the HASH function performance, and counter, secondary encryption data producer, selector MUX1 and XOR device XOR1 quit work, and therefore in Figure 18, does not show out.Dotted line representes that the circuit on this path only at a time works among Figure 18, and the operating time is very short.

In conjunction with Fig. 8, the control method of circuit structure shown in Figure 180 is described.Circuit is when realizing MMO HASH function performance, and its control method specifically may further comprise the steps:

(1) under control signal control, selector MUX2 is with the data set on the data-in port I _kBe sent to the data input pin of AES encryption equipment, wherein k=1 ..., s-1, sBe natural number;

(2) under control signal control, AES encryption equipment input data set I _k, and the data set to importing I _kEncrypt, in ciphering process, key generator is according to initial key Hash _k-1Produce 10 groups of sub-keys, wherein, Hash ₀Be the initial value of key generator internal register, and Hash ₀=0 ¹²⁸, and output to the key input of AES encryption equipment, the AES encryption equipment according to sub-key to data set I _kEncrypt, encrypted result outputs to the data input of XOR device XOR2;

Simultaneously, selector MUX4 is with the data set on the data-in port I _kBe sent in the register;

(3) under control signal control, XOR device XOR2 is to the encrypted result and the data set of AES encryption equipment I _kCarry out XOR, the XOR result Hash _kOutput to the output of XOR device XOR2;

(4) if k< s, under control signal control, selector MUX3 exports XOR device XOR2 Hash _kBe sent to the key generator data input pin, will Hash _kInitial key as next round MMO HASH functional operation;

If k= s, under control signal control, XOR device XOR2 operation result Hash _sAs MMO HASH functional operation result HMACOutput on the data-out port.

The present invention is described with reference to current execution mode; But those skilled in the art will be appreciated that; Above-mentioned execution mode only is used for explaining the present invention, is not to be used for limiting protection scope of the present invention, and is any within spirit of the present invention and principle scope; Any modification of being done, equivalence replacement, improvement all should be included within the rights protection scope of the present invention.

Claims

1. security coprocessor circuit structure that is applied to the ZigBee agreement is characterized in that:

The data input pin of said AES encryption equipment is connected to the output of selector MUX2, and the key input of AES encryption equipment is connected to the output of key generator, and signal input end is connected with the signal input end mouth;

The data input of said selector MUX4 is connected to the output of XOR device XOR2; A data input is connected to data-in port; A data input is connected to the output of AES encryption equipment, selects signal input part to be connected with the signal input end mouth;

Said data-out port is connected to the output of XOR device XOR2.

2. the security coprocessor circuit structure that is applied to the ZigBee agreement according to claim 1; It is characterized in that described AES encryption equipment adopts pipelined circuit; Pipeline series is more than the two-stage, and circuit is when realizing that CCM* encrypted/authenticated sign indicating number produces function or CCM* deciphering/authentication code affirmation function, and the AES encryption equipment is handled two groups of data simultaneously; When first group of data arrives second level and the above streamline in the second level, first order streamline is imported second group of data.

3. based on the control method of the said circuit structure of claim 1; It is characterized in that through signal input end mouth input control signal; Under the control of control signal; Circuit is changed between six kinds of states, and six kinds of states comprise: " idle condition ", " CTR mode of operation ", " CBC-MAC mode of operation ", " CCM encrypted state ", " CCM decrypted state " and " HASH function status ":

4. control method according to claim 3 is characterized in that, circuit is under " CTR mode of operation ", and control method specifically may further comprise the steps:

A. import initial key Key

B. import the secondary encryption data set A ₀

C. import the clear data group M _jOr encrypt data group C _j, wherein j=0 ..., m, mBe natural number;

Described step a is to accomplish initial key KeyBe input to the operation of key generator, further may further comprise the steps:

A1) under control signal control, selector MUX3 is with the initial key on the key input port KeyBe sent to the key generator data input pin;

A2) under control signal control, key generator is with initial key KeyRead in its internal register;

Described step b is to accomplish the secondary encryption data set A ₀Be input to the operation of secondary encryption data producer, concrete operations are:

Described step c is to accomplish the clear data group M _jCTR cryptographic calculation operation or encrypt data group C _jCTR decrypt operation operation, further may further comprise the steps:

C1) under control signal control, the rolling counters forward value adds 1, and the counter initial value is 0, and counter is with current count value jOutput to secondary encryption data producer data input pin;

C2) under control signal control, the secondary encryption data producer is according to current count value jWith the data set in the internal register A ₀, generate current secondary encryption data set A _j, and will A _jOutput to data input of selector MUX2;

C3) under control signal control, selector MUX2 will A _jOutput to AES encryption equipment data input pin;

Simultaneously, selector MUX4 is with the data set of data-in port input M _j/ C _jBe sent to the register data input;

C4) under control signal control, the AES encryption equipment is right A _jEncrypt, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to AES encryption equipment key input, the AES encryption equipment uses sub-key right A _jEncrypt encrypted result Y _jOutput to data input of XOR device XOR2;

C5) under control signal control, XOR device XOR2 is to data set M _j/ C _jWith data set Y _jCarry out XOR, the XOR result C _j/ M _jOutput to data-out port.

5. control method according to claim 3 is characterized in that, circuit is under " CBC-MAC mode of operation ", and its control method specifically may further comprise the steps:

A. import initial key Key

B. import data set B _i, wherein i=0 ..., n, nBe natural number;

C. authentication code generation/affirmation;

Described step b is to accomplish data set B _iThe CBC-MAC arithmetic operation, further may further comprise the steps:

B1) under control signal control, selector MUX1 is with the data set on the data-in port B _iBe sent to the data input of XOR device XOR1;

B2) under control signal control, XOR device XOR1 is to data set B _iWith data set X _iCarry out XOR, X _iBe the output valve of AES encryption equipment, wherein, the initial value of AES encryption equipment output X ₀=0 ¹²⁸, 0 ¹²⁸Represent 128 bits 0, the XOR result D _iOutput to the input of the data input AES encryption equipment of selector MUX2;

B3) under control signal control, selector MUX2 is with the dateout of XOR device XOR1 D _iSend into the data input pin of AES encryption equipment, and the data of input are encrypted, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to the key input of AES encryption equipment, the AES encryption equipment is encrypted data according to sub-key, encrypted result X _{i+ 1}Export from AES encryption equipment output;

Described step c is to accomplish the operation that authentication code produces or authentication code is confirmed, two operations are different, wherein:

C1) produce operation if carry out authentication code, further may further comprise the steps:

1. under control signal control, with the register zero clearing;

C2) produce affirmation if carry out authentication code, further may further comprise the steps:

3. under control signal control, the XOR result E=T '⊕ TOutput to data-out port.

6. control method according to claim 3 is characterized in that, circuit is under " CCM encrypted state ", and its control method specifically may further comprise the steps:

A. import initial key Key

B. import the aided verification data set B ₀~ B _t, tBe natural number;

C. import the aided verification data set B _{t+ 1}~ B _n, nBe natural number, t< n

D. identifying code TEncrypt;

Described step b is to accomplish the aided verification data set B ₀Be input to the secondary encryption data producer, and accomplish the aided verification data set B ₀~ B _tThe CBC-MAC arithmetic operation, two operations are carried out simultaneously, wherein:

B1) with the aided verification data set B ₀Be input to the operation of secondary encryption data producer, concrete operations are:

B2) aided verification data set B ₀~ B _tThe CBC-MAC arithmetic operation, further may further comprise the steps:

B2-1) under control signal control, selector MUX1 is with the data set on the data-in port B _iBe sent to the data input of XOR device XOR1, wherein i=0 ..., t

B2-2) under control signal control, XOR device XOR1 is to data set B _iWith data set X _iCarry out XOR, X _iBe the output valve of AES encryption equipment, wherein, the initial value of AES encryption equipment output X ₀=0 ¹²⁸, 0 ¹²⁸Represent 128 bits 0, the XOR result D _iOutput to the input of the data input AES encryption equipment of selector MUX2;

B2-3) under control signal control, selector MUX2 is with the dateout of XOR device XOR1 D _iSend into the data input pin of AES encryption equipment, and the data of input are encrypted, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to the key input of AES encryption equipment, the AES encryption equipment is encrypted data according to sub-key, encrypted result X _{i+ 1}Export from AES encryption equipment output;

Described step c is to accomplish the aided verification data set B _{t+ 1}~ B _nThe operation of CBC-MAC and CTR cryptographic calculation, further may further comprise the steps:

C1) under control signal control, the rolling counters forward value adds 1, and the counter initial value is 0, and counter is with current count value jOutput to secondary encryption data producer data input pin, wherein j=1 ..., m; M=n-t, mBe natural number;

C2) under control signal control, the secondary encryption data producer is according to current count value jWith the data set in the internal register B ₀, generate current secondary encryption data set A _j, and will A _jOutput to data input of selector MUX2;

C3) under control signal control, MUX2 is at first with data set A _jOutput to the AES encryption equipment, and to data set A _jCarry out cryptographic operation, work as data set A _jWhen getting into the above streamline in the second level and the second level of AES encryption equipment, MUX2 is with data set D _iOutput to the first order streamline of AES encryption equipment, the AES encryption equipment is simultaneously to data set A _jAnd data set D _iCarry out cryptographic operation;

C4) AES encryption equipment output data groups at first A _jEncrypted result Y _j, under control signal control, the AES encryption equipment is with data set Y _jOutput to data input of XOR device XOR2; Simultaneously, register is with data set B _iBe sent to another data input pin of XOR device XOR2, XOR device XOR2 is to data set B _iWith data set Y _jCarry out XOR, the XOR result C _jOutput to data-out port; AES encryption equipment output data groups subsequently D _iEncrypted result X _{i+ 1}

Described steps d is to accomplish identifying code TCTR cryptographic calculation operation, further may further comprise the steps:

D1) under control signal control, selector MUX4 exports the AES encryption equipment X _{n+ 1}Be sent in the register, X _{n+ 1}Be data set B ₀~ B _nThe CBC-MAC operation result, X _{n+ 1}By MThe identifying code of byte TAnd 16- MAny binary bits string of byte xForm, promptly T|| x

D2) under control signal control, the secondary encryption data producer is according to the data set in current count value 0 and the internal register B ₀, generate current secondary encryption data set A ₀, and will A ₀Output to data input of selector MUX2;

D3) under control signal control, selector MUX2 will A ₀Output to the data input pin of AES encryption equipment;

D4) under control signal control, the AES encryption equipment is right A ₀Encrypt, in ciphering process, key generator is according to initial key KeyProduce 10 groups of sub-keys, and output to the key input of AES encryption equipment, the AES encryption equipment uses sub-key right A ₀Encrypt encrypted result Y ₀Output to data input of XOR device XOR2;

D5) under control signal control, XOR device XOR2 is to data set X _{n+ 1}With data set Y ₀Carry out XOR, the XOR result U|| xOutput to data-out port, the XOR result U|| xBy MThe encrypted authentication sign indicating number of byte UAnd 16- MAny binary bits string of byte xForm.

7. control method according to claim 3 is characterized in that, circuit is under " CCM decrypted state ", and its control method specifically may further comprise the steps:

A. import initial key Key

B. import the aided verification data set B ₀~ B _t-1, tBe natural number;

C. input information encrypt data group B _t, C ₁~ C _m, U|| 0, mBe natural number;

D. identifying code TConfirm;

Described step b is to accomplish the aided verification data set B ₀Be input to the secondary encryption data producer, and accomplish the aided verification data set B ₀~ B _t-1The CBC-MAC arithmetic operation, two operations are carried out simultaneously, wherein:

B2) aided verification data set B ₀~ B _t-1The CBC-MAC arithmetic operation, further may further comprise the steps:

B2-1) under control signal control, selector MUX1 is with the data set on the data-in port B _iBe sent to the data input of XOR device XOR1, wherein i= 0..., t-1;

Described step c is a completion information encrypt data group C ₁~ C _m, U|| 0 CTR decrypt operation operation, and accomplish the aided verification data set B _t~ B _nThe CBC-MAC arithmetic operation, further may further comprise the steps:

C1) if the current count value of counter jLess than m, wherein j=0 ..., m; M=n-t, nBe natural number, under control signal control, count value adds 1, if the current count value of counter jEqual m, under control signal control, the count value zero clearing; Count value after counter will calculate jOutput to secondary encryption data producer data input pin;

C2) under control signal control, the secondary encryption data producer is according to count value jWith the data set in the internal register B ₀, generate current secondary encryption data set A _j, and will A _jOutput to another data input pin of selector MUX2;

C4) AES encryption equipment output data groups at first A _jEncrypted result Y _j, under control signal control, the AES encryption equipment is with data set Y _jOutput to data input of XOR device XOR2; Simultaneously, register is with data set C _j/ U|| 0 is sent to another data input pin of XOR device XOR2, and XOR device XOR2 is to data set C _j/ U|| 0 and data set Y _jCarry out XOR, the XOR result M _j, i.e. data set B _T+j/ T|| x, output to data-out port; AES encryption equipment output data groups subsequently D _iEncrypted result X _{i+ 1}

Described steps d is to accomplish identifying code TAffirmation operation, further may further comprise the steps:

D1) under control signal control, selector MUX4 is with the XOR result of XOR device XOR2 output T|| xOutput in the register XOR T|| xThe result by MThe identifying code of byte TAnd 16- MAny binary bits string of byte xForm;

D2) under control signal control, XOR device XOR2 reads in the data set of AES encryption equipment output respectively X _{n+ 1}, and the data set of register output T|| x, X _{n+ 1}Be data set B ₀~ B _nThe CBC-MAC operation result, X _{n+ 1}By the identifying code that regenerates T ', and any binary bits string xForm, promptly T '|| x, T 'Length does MByte, xLength is 16- MByte, XOR device XOR2 is to data set T|| xAnd data set T '|| xCarry out XOR, and with the XOR result EOutput to the authentication result output port.

8. control method according to claim 3 is characterized in that, circuit is under " HASH function status ", and its control method specifically may further comprise the steps:

A. under control signal control, selector MUX2 is with the data set on the data-in port I _kBe sent to the data input pin of AES encryption equipment, wherein k=1 ..., s-1, sBe natural number;

B. under control signal control, the AES encryption equipment is imported data set I _k, and the data set to importing I _kEncrypt, in ciphering process, key generator is according to initial key Hash _k-1Produce 10 groups of sub-keys, wherein, Hash ₀Be the initial value of key generator internal register, and Hash ₀=0 ¹²⁸, and output to the key input of AES encryption equipment, the AES encryption equipment according to sub-key to data set I _kEncrypt, encrypted result outputs to the data input of XOR device XOR2;

C. under control signal control, XOR device XOR2 is to the encrypted result and the data set of AES encryption equipment I _kCarry out XOR, the XOR result Hash _kOutput to the output of XOR device XOR2;

If d. k< s, under control signal control, selector MUX3 exports XOR device XOR2 Hash _kBe sent to the key generator data input pin, will Hash _kInitial key as next round MMO HASH functional operation;

9. according to the arbitrary described control method of claim 3 ~ 8; It is characterized in that described AES encryption equipment adopts pipelined circuit, pipeline series is more than the two-stage; Circuit is under " CCM encrypted state " or " CCM decrypted state "; The AES encryption equipment is handled two groups of data simultaneously, and when first group of data arrives second level and the above streamline in the second level, first order streamline is imported second group of data.