CN102664125B - Double high driving level-resistant magnetic latching relay driving circuit - Google Patents
Double high driving level-resistant magnetic latching relay driving circuit Download PDFInfo
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- CN102664125B CN102664125B CN201210153666.1A CN201210153666A CN102664125B CN 102664125 B CN102664125 B CN 102664125B CN 201210153666 A CN201210153666 A CN 201210153666A CN 102664125 B CN102664125 B CN 102664125B
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Abstract
The invention relates to a double high driving level-resistant magnetic latching relay driving circuit, wherein the driving circuit is a bridge type driving circuit, a base electrode of a first audion which corresponds to a first bridge arm is connected with a first driving end of the driving circuit, and a base electrode of a second audion which corresponds to a second bridge arm is connected with a second driving end of the driving circuit; and the driving circuit further comprises a clamping circuit preventing the base electrode of the first audion and the base electrode of the second audion from simultaneously appearing high level. According to the circuit, one control IO port (input/ output) (driving end) controls the other control IO port, the other control IO port is forcibly arranged at low level when the high level is applied to the control IO port with high priority level, so that the damage of the double high level to the driving circuit can be effectively avoided, and a magnetic latching relay is arranged at a known controllable status, so that the aims of effectively avoiding the damage to a protector of the driving circuit caused by the uncertainty of the level of the control IO port, and reliably arranging the magnetic latching relay at the controllable status can be achieved.
Description
Technical field
The present invention relates to a kind of drive circuit of magnetic latching relay of anti-two high drive levels.
Background technology
Generally the power supply of master cpu circuit and drive circuit of magnetic latching relay is provided by same power supply, when CPU just powers on, various functions starts initialization, its IO mouth level of controlling drive circuit of magnetic latching relay will be in nondeterministic statement, and now drive circuit of magnetic latching relay has also powered on, probably cause the switch triode damage drive circuit that misleads.
The Chinese patent document of ZL201020245700.4 discloses a kind of drive circuit of magnetic latching relay, as shown in Figure 1, RelayOn is high level, when RelayOff is low level, Q502, Q503 enters conducting state fast, Q501, Q504 enters cut-off state fast time, and electric current is through HVC-->Q502-->RYB--GreatT.Gre aT.GTRYA-->Q503-->GAD, relay power closure.When magnetic latching relay need to be disconnected by closure, making magnetic latching relay control signal RelayOn is low level, RelayOff is high level, Q501, Q504 enters conducting state fast, Q502, and Q503 enters cut-off state fast, electric current is through HVC-->Q501-->RYA--GreatT.Gre aT.GTRYB-->Q504-->GND, and relay power disconnects.
Foregoing circuit, if RelayOn, RelayOff(drive signal or claim control signal) be high level simultaneously, four triodes conductings simultaneously, directly flow through two triodes of the same side of large electric current, easily cause drive circuit damage.
Summary of the invention
The object of this invention is to provide a kind of can effectively prevent from powering on, resetting at CPU and crash time the nondeterministic statement of IO mouth level relay is caused to the drive circuit of damage, the damage of the misoperation during for the two high level of inhibitory control port to drive circuit.
For achieving the above object, the solution of the present invention is: a kind of drive circuit of magnetic latching relay of anti-two high drive levels, described drive circuit is bridge drive circuit, the base stage of the first triode that its first brachium pontis is corresponding connects the first drive end of described drive circuit, and the base stage of the second triode that the second brachium pontis is corresponding connects the second drive end of described drive circuit; Described drive circuit also comprises that one prevents that the clamp circuit of high level from appearring in the base stage of the first triode and the base stage of the second triode simultaneously; This clamp circuit comprises a clamping transistor (Q5), the base stage of this clamping transistor (Q5) connects the first drive end, between the second drive end and the second transistor base, string is provided with a current-limiting resistance (R7), clamping transistor (Q5) collector electrode connects the second drive end, the emitter grounding of clamping transistor (Q5) by this current-limiting resistance (R7).
Between described the second drive end and the second transistor base, string is provided with described current-limiting resistance and a forward diode (D5) successively.
The present invention is that the first drive end and the second drive end add priority; with one of them control IO(drive end) mouthful remove to control another one control IO mouth; when giving the control IO mouth high level of high priority, by force another one control IO mouth is set low to level; effectively prevent the damage to drive circuit at two high level; magnetic latching relay is placed in to known controllable state simultaneously; reach and effectively prevent that the uncertainty of controlling IO mouth level from causing and damaging protection instrument drive circuit, and reliably magnetic latching relay is placed in to the object of controllable state.
For example, establishing the first drive end is high priority, and the second drive end is low priority, and the first drive end connects the base stage of clamping transistor, and the second drive end connects the collector electrode of clamping transistor by current-limiting resistance (R7).When control signal RelayOn, RelayOff are high level, the base stage of the first triode is high level and conducting, by Q5, the base stage of the second triode is forced to draw as low level, make the second triode cut-off, thereby while avoiding two high level, misoperation appears in circuit.
Accompanying drawing explanation
Fig. 1 is existing drive circuit;
Fig. 2 is clamp circuit of the present invention;
Fig. 3 is the circuit theory diagrams of embodiment 2.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described in detail.
Embodiment 1
As the drive circuit of Fig. 1, between the triode Q503 of left side brachium pontis and the triode Q504 of right side brachium pontis, increase clamp circuit, as Fig. 2, just can be transform as the drive circuit of anti-two high drive levels.Clamp circuit comprises a clamping transistor Q5(NPN triode), the base stage of this clamping transistor Q5 connects RelayOn drive end, between RelayOff drive end and its corresponding triode Q504 base stage, string is provided with a current-limiting resistance R7, Q5 collector electrode connects RelayOff drive end, the emitter grounding of Q5 by current-limiting resistance R7.
Above-mentioned drive circuit, when two high drive levels occur, RelayOn, RelayOff are high level, and RelayOn is high, Q5 conducting, causing RC point is low level by clamp.RelayOff arrives ground by R7 and Q5, can not affect Q504, and Q504 cut-off guarantees not conducting simultaneously of Q503 and Q504, avoids drive circuit damage.As analyzed in summary of the invention, sort circuit connected mode, RelayOn is high priority, RelayOff low priority, high priority can clamp low priority, and low priority could be only high level when high priority is low level.Only RelayOn, RelayOff need be exchanged, can realize the exchange of priority.
Further, between R7 and Q504 base stage, increase a forward diode D5.D5 is used for raising the level that RC is ordered when driving signal RelayOff high level, when Q5 conducting, makes more reliably Q504 in off state.
Embodiment 2
As Fig. 3, the drive circuit of the present embodiment comprises switch triode Q1～Q5, current-limiting resistance R1～R7, pull down resistor R8～R10, wherein Q1～Q4 forms bridge drive circuit, and Q1, Q2 is positive-negative-positive triode, Q3, and Q4 is NPN type triode, current-limiting resistance R1～R7 flows through the size of its electric current by control, the max-flow overcurrent that restriction magnetic latching relay drives.Between the collector and emitter of switch triode Q1～Q4, one of reverse parallel connection is protected diode D1～D4 successively.+ 12V is the power supply that drives magnetic latching relay action, RA, RB are the pin that connects magnetic latching relay control end, RelayOn, RelayOff are the control signal input of master cpu, current-limiting resistance is used for limiting the size that flows through switch triode base current, pull down resistor prevents that switch triode is subject to noise impact and produces misoperation, makes switch triode action more reliable.Diode D5 and pull down resistor R9 force Q2, Q4 in off state reliably, and magnetic latching relay is forced to draw as closure state
Only be from the different of embodiment 1, the triode in two of the left and right brachium pontis in embodiment 1 is complementary conducting work (Q502, Q503 conducting, Q501, Q504 cut-off; Q502, Q503 cut-off, Q501, Q504 conducting), and two of left and right brachium pontis in embodiment 2 is symmetrical straight-through (Q1, Q3 conducting, Q2, Q4 cut-off; Q1, Q3 cut-off, Q2, Q4 conducting).
Specific works mode of the present invention is as follows:
Under operate condition not, when input control signal RelayOn, RelayOff are high level, Q1, Q3, Q5 are in conducting state, by Q5, RC point is forced to draw into low level and by D5 and pull down resistor R9, Q2, Q4 are forced in off state reliably, magnetic latching relay is forced to draw as closure state.
Under operate condition not, when input control signal RelayOn, RelayOff are low level, Q1～Q5 is all in off state, and magnetic latching relay does not have any action.
When magnetic latching relay needs closure; making control signal input RelayOn is high level; RelayOff is low level; Q1, Q3, Q5 enter conducting state; Q2, Q4 enter off state; electric current warp+12V->Q1->RA->R B->Q3->GND; magnetic latching relay energising is closed, and in this process, magnetic latching relay produces a negative voltage by protecting diode D1, D4 to bleed off.
When magnetic latching relay need to disconnect; making control signal input RelayOn is low level; RelayOff is high level; Q1, Q3, Q5 enter off state; Q2, Q4 enter conducting state; electric current warp+12V->Q2->RB->R A->Q4->GND; magnetic latching relay energising disconnects, and in this process, magnetic latching relay produces a negative voltage by protecting diode D2, D3 to bleed off.
Above embodiment is the unrestricted technical method of the present invention in order to explanation only, although the present invention is had been described in detail with reference to above-described embodiment, those of ordinary skill in the art is to be understood that: the present invention is modified or is equal to replacement, and do not depart from any modification or partial replacement of the spirit and scope of the present invention, all should be encompassed in the middle of claim scope of the present invention.
Claims (2)
1. the drive circuit of magnetic latching relay of anti-two high drive levels, described drive circuit is bridge drive circuit, the base stage of the first triode that its first brachium pontis is corresponding connects the first drive end of described drive circuit, and the base stage of the second triode that the second brachium pontis is corresponding connects the second drive end of described drive circuit; It is characterized in that, described drive circuit also comprises that one prevents that the clamp circuit of high level from appearring in the base stage of the first triode and the base stage of the second triode simultaneously; This clamp circuit comprises a clamping transistor (Q5), the base stage of this clamping transistor (Q5) connects the first drive end, between the second drive end and the second transistor base, string is provided with a current-limiting resistance (R7), clamping transistor (Q5) collector electrode connects the second drive end, the emitter grounding of clamping transistor (Q5) by this current-limiting resistance (R7).
2. the drive circuit of magnetic latching relay of a kind of anti-two high drive levels according to claim 1, is characterized in that, between described the second drive end and the second transistor base, string is provided with described current-limiting resistance and a forward diode (D5) successively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210153666.1A CN102664125B (en) | 2012-05-17 | 2012-05-17 | Double high driving level-resistant magnetic latching relay driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210153666.1A CN102664125B (en) | 2012-05-17 | 2012-05-17 | Double high driving level-resistant magnetic latching relay driving circuit |
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| CN102664125A CN102664125A (en) | 2012-09-12 |
| CN102664125B true CN102664125B (en) | 2014-04-30 |
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| CN109412570A (en) * | 2018-11-26 | 2019-03-01 | 深圳和而泰智能控制股份有限公司 | A kind of switch driving circuit, controller and electronic equipment |
| CN110488680A (en) * | 2019-07-25 | 2019-11-22 | 宁波三星医疗电气股份有限公司 | A kind of control circuit with clamp function |
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| JPH01129133A (en) * | 1987-11-16 | 1989-05-22 | Hitachi Ltd | Self-diagnosis of control apparatus of engine |
| CN1233085C (en) * | 2002-08-30 | 2005-12-21 | 艾默生网络能源有限公司 | Inserting position driving circuit |
| CN201345539Y (en) * | 2009-01-22 | 2009-11-11 | 合肥工业大学 | Serial connection IGBT pressure-equalizing protection and control circuit |
| CN101860288B (en) * | 2010-05-20 | 2011-11-30 | 郑贵林 | Intelligent controller for three-phase motor |
| CN201698967U (en) * | 2010-07-02 | 2011-01-05 | 威胜集团有限公司 | Driving circuit of improved magnetic latching relay of electric energy meter |
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Owner name: XUJI GROUP CO., LTD. HENAN XUJI METER CO., LTD. ST Free format text: FORMER OWNER: HENAN XUJI METER CO., LTD. Effective date: 20141223 Owner name: STATE GRID CORPORATION OF CHINA Free format text: FORMER OWNER: XUJI GROUP CO., LTD. Effective date: 20141223 |
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Effective date of registration: 20141223 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: Xuji Group Co., Ltd. Patentee after: Henan Xuji Instrument Co., Ltd. Patentee after: State Grid Tianjin Electric Power Company Address before: No. 1298 Xuchang City, Henan province 461000 XJ Avenue Patentee before: Xuji Group Co., Ltd. Patentee before: Henan Xuji Instrument Co., Ltd. |