CN102662726B - The analogy method of virtual machine and computer equipment - Google Patents
The analogy method of virtual machine and computer equipment Download PDFInfo
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Abstract
The present invention relates to analogy method bypass conversion buffered in a kind of virtual machine and device.Wherein, the tlb entry in target CPU is filled up in the TLB of local cpu by virtual machine, and when target CPU will perform an access instruction, this access instruction is translated as the executable access instruction of local cpu by virtual machine; When virtual machine performs the access instruction after translation, the virtual address translation that access instruction is carried by the TLB of local cpu is physical address, for the access instruction access after translation, completes the accessing operation of the access instruction that target CPU will perform thus.The method that the present invention uses hardware and software to combine achieves the simulation of TLB in isomery virtual machine, improves the simulation precision of TLB.
Description
Technical field
The present invention relates to Computer Systems Organization, virtual machine technique field, particularly relate to a kind of analogy method and computer equipment of virtual machine.
Background technology
Bypass conversion buffered (Translation Look-aside Buffer, TLB) simulation has critical impact to the performance of virtual machine, and in all instructions that CPU performs, the instruction more than 50% is access instruction.General CPU all supports virtual store mechanism now, and the logical address namely contained in instruction is converted to physical address through page table.TLB is the hardware supported parts for accelerating page table conversion, has higher execution frequency.
In current virtual machine, the main method of pure software that adopts realizes TLB simulation.In dummy machine system of increasing income (such as Bochs, QEMU etc.), all with the execution mechanism of TLB in Software-only method simulation dummy machine system, comprising: traversal tlb entry; Judge whether list item mates the virtual address of input; If hit, returns the physical address comprised in list item; If do not hit, execute exception process.The analogy method of pure software has good portability, but is the introduction of higher simulation cost: the access instruction performed for target CPU, for simulating general at least tens of the dummy instruction of TLB lookup algorithm.In the occasion had higher requirements to virtual machine performance, TLB simulates the easy form performance bottleneck of link.
In order to overcome the shortcoming of Software-only method, some virtual machine adopts hardware simulation mode, with local physics TLB simulated target TLB, this analogy method is mainly used in the virtual machine (such as Vmware, VirtualBox, KVM etc.) of same architecture, the page table snapshot of application program in goal systems is preserved, with the access instruction of the direct performance objective CPU of local cpu in the TLB of i.e. local cpu.
Hardware simulation mode has outstanding odds for effectiveness than Software-only method, but limits portability, could can only use in the virtual machine of same architecture.For isomery virtual machine, due to cannot on local cpu the access instruction of direct performance objective architecture, therefore also directly cannot utilize the TLB simulated target TLB of local cpu.
Summary of the invention
The object of the invention is the defect for prior art, a kind of analogy method and computer equipment of virtual machine are provided, achieve the simulation utilizing software and hardware jointly to complete TLB in virtual machine, this analogy method can be applicable to isomery virtual machine simultaneously, and TLB simulation precision is high.
In order to achieve the above object, the invention provides a kind of analogy method of virtual machine, said method comprising the steps of: virtual machine takes out the first access instruction that target CPU will perform; Obtain the second access instruction that described first access instruction is corresponding, the executable instruction of local cpu that described second access instruction obtains for the first access instruction described in virtual machine translation; When virtual machine performs described second access instruction, the list item in the virtual address that described second access instruction is carried by the bypass conversion buffered TLB of local cpu and TLB carries out matching check, judges whether to there is list item corresponding to described virtual address; When there is list item corresponding to described virtual address in the TLB of local cpu, described virtual address translation is physical address by the TLB of local cpu, in order to make local cpu using the actual access address of described physical address as described second access instruction, described second access instruction of normal execution.
Preferably, described judge whether to there is list item corresponding to described virtual address after also comprise: when there is not list item corresponding to described virtual address in the TLB of local cpu, it is abnormal that local cpu produces TLB miss, and proceed to the exception handler entrance performing native operating sys-tern registration, carry out simulation process by native operating sys-tern for described TLB miss is abnormal
Preferably, list item in described virtual address and TLB is carried out matching check by the TLB of described local cpu, also comprises: virtual machine is by being filled up in the TLB of local cpu by the tlb entry of simulating in target CPU before judging whether to there is list item corresponding to described virtual address.
Preferably, the second access instruction that described virtual machine obtains described first access instruction corresponding is specially: virtual machine preserves queue according to instruction after translation, judge whether described first access instruction has been translated into the second access instruction of local cpu, if so, then preserve queue from instruction after described translation and obtain described second access instruction; Otherwise described first access instruction is translated as described second access instruction, and described second access instruction is preserved queue stored in instruction after described translation.
Preferably, described target CPU and described local cpu are different architectures; TLB in described target CPU is identical with the size of the page unit that the TLB in described local cpu supports.
Preferably, described second access instruction is specially an access instruction, or an access instruction sequence.
Preferably, describedly carried out simulation process by native operating sys-tern be specially for described TLB miss is abnormal: native operating sys-tern identifies abnormal Producing reason in exception handler, judge described exception be come the TLB miss of self virtualizing machine abnormal after, the hardware processing method producing TLB miss exception in simulated target CPU processes.
Correspondingly, in order to achieve the above object, the embodiment of the present invention additionally provides a kind of computer equipment, and described computer equipment comprises: virtual machine, and described virtual machine comprises: Fetch unit, for taking out the first access instruction that target CPU will perform; Instruction fetch unit, for obtaining the second access instruction corresponding to described first access instruction, the executable instruction of local cpu that described second access instruction obtains for the first access instruction described in virtual machine translation;
Described computer equipment also comprises local cpu, and described local cpu comprises: bypass conversion buffered TLB, carries out matching check, judge whether to there is list item corresponding to described virtual address for the list item in the virtual address of described second access instruction being carried and TLB; When there is list item corresponding to described virtual address in the TLB of local cpu, described virtual address translation is physical address by TLB, in order to make local cpu using the actual access address of described physical address as described second access instruction, described second access instruction of normal execution.
Preferably, the virtual machine in the embodiment of the present invention also comprises: TLB operating unit, for by being filled up in the TLB of local cpu by the bypass conversion buffered tlb entry of simulating in target CPU.
Preferably, described instruction fetch unit specifically for: according to translation after instruction preserve queue, judge whether described first access instruction has been translated into the second access instruction of local cpu, if so, then preserve queue from instruction after described translation and obtain described second access instruction; Otherwise described first access instruction is translated as described second access instruction, and described second access instruction is preserved queue stored in instruction after described translation.
Preferably, described target CPU and described local cpu are different architectures; TLB in described target CPU is identical with the size of the page unit that the TLB in described local cpu supports.
In the above embodiment of the present invention, the tlb entry in target CPU is filled up in the TLB of local cpu by virtual machine, and when target CPU will perform an access instruction, this access instruction is translated as the executable access instruction of local cpu by virtual machine; When virtual machine performs the access instruction after translation, the virtual address translation that access instruction is carried by the TLB of local cpu is physical address, for the access instruction access after translation, completes the accessing operation of the access instruction that target CPU will perform thus; If do not comprise the list item that virtual address that access instruction carries is corresponding in the TLB of local cpu, it is abnormal that local cpu produces TLB miss, and proceed to the exception handler entrance performing the registration of local operation system, by this exception of hardware processing method process producing TLB miss exception in native operating sys-tern simulated target CPU.Thus, the method that the present invention uses hardware and software to combine achieves the simulation of TLB in isomery virtual machine, improves the simulation precision of TLB in virtual machine.
Accompanying drawing explanation
The analogy method process flow diagram of a kind of virtual machine that Fig. 1 provides for the embodiment of the present invention;
The analogy method process flow diagram of the another virtual machine that Fig. 2 provides for the embodiment of the present invention;
A kind of computer equipment schematic diagram that Fig. 3 provides for the embodiment of the present invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.First the vocabulary of terms used in present specification is made an explanation:
1, local platform refers to the operation platform at software virtual machine place, is real physical platform;
2, target platform refers to the platform that software virtual machine is simulated at run duration, the platform that the target software namely run in virtual machine relies on.
3, the local cpu CPU that to be the CPU in local platform, target CPU be in target platform.
4, when the local platform of virtual machine is identical with target platform, be called isomorphism virtual machine, otherwise be called isomery virtual machine.
5, TLB hit refers in TLB and comprises list item corresponding to the virtual address imported into, can convert physical address to.TLB does not hit and refers in TLB and do not comprise list item corresponding to the virtual address imported into.
6, destination OS refers to the operating system run in virtual machine, and native operating sys-tern is the operating system run on local physical host.
The analogy method process flow diagram of a kind of virtual machine that Fig. 1 provides for the embodiment of the present invention.The present embodiment describes the process utilizing software and hardware jointly to complete the simulation of TLB in virtual machine in detail.As shown in Figure 1, the present embodiment comprises the following steps:
Step 101, virtual machine takes out the first access instruction that target CPU will perform.
Virtual machine is in the process of performance objective program, and the continuous in a looping fashion instruction of taking out next and will perform from target memory, if this instruction is access instruction, then uses the method that provides of the embodiment of the present invention to simulate the implementation of this access instruction; Otherwise the execution of instruction is unrelated to the invention.
It should be noted that, the method that the embodiment of the present invention provides is applicable to isomery virtual machine, and namely local cpu is not identical with the architecture of target CPU.
In addition, in the embodiment of the present invention, local cpu and target CPU all support virtual storage system, and local cpu and target CPU all comprise the hardware TLB for virtual address and physical address translations; TLB in local cpu and the TLB in target CPU will support the page unit of formed objects, and this condition usually can be met in existing main platform, and therefore the feasibility of method that provides of the embodiment of the present invention is better; Local cpu provides the operational order for TLB, i.e. the read write command of tlb entry, so that virtual machine can use these instructions to read and write local TLB.
Step 102, virtual machine obtains the second access instruction corresponding to described first access instruction, and described second access instruction is the first access instruction described in virtual machine translation and the executable instruction of local cpu that obtains.
The concrete grammar that virtual machine obtains the second access instruction corresponding to described first access instruction is: virtual machine preserves queue according to instruction after translation, judge whether the first access instruction has been translated into the second access instruction of local cpu, if so, then preserve queue from instruction after described translation and obtain described second access instruction; Otherwise the first access instruction is translated as executable second access instruction of local cpu.
Virtual machine is when simulating the first access instruction performing and take out, and instruction is preserved in queue and retrieved first upon translation, checks the second access instruction whether this instruction has been translated into local cpu and can performs.After translation, queue is preserved in instruction is for preserving a queue of all translation post code in virtual machine, if the instruction that will perform is translated, then the second access instruction that the local cpu after translation can perform directly is taken out and performs by virtual machine.If the second access instruction of the local cpu execution that the first access instruction not having target CPU to perform in instruction preservation queue after translation is corresponding, then virtual machine translation first access instruction, and instruction is preserved in queue after the code after translation is kept at this translation, so that when virtual machine performs the first access instruction next time again, again need not translate, directly take out from this queue and perform the second access instruction after translating.
The method that the second access instruction that the first access instruction in target CPU translates into local cpu uses is by virtual machine: before adopting binary command translation rule to ensure translation, after translation, instruction is at equivalence semantically.Comprise the access action for local internal memory in instruction sequence after translation, the virtual address comprised in instruction is identical with before translation.
It should be noted that, the second access instruction in the present embodiment can be a single instruction, also can be an instruction sequence, i.e. multiple instruction, and this is determined by the architecture of target CPU and local cpu.
Step 103, when virtual machine performs described second access instruction, the list item in the virtual address that described second access instruction is carried by the bypass conversion buffered TLB of local cpu and TLB carries out matching check, judges whether to there is list item corresponding to described virtual address.
During second access instruction of virtual machine after getting translation, this instruction sequence is dropped into local cpu run, the virtual address that target CPU will access is carried in second access instruction, the TLB of local cpu inside checks in hardware in this TLB and comprises list item corresponding to this virtual address, namely inquire about this virtual address and whether can be converted to physical address, namely use the exception handling of TLB itself to judge whether can be physical address by this virtual address translation.Wherein, the virtual address that above-mentioned virtual address will be accessed by dummy instruction, physical address is local physical memory addresses, corresponding to the region of target memory.
Tlb entry in target CPU is filled up in the TLB of local cpu, achieve the inquiry and address flow path switch that use pure hardware approach simulated target TLB, access instruction after translation will be only had in translation post code in step 102, the judgement code need not generate the retrieval of TLB, whether hitting, thus making translation cost be reduced to minimum radius, execution speed is far away higher than the scale of tens instructions of use Software-only method.
Step 104, when there is list item corresponding to described virtual address in the TLB of local cpu, described virtual address translation is physical address by the TLB of local cpu, in order to make local cpu using the actual access address of described physical address as described second access instruction, described second access instruction of normal execution.
Virtual machine by local cpu according to the virtual address in the second access instruction, obtains the physical address that virtual address is corresponding after the second access instruction is dropped into local cpu operation in TLB.As long as local cpu is configured to the pattern of enabling page table conversion by native operating sys-tern, first local cpu carries out " virtual address-physical address " conversion through TLB when performing instruction, the virtual address that TLB will change and all list items that self preserves carry out matching check, if there is the list item of same virtual address, then return corresponding physical address, in the memory access flow process that local cpu continues after execution.
The physical location that physical address after changing is memory access by local cpu, according to the access action of the local internal memory of the semantic execution of instruction, normally to complete the execution of the second access instruction.
Because TLB generally has higher hit rate, therefore TLB hit, the normally complete situation of second access instruction accounts for the important proportion of TLB simulation, again due to can not exception be produced when TLB hits, therefore also without the need to execute exception processing section in kernel, virtual machine is made to create fairly large performance boost on the whole.
In the embodiment of the present invention, when target CPU will perform an access instruction, first virtual machine obtains executable for local cpu corresponding for this access instruction access instruction; When virtual machine performs the access instruction after translation, the virtual address translation that access instruction is carried by the TLB of local cpu is physical address, for the access instruction access after translation, completes the accessing operation of the access instruction that target CPU will perform thus.Thus, the method that the present invention uses hardware and software to combine achieves the simulation of TLB in isomery virtual machine, improves the simulation precision of TLB in virtual machine
The analogy method process flow diagram of the another virtual machine that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2, the present embodiment comprises the following steps:
Step 201, virtual machine takes out the first access instruction that target CPU will perform.
Virtual machine is in the process of performance objective program, and the continuous in a looping fashion instruction of taking out next and will perform from target memory, if this instruction is access instruction, then uses the method that provides of the embodiment of the present invention to simulate the implementation of this access instruction; Otherwise the execution of instruction is unrelated to the invention.
Step 202, virtual machine preserves queue according to instruction after translation, judges whether the first access instruction has been translated into the second access instruction of local cpu, if so, then preserves queue from instruction after described translation and obtains described second access instruction; Otherwise the first access instruction is translated as executable second access instruction of local cpu.
Virtual machine is when simulating the first access instruction performing and take out, and instruction is preserved in queue and retrieved first upon translation, checks the second access instruction whether this instruction has been translated into local cpu and can performs.After translation, queue is preserved in instruction is for preserving a queue of all translation post code in virtual machine, if the instruction that will perform is translated, then the second access instruction that the local cpu after translation can perform directly is taken out and performs by virtual machine.If the second access instruction of the local cpu execution that the first access instruction not having target CPU to perform in instruction preservation queue after translation is corresponding, then virtual machine translation first access instruction, and instruction is preserved in queue after the code after translation is kept at this translation, so that when virtual machine performs the first access instruction next time again, again need not translate, directly take out from this queue and perform the second access instruction after translating.
Step 203, when virtual machine performs described second access instruction, the virtual address of being carried according to described second access instruction by local cpu, list item in described virtual address and TLB is carried out matching check by the bypass conversion buffered TLB of local cpu, judges whether to there is list item corresponding to described virtual address.
During second access instruction of virtual machine after getting translation, this instruction sequence is dropped into local cpu run, the virtual address that target CPU will access is carried in second access instruction, the TLB of local cpu inside checks in hardware in this TLB and comprises list item corresponding to this virtual address, namely inquire about this virtual address and whether can be converted to physical address, namely use the exception handling of TLB itself to judge whether can be physical address by this virtual address translation.Wherein, the virtual address that above-mentioned virtual address will be accessed by dummy instruction, physical address is local physical memory addresses, corresponding to the region of target memory.
According to the virtual address that described second access instruction is carried, before whether there is list item corresponding to described virtual address in the TLB of inquiry local cpu, the present embodiment also comprises: step 206, by being filled up in the TLB of local cpu by the tlb entry of simulating in target CPU.
The opportunity that virtual machine performs the operation of step 206 is identical with the opportunity performing this hardware action in target CPU.
Preferably, when destination OS dispatches new process, virtual machine can by being filled up in the TLB of local cpu by the tlb entry of simulating in target CPU.
Preferably, when target CPU performs page table update action, the tlb entry after renewal in target CPU can be replaced corresponding tlb entry in local cpu by virtual machine.
Preferably, when TLB miss exception occurs target CPU, virtual machine can perform list item and replace action, uses the tlb entry in the page table content replacement local cpu in target memory.
Preferably, virtual machine can also use local cpu to provide operational order for TLB, the tlb entry in display update local cpu.
Tlb entry in target CPU is filled up in the TLB of local cpu, achieve the inquiry and address flow path switch that use pure hardware approach simulated target TLB, access instruction after translation will be only had in translation post code in step 202, the judgement code need not generate the retrieval of TLB, whether hitting, thus making translation cost be reduced to minimum radius, execution speed is far away higher than the scale of tens instructions of use Software-only method.
Step 204, when there is list item corresponding to described virtual address in the TLB of local cpu, described virtual address translation is physical address by the TLB of local cpu, normally performs described second access instruction in order to make local cpu.
Virtual machine by local cpu according to the virtual address in the second access instruction, obtains the physical address that virtual address is corresponding after the second access instruction is dropped into local cpu operation in TLB.As long as local cpu is configured to the pattern of enabling page table conversion by native operating sys-tern, first local cpu carries out " virtual address-physical address " conversion through TLB when performing instruction, the virtual address that TLB will change and all list items that self preserves carry out matching check, if there is the list item of same virtual address, then return corresponding physical address, in the memory access flow process that local cpu continues after execution.
Step 205, when there is not list item corresponding to described virtual address in the TLB of local cpu, it is abnormal that local cpu produces TLB miss, and proceed to the exception handler entrance performing the registration of local operation system, carries out simulation process by native operating sys-tern for described TLB miss is abnormal.
If there is not list item corresponding to described virtual address in the TLB of local cpu, it is abnormal that local cpu produces TLB miss, processes this exception by the abnormality processing functional module in native operating sys-tern.
Extremely carry out simulation process by native operating sys-tern for described TLB miss to be specially: native operating sys-tern identifies abnormal Producing reason in exception handler, judge described exception be come the TLB miss of self virtualizing machine abnormal after, the hardware processing method producing TLB miss exception in simulated target CPU processes.
It should be noted that, in different architectures, TLB miss exception handling procedure is different.In the TLB of hardware management (taking X86 as representative), when there is miss and being abnormal in TLB, first in physical memory, page table lookup action is performed by CPU, if find effective physical address in page table, then fill out in TLB counter for current lookup result, thus can directly be changed in TLB when next time accesses same virtual address.In the TLB of software administration (taking MIPS as representative), when there is miss and being abnormal in TLB, CPU itself is only abnormal to operating system report, what complete page table in physical memory by operating system searches action, if find effective physical address in page table, then call specific TLB read write command by operating system, explicit fills out in TLB counter for current lookup result.No matter be in any type, virtual machine is all the behavior that simulation matches with target hardware, on the opportunity that the TLB of target CPU is modified, performs the corresponding modify of local TLB.
In the embodiment of the present invention, the tlb entry in target CPU is filled up in the TLB of local cpu by virtual machine, and when target CPU will perform an access instruction, this access instruction is translated as the executable access instruction of local cpu by virtual machine; When virtual machine performs the access instruction after translation, the virtual address translation that access instruction is carried by the TLB of local cpu is physical address, for the access instruction access after translation, completes the accessing operation of the access instruction that target CPU will perform thus; If do not comprise the list item that virtual address that access instruction carries is corresponding in the TLB of local cpu, it is abnormal that local cpu produces TLB miss, and proceed to the exception handler entrance performing the registration of local operation system, by this exception of hardware processing method process producing TLB miss exception in native operating sys-tern simulated target CPU.Thus, the method that the present invention uses hardware and software to combine achieves the simulation of TLB in isomery virtual machine, improves the simulation precision of TLB in virtual machine.
Below for the access instruction that a target CPU will perform, the method for TLB simulation in isomery virtual machine is described.
The CPU supposing in main frame is the CPU of MIPS structure, the CPU of virtual machine is the CPU of X86, the 4K page is used in X86CPU, then the page size that 4K, 16K etc. are different generally can be supported in MIPS CPU, even at the page table of CPU run duration different page unit used in combination, the precondition using this method can be met.4 TLB operational order: TLBP (query entries), TLBR (reading entry), TLBWI (writing entry), TLBWR (random write entry) are provided in MIPS instruction set.This four instructions is all privileged instruction, must perform under franchise state, provides whole necessary means of the local TLB of operation.
Suppose that virtual machine uses continuous print local physical memory simulation X86 physical memory, its start physical address is 0x40000000.In X86CPU, in the page table of certain application program, there is mapping below:
[virtual address 0x80000000, physical address 0x50000]
And this mapping exists in the TLB of local cpu, and its content is:
[virtual address 0x80000000, physical address 0x40050000]
If application program performs access instruction below:
MOV EAX，[0x80000002]
MIPS instruction below virtual machine translation becomes:
lui t0，0x8000
ori t0 0x0002
1w s0，0(t 0)
Wherein, register t0 saves the virtual address that original X86 instruction will be accessed; S0 is used for simulated target eax register, for preserving the data read from internal memory.
Local MIPS, when performing the last item 1w instruction, inquires about TLB with the page base address of virtual address (0x80000000), matches with list item in TLB, thus taking-up physics page base address is 0x40050000.This physical address adds the page bias internal amount (0x2) of former virtual address, and the local physical address obtaining final access is 0x40050002.The X86 target physical address of this address virtual machine simulation just, thus the semanteme of the MOV instruction that simulation is performed correctly is simulated.
Described by above-mentioned concrete example, the feasibility describing the TLB analogy method that the embodiment of the present invention provides is good, and efficiency is high.
Correspondingly, present invention also offers analogue means bypass conversion buffered in a kind of virtual machine.A kind of computer equipment schematic diagram that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, the present embodiment comprises with lower unit:
Virtual machine 301, virtual machine 301 comprises: Fetch unit 303, for taking out the first access instruction that target CPU will perform; Instruction fetch unit 304, for obtaining the second access instruction corresponding to described first access instruction, the executable instruction of local cpu that described second access instruction obtains for the first access instruction described in virtual machine translation.
It should be noted that, the virtual machine that the embodiment of the present invention provides can be both isomorphism virtual machine, and also can be isomery virtual machine, namely local cpu and target CPU can be identical architectures, also can be different architectures.For isomorphism virtual machine, virtual machine can directly utilize the TLB of local cpu simulated target CPU to perform flow process, and therefore, the embodiment of the present invention will only be described in detail for the simulation of TLB in isomery virtual machine.
In addition, in the embodiment of the present invention, local cpu and target CPU all support virtual storage system, and local cpu and target CPU all comprise the hardware TLB for virtual address and physical address translations; TLB in local cpu and the TLB in target CPU will support the page unit of formed objects, and this condition usually can be met in existing main platform, and the device that therefore embodiment of the present invention provides has applicability widely; Local cpu provides the operational order for TLB, i.e. the read write command of tlb entry, so that virtual machine can use these instructions to read and write local TLB.
Instruction fetch unit 304 specifically for: according to translation after instruction preserve queue, judge whether described first access instruction has been translated into the second access instruction of local cpu, if so, then preserve queue from instruction after described translation and obtain described second access instruction; Otherwise described first access instruction is translated as described second access instruction, and described second access instruction is preserved queue stored in instruction after described translation.
Virtual machine is when simulating the first access instruction performing and take out, and instruction fetch unit 304 first upon translation instruction is preserved in queue and retrieved, and checks the second access instruction whether this instruction has been translated into local cpu and can performs.After translation, queue is preserved in instruction is for preserving a queue of all translation post code in virtual machine, if the instruction that will perform is translated, then the second access instruction that the local cpu after translation can perform directly is taken out and performs by virtual machine.If the second access instruction of the local cpu execution that the first access instruction not having target CPU to perform in instruction preservation queue after translation is corresponding, then virtual machine translation first access instruction, and instruction is preserved in queue after the code after translation is kept at this translation, so that when virtual machine performs the first access instruction next time again, again need not translate, directly take out from this queue and perform the second access instruction after translating.
The method that the second access instruction that the first access instruction in target CPU translates into local cpu uses is by virtual machine: before adopting binary command translation rule to ensure translation, after translation, instruction is at equivalence semantically.Comprise the access action for local internal memory in instruction sequence after translation, the virtual address comprised in instruction is identical with before translation.
It should be noted that, the second access instruction in the present embodiment can be a single instruction, also can be an instruction sequence, i.e. multiple instruction, and this is determined by the architecture of target CPU and local cpu.
Local cpu 302, local cpu 302 comprises: TLB305, carries out matching check, judge whether to there is list item corresponding to described virtual address for the list item in the virtual address of described second access instruction being carried and TLB305; When there is list item corresponding to described virtual address in the TLB305 of local cpu 302, described virtual address translation is physical address by TLB305, normally performs described second access instruction in order to make local cpu 302
Preferably, virtual machine 301 also comprises: TLB operating unit 306, for by being filled up in the TLB305 of local cpu 302 by the bypass conversion buffered tlb entry of simulating in target CPU.
Access instruction after translation is dropped into local cpu 302 and runs by virtual machine, access instruction is performed by local cpu 302 simulated target CPU, perform in the process of access instruction at local cpu, local TLB305 checks the list item in this TLB in hardware, to judge whether that the virtual address dress that access instruction can be carried is changed to physical address, if can, then normally perform access instruction, otherwise the method process TLB miss of simulated target hardware is abnormal.
Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. an analogy method for virtual machine, is characterized in that, described method comprises:
Virtual machine takes out the first access instruction that target CPU will perform;
Virtual machine obtains the second access instruction corresponding to described first access instruction, and described second access instruction is the first access instruction described in virtual machine translation and the executable instruction of local cpu that obtains;
When virtual machine performs described second access instruction, the list item in the virtual address that described second access instruction is carried by the bypass conversion buffered TLB of local cpu and TLB carries out matching check, judges whether to there is list item corresponding to described virtual address;
When there is list item corresponding to described virtual address in the TLB of local cpu, described virtual address translation is physical address by the TLB of local cpu, in order to make local cpu using the actual access address of described physical address as described second access instruction, described second access instruction of normal execution;
List item in described virtual address and TLB is carried out matching check by the TLB of described local cpu, also comprises before judging whether to there is list item corresponding to described virtual address: virtual machine will be filled up in the TLB of local cpu by the tlb entry of simulating in target CPU;
Described judge whether to there is list item corresponding to described virtual address after also comprise: when there is not list item corresponding to described virtual address in the TLB of local cpu, it is abnormal that local cpu produces TLB failure TLB miss, and proceed to the exception handler entrance performing native operating sys-tern registration, carry out simulation process by native operating sys-tern for described TLB miss is abnormal;
Describedly carried out simulation process by native operating sys-tern be specially for described TLB miss is abnormal: native operating sys-tern identifies abnormal Producing reason in exception handler, judge described exception be come the TLB miss of self virtualizing machine abnormal after, the hardware processing method producing TLB miss exception in simulated target CPU processes.
2. the analogy method of virtual machine as claimed in claim 1, it is characterized in that, the second access instruction that described virtual machine obtains described first access instruction corresponding is specially: virtual machine preserves queue according to instruction after translation, judge whether described first access instruction has been translated into the second access instruction of local cpu, if so, then preserve queue from instruction after described translation and obtain described second access instruction; Otherwise described first access instruction is translated as described second access instruction, and described second access instruction is preserved queue stored in instruction after described translation.
3. the analogy method of virtual machine as claimed in claim 1, it is characterized in that, described target CPU and described local cpu are different architectures; TLB in described target CPU is identical with the size of the page unit that the TLB in described local cpu supports.
4. the analogy method of virtual machine as claimed in claim 1, it is characterized in that, described second access instruction is specially an access instruction, or an access instruction sequence.
5. a computer equipment, is characterized in that, described computer equipment comprises:
Virtual machine, described virtual machine comprises: Fetch unit, for taking out the first access instruction that target CPU will perform; Instruction fetch unit, for obtaining the second access instruction corresponding to described first access instruction, the executable instruction of local cpu that described second access instruction obtains for the first access instruction described in virtual machine translation;
Local cpu, described local cpu comprises: bypass conversion buffered TLB, carries out matching check, judge whether to there is list item corresponding to described virtual address for the list item in the virtual address of described second access instruction being carried and TLB; When there is list item corresponding to described virtual address in the TLB of local cpu, described virtual address translation is physical address by TLB, in order to make local cpu using the actual access address of described physical address as described second access instruction, described second access instruction of normal execution; When there is not list item corresponding to described virtual address in the TLB of local cpu, it is abnormal that local cpu produces TLB failure TLB miss, and proceed to the exception handler entrance performing native operating sys-tern registration, carry out simulation process by native operating sys-tern for described TLB miss is abnormal; Describedly carried out simulation process by native operating sys-tern be specially for described TLB miss is abnormal: native operating sys-tern identifies abnormal Producing reason in exception handler, judge described exception be come the TLB miss of self virtualizing machine abnormal after, the hardware processing method producing TLB miss exception in simulated target CPU processes;
Described virtual machine also comprises: TLB operating unit, for by being filled up in the TLB of local cpu by the bypass conversion buffered tlb entry of simulating in target CPU.
6. computer equipment as claimed in claim 5, it is characterized in that, described instruction fetch unit specifically for: according to translation after instruction preserve queue, judge whether described first access instruction has been translated into the second access instruction of local cpu, if so, then preserve queue from instruction after described translation and obtain described second access instruction; Otherwise described first access instruction is translated as described second access instruction, and described second access instruction is preserved queue stored in instruction after described translation.
7. computer equipment as claimed in claim 5, it is characterized in that, described target CPU and described local cpu are different architectures; TLB in described target CPU is identical with the size of the page unit that the TLB in described local cpu supports.
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| CN103455363B (en) * | 2013-08-30 | 2017-04-19 | 华为技术有限公司 | Command processing method, device and physical host of virtual machine |
| CN106371890B (en) * | 2016-08-29 | 2019-05-28 | 山东乾云启创信息科技股份有限公司 | A kind of analogy method of GPU |
| CN111061655B (en) * | 2017-12-28 | 2022-06-17 | 贵阳忆芯科技有限公司 | Address translation method and device for storage device |
| CN110209603B (en) * | 2019-05-31 | 2021-08-31 | 龙芯中科技术股份有限公司 | Address translation method, device, equipment and computer readable storage medium |
| CN114546897A (en) * | 2020-11-26 | 2022-05-27 | 龙芯中科技术股份有限公司 | Memory access method and device, electronic equipment and storage medium |
| CN114840445A (en) * | 2022-03-02 | 2022-08-02 | 阿里巴巴（中国）有限公司 | Memory access method and device |
| CN114996176A (en) * | 2022-07-29 | 2022-09-02 | 飞腾信息技术有限公司 | Memory access method, computing device and storage medium |
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