CN102662605B - Storage device, storage system and storage method based on solid-state storage medium - Google Patents
Storage device, storage system and storage method based on solid-state storage medium Download PDFInfo
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- CN102662605B CN102662605B CN201210058178.2A CN201210058178A CN102662605B CN 102662605 B CN102662605 B CN 102662605B CN 201210058178 A CN201210058178 A CN 201210058178A CN 102662605 B CN102662605 B CN 102662605B
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Abstract
The invention discloses a storage device, a storage system and a storage method based on a solid-state storage medium, wherein the storage device comprises multiple flash memory chips and a plurality of the flash memory chips are connected in series to form a chip array (string). Each string is connected to a string controller, wherein the string controller comprises a processor unit, a controller unit, an interface unit, and a buffer unit. The interface unit is connected to a host port interface, wherein the interface unit has different types, including a SATA interface, a SAS interface, and a PCIe interface which are used for connecting a host. The strings are connected to the host and configured as logical volumes which can be identified by a host file system, wherein the logical volume maps one string or a plurality of strings. The storage device, the storage system and the storage method provided by the invention have the advantages of configurability, manifesting as a plurality of independent storage devices for the host, capability of configuration as a RAID, and performance of the entire device improving.
Description
Technical field
The present invention relates to a kind of memory device based on solid storage medium, storage system and storage means.
Background technology
Along with the progressively raising of flash memory application technology, the requirement of user to equipment read-write speed is also more and more higher.The interface bandwidth of single or single pass flash memory device can not meet the demand of user far away.Therefore, the factory commercial city of nearly all flash memory device and flash controller is in the multichannel flash chip operator scheme of research and development.This its advantage of multichannel flash memory device is to carry out flash disk operation by hyperchannel simultaneously, can significantly improve interface bandwidth and the I/O ability of flash memory device.The multiple flash controller of this multichannel flash memory device configuration, but these multiple flash controllers share simultaneously one with the SATA of main frame or PCIe interface, therefore at main frame, this multichannel flash memory device still shows as the flash memory device of a single face.This limits the capacity of flash memory device and the further raising of bandwidth of handling up to a certain extent.
Application number be 201010184698.9 Chinese invention patent disclose a kind of multi-interface solid state disk (SSD) and disposal route thereof and system, this invention comprises multiple interface control unit, command scheduling unit, flash control module and flash chip, realizes the communication scheduling of multiple interface control unit to flash control module and flash chip by described command scheduling unit.But this system lacks the dirigibility to the configuration of flash chip.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of memory device based on solid storage medium, storage system and storage means, overcomes the not high defect of dirigibility of existing Large Copacity, the interface of two-forty solid state medium storage system and configuration management.
For solving the problems of the technologies described above, first the present invention provides a kind of memory device based on solid storage medium, comprise multiple flash chip, it is characterized in that, some described flash chips are composed in series a chip array string, each described chip array string connects chip array string controller respectively, and described chip array string controller comprises processor unit, controller unit, interface unit and buffer unit, and described interface unit connects host bus interface.
Flash chip in described chip array string is the storage medium of MLC or SLC type.The described chip array string that the flash chip of same MLC or SLC type forms is called MLC type chip array string or SLC type chip array string.
Described interface unit has dissimilar, comprises SATA, SAS and PCIe interface of connecting main frame.
Described chip array string is configured to the discernible logical volume of host file system, comprises one or more described chip array string in described logical volume,
Described chip array string in each described logical volume is single MLC type chip array string or SLC type chip array string.Each described logical volume shares same host bus interface.
Multiple described chip array string connects according to RAID algorithm or in JBOD mode.
The present invention proposes the storage system of the memory device based on solid storage medium described in a kind of basis simultaneously, it is characterized in that, described chip array string is connected with main frame, be configured to the discernible logical volume of host file system, described logical volume maps one or more described chip array string
Described chip array string in each described logical volume is single MLC type chip array string or SLC type chip array string.
Each described logical volume shares same host bus interface.
Multiple described chip array string connects according to RAID algorithm or in JBOD mode.
The invention allows for the storage means of the storage system of the memory device based on solid storage medium described in a kind of basis, it is characterized in that, comprise the following steps:
Use the main process equipment drive software based on the memory device of chip array string that chip array string is configured multiple different logical volume according to demand, each logical volume comprises 1 or multiple chip array string;
Configuration information is issued chip array string controller by the device driver software of main frame, chip array string is configured, multiple flash chips that one single chip array string comprises are configured to an independently read-write equipment, or multiple chip array string is configured to a read-write equipment;
Described multiple read-write equipment is configured to RAID mode by main frame;
When read-write equipment operates, chip array string controller, according to the firmware of the configuration in ROM or upper strata instruction and device configuration information, is resolved instruction, and by control bus, controller unit is issued in instruction; Controller unit by instructions parse in the control module of the different chip array string of correspondence, described control module is hung on the control bus, accept the command operating of main frame for different chip array string, and be handed down to different chip array string, complete read-write operation.
Difference with general multi-passage flash memory apparatus is, multi-path-apparatus is that multiple passage operates, an independently flash memory device is shown as to main frame, and the flash memory device of multiple chips array string can support multiple equipment interface, multiple independently flash memory device can be shown as to main frame, many differences with general multi-passage flash memory apparatus are, multi-path-apparatus is that multiple passage operates, an independently flash memory device is shown as to main frame, and the flash memory device of multiple chips array string can support multiple equipment interface, multiple independently flash memory device can be shown as to main frame, when multiple chip array string is set to same flash memory device, multiple chip array string in this equipment can as the flash memory device of multiple passage, independent parallel operates, the reading and writing data speed of individual equipment is significantly improved.Main frame, for the operation between multiple equipment, can being done simply independently to operate, also by arranging, multiple equipment can be arranged to RAID, to meet the demand of user as the multiple memory device of general operation.Like this, the good lifting that made the performance of memory device have and improve the data security of equipment.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is further described in detail.
Fig. 1 is the structural representation that flash memory chip set becomes chip array string of the present invention.
Fig. 2 is the structural representation that chip array string of the present invention forms logical volume and file system logic volume manager.
Fig. 3 is the connection diagram of chip array string and chip array string controller.
Fig. 4 is the connection diagram of chip array string, chip array string controller and main frame.
Embodiment
As shown in Figure 1, a chip array string is composed in series by some MLC or SLC Flash chip of the same type, and the described chip array string that the flash chip of same MLC or SLC type forms is called MLC type chip array string or SLC type chip array string.Therefore, there is dissimilar chip array string in system simultaneously; The quantity of the chip array string of system support reaches thousands of, separately between multiple logical volume becomes system.
As shown in Figure 2, chip array string can be configured to the discernible logical volume of host file system by the LVM of host file system, comprises one or more chip array string in each logical volume.Logical volume 0 comprises chip array string0, chip array string1, chip array string2, is SLC type.Logical volume x comprises chip array stringM, chip array stringM+1, is MLC type.In addition, also comprise Redundant chip array string redundancy chip array string, can dynamically replace when certain chip array string makes mistakes.The storage medium of SLC type is because it is quick and long service life, and logical volume 0 is connected on internal bus Intenal Bus0, as system and frequently-used data storage medium.MLC is due to its suitable price, and logical volume x is connected on internal bus Intenal Bus1, as backup and the operation medium of data seldom wiped of mass data.Multiple chip array string connects according to RAID algorithm or in JBOD mode.
As Fig. 3, and shown in composition graphs 4, chip array string controller comprises processor unit, controller unit, interface unit and buffer unit, chip array string0, chip array string1, chip array string2 ..., chip array stringN respectively connection control device unit, interface unit connects host bus interface.Interface unit has dissimilar, comprise SATA, SAS and PCIe interface of connecting main frame, by host bus interface, and under the management of host driven and software systems, memory device be mapped as respectively the manageable equipment 0 of file system, equipment 1 ...., equipment N.
Briefly introduce the implementation method of native system below.
User uses the device driver software based on the memory device of chip array string that equipment is configured multiple different logical volume according to demand; Each logical volume comprises 1 or multiple chip array string.
Configuration information is issued chip array string controller by device driver software, is configured equipment firmware; Multiple flash chips that one single chip array string comprises are configured to an independently equipment, or multiple chip array string is configured to an equipment; Meanwhile, multiple autonomous device can be configured to RAID by main frame.
When user is to equipment operating, chip array string controller, according to the firmware of the configuration in ROM or upper strata instruction and device configuration information, is resolved instruction, and by control bus, controller unit is issued in instruction; Controller unit can comprise the control module of the different chip array string of multiple correspondence, and these control modules are hung on the control bus, accept the command operating of main frame for different chip array string, and are handed down to different chip array string;
In addition, controller also by the mode of parallel work-flow, can accept the operational order to different chip array string that main frame is sent, and parallel sends to different chip array string by instruction.
Advantage of the present invention comprises: 1. configurability; 2. can show as multiple independently memory device to main frame; 3. can be configured to RAID, improve the performance of whole equipment.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (1)
1. based on a storage means for the storage system of the memory device of solid storage medium, it is characterized in that, comprise the following steps:
Use the main process equipment drive software based on the memory device of chip array string that chip array string is configured multiple different logical volume according to demand, each logical volume comprises 1 or multiple chip array string;
Configuration information is issued chip array string controller by the device driver software of main frame, chip array string is configured, multiple flash chips that one single chip array string comprises are configured to an independently read-write equipment, or multiple chip array string is configured to a read-write equipment;
Multiple described read-write equipment is configured to RAID mode by main frame;
When read-write equipment operates, chip array string controller, according to the firmware of the configuration in ROM or upper strata instruction and device configuration information, is resolved instruction, and by control bus, controller unit is issued in instruction; Controller unit by instructions parse in the control module of the different chip array string of correspondence, described control module is hung on the control bus, accept the command operating of main frame for different chip array string, and be handed down to different chip array string, complete read-write operation.
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| CN201210058178.2A CN102662605B (en) | 2012-03-07 | 2012-03-07 | Storage device, storage system and storage method based on solid-state storage medium |
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| CN102662605B true CN102662605B (en) | 2015-06-24 |
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| AU2017290693B2 (en) * | 2016-06-29 | 2020-07-02 | Amazon Technologies, Inc. | Network-accessible data volume modification |
| CN107291397A (en) * | 2017-06-28 | 2017-10-24 | 山东超越数控电子有限公司 | A kind of implementation method of the disk array based on blending agent |
| CN116955241B (en) * | 2023-09-21 | 2024-01-05 | 杭州智灵瞳人工智能有限公司 | Memory chip compatible with multiple types of memory media |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101553032A (en) * | 2008-04-03 | 2009-10-07 | 华为技术有限公司 | Channel allocating method, device and base station sub-system |
| CN201725323U (en) * | 2010-06-07 | 2011-01-26 | 宇达电脑（上海）有限公司 | Independent redundant disk array |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101553032A (en) * | 2008-04-03 | 2009-10-07 | 华为技术有限公司 | Channel allocating method, device and base station sub-system |
| CN201725323U (en) * | 2010-06-07 | 2011-01-26 | 宇达电脑（上海）有限公司 | Independent redundant disk array |
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Address after: 430070 Hubei city of Wuhan province Wuhan East Lake New Technology Development Zone Road No. two high Guan Nan Industrial Park No. 2 building 2-3 floor West Applicant after: MEMORIGHT (WUHAN) Co.,Ltd. Address before: 430070 Hubei city of Wuhan province Kuanshan road Optics Valley Software Park building C3 on the third floor 301-303 room Applicant before: MEMORIGHT (WUHAN) Co.,Ltd. |
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Address after: 430070 Hubei city of Wuhan province Wuhan East Lake New Technology Development Zone Road No. two high Guan Nan Industrial Park No. 2 building 2-3 floor West Patentee after: EXASCEND TECHNOLOGY (WUHAN) CO.,LTD. Address before: 430070 Hubei city of Wuhan province Wuhan East Lake New Technology Development Zone Road No. two high Guan Nan Industrial Park No. 2 building 2-3 floor West Patentee before: MEMORIGHT (WUHAN) Co.,Ltd. |
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Denomination of invention: Storage device, storage system and storage method based on solid state storage medium Effective date of registration: 20211021 Granted publication date: 20150624 Pledgee: Bank of Hankou Limited by Share Ltd. Financial Services Center Pledgor: EXASCEND TECHNOLOGY (WUHAN) Co.,Ltd. Registration number: Y2021420000115 |
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Address after: 430000 west of 2-3 / F, No.2 factory building, Guannan Industrial Park, No.1 Gaoxin 2nd Road, Wuhan Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: Zhiyu Technology Co.,Ltd. Address before: 430070 Wuhan, Hubei Wuhan East Lake New Technology Development Zone, high-tech two Road No. 1 South Guan Industrial Park 2 factory 2-3 floor West. Patentee before: EXASCEND TECHNOLOGY (WUHAN) CO.,LTD. |