CN102645806A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN102645806A CN102645806A CN2012100936436A CN201210093643A CN102645806A CN 102645806 A CN102645806 A CN 102645806A CN 2012100936436 A CN2012100936436 A CN 2012100936436A CN 201210093643 A CN201210093643 A CN 201210093643A CN 102645806 A CN102645806 A CN 102645806A
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- 239000000758 substrate Substances 0.000 title abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 19
- 239000012212 insulator Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052779 Neodymium Inorganic materials 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010409 thin film Substances 0.000 description 11
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 9
- 230000008021 deposition Effects 0.000 description 4
- 239000012467 final product Substances 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an array substrate and a manufacturing method thereof. A resistor for providing a Gamma voltage is integrated in the array substrate to save the area originally reserved for the resistor in a printed circuit board (PCB); and because the array substrate only adopts the resistor to provide the Gamma voltage, compared with the an array substrate adopting a Power IC, the cost is reduced, and the power consumption of the array substrate provided by the invention is low. The array substrate provided by the invention comprises a resistor positioned between a gate insulation layer and a passivation layer, and at least one through hole formed on an area of the passivation layer covered by the resistor, wherein the resistor is not connected with an active layer and a source-drain electrode layer in the array substrate. The manufacturing method of the array substrate comprises the following steps of: forming the resistor on the gate insulation layer, wherein the resistor is separated from and not connected with the active layer and the source-drain electrode layer in the array substrate; and forming the passivation layer on the resistor, and forming at least one through hole on the area of the passivation layer covered by the resistor through etching.
Description
Technical field
The present invention relates to the display device technical field, relate in particular to a kind of array base palte and manufacturing approach.
Background technology
In existing liquid crystal indicator, the actual source electrode drive circuit voltage that offers of gamma (Gamma) voltage.Dual mode is mainly adopted in the generation of gamma in the driving circuit of liquid crystal panel (Gamma) voltage: first; As shown in Figure 1; Directly at PCB (Printed Circuit Board; Printed circuit board (PCB)) upward provides a voltage, share the form that this provides voltage with Chip-R 11 series connection then, provide Gamma voltage to source electrode drive circuit 12 through power IC (Power IC).The second, directly provide Gamma voltage through programmable Power IC.
Adopt first kind of mode that gamma voltage is provided, its circuit structure is simple, and power consumption can do very low.But, adopt first kind of mode to be the Chip-R slot milling, and increase the area of PCB because of needs.In panel increasing demand lightening today, reserving valuable pcb board area is very necessary to solve other problems.And, using various encapsulation continually, the resistance of different resistances brings trouble to a certain degree also can for the management and the supply of manufacturer.And pass through the second way; Be that Power IC able to programme directly provides Gamma voltage; This mode of voltage that provides is flexible, has shortened the time of Gamma voltage adjustment (Gamma Tuning), also can solve the difficulty that first method is brought to a great extent.But; Programmable Power IC itself is relatively more expensive; Adopt programmable Power IC can significantly improve production cost undoubtedly; Programmable Power IC is made up of a plurality of electronic components simultaneously, the power consumption that therefore provides gamma electric voltage also can improve product by programmable Power IC, and this respect also is the problem that panel vendor needs emphasis to consider.
Summary of the invention
The invention provides a kind of array base palte and manufacturing approach thereof, resistance is integrated in the array base palte, through giving the resistance in the array base palte voltage is provided, and voltage is derived so that voltage to be provided through equally distributed through hole on the dielectric layer covered above the resistance.So both practiced thrift out more spaces, and as long as through provide voltage with regard to exportable voltage to resistance, power consumption is also low for pcb board.
Array base palte provided by the invention, said array base palte comprises: the resistance between gate insulator and passivation layer, and on the zone of passivation layer covering resistance, at least one through hole is arranged;
Wherein, said resistance separates setting with active layer, source-drain electrode layer in the array base palte.
Said resistance is strip.
Said through hole evenly distributes on the length direction of strip resistance.
The material of said resistance is an amorphous silicon.
In the said through hole metal level is arranged.
N type amorphous silicon layer is arranged in the said through hole, and said N type amorphous silicon layer is between said metal level and resistance.
The material of said metal level is a kind of metal or several kinds of alloys that constitute in molybdenum, aluminium, neodymium, titanium, chromium, tantalum or the copper.
The present invention also provides a kind of display device, and this display device comprises above-mentioned array base palte.
The present invention also provides the method for making above-mentioned array base palte, and this method comprises:
Formation resistance on gate insulator, wherein, said resistance separates setting with active layer, source-drain electrode layer in the array base palte;
On resistance, form passivation layer, and, form at least one through hole through on the zone that is etched in passivation layer covering resistance.
Said after forming resistance on the gate insulator, before forming passivation layer on the resistance, this method further comprises:
On said resistance, and the position that needs to form through hole forms metal level.
After forming resistance on the gate insulator, before forming passivation layer on the resistance, this method further comprises:
On said resistance, and need the position of formation through hole to form metal level and N type amorphous silicon layer, said N type amorphous silicon layer is between said metal level and resistance.
Array base palte provided by the invention is integrated in resistance wherein, reduces the pcb board area take in order to set up resistance separately, and adopts and be integrated in the resistance in the array base palte, and cost is not high and power consumption is lower.
Description of drawings
Fig. 1 is for providing the structure of Gamma voltage through Chip-R in the existing mode of the present invention;
Fig. 2 is the sectional view of embodiment of the invention array base palte resistance region;
Fig. 3 is the structural representation of array base palte embodiment of the present invention;
Fig. 4 is the resistance position view of array base palte embodiment of the present invention;
Fig. 5 is a through hole distribution schematic diagram in the embodiment of the invention;
Fig. 6 applies the sectional view of voltage to grid layer for embodiment of the invention array base palte resistance region;
Fig. 7 is the process flow diagram of the inventive method embodiment.
Embodiment
In order to practice thrift the area of pcb board, avoid the big cost and the high power consumption that adopt programmable Power IC to expend simultaneously, the invention provides a kind of array base palte.Embodiment to this array base palte describes below in conjunction with accompanying drawing.
Array base palte in the present embodiment; As shown in Figure 2; Be from bottom to top glass substrate 21, grid layer 22, gate insulator 23, resistance 24 between gate insulator 23 and passivation layer 25, and cover at passivation layer 25 on the zone of resistance 24 at least one through hole 26 arranged.When connecting voltage for resistance 24 two ends, can ohmically voltage be derived so that dividing potential drop to be provided through through hole 26.
Through hole 26 described in the present embodiment is to be used for the voltage that is added on the resistance 24 is guided.In fact, also can be through forming through hole in the end positions of resistance, needs are added in the through hole of ohmically voltage through the resistance two ends are added on the resistance.But the through hole at resistance two ends is different through holes with through hole described in the present embodiment 26, acts on also different.Certainly, also can before forming passivation layer, just form lead-in wire earlier at the resistance two ends, then when needs apply voltage to resistance, can directly be connected on the lead-in wire of prior formation and get final product.
What provide in the present embodiment is integrated in the resistance in the array base palte, and as shown in Figure 3, said resistance is arranged in array base palte, can be used for providing Gamma voltage to source electrode drive circuit, but not only for being used to that Gamma is provided voltage condition.Other need to provide with resistance the situation of dividing potential drop, and the resistance that is integrated in array base palte that all can adopt present embodiment to provide.
Certainly, in the practice, the resistance quantity on each array base palte is restriction not, can be according to the quantity and the position of actual conditions setting resistance voluntarily.Such as, to bigger array base palte, then can set the resistance in a plurality of present embodiments.Each resistance all is integrated between the gate insulator and passivation layer of array base palte, through applying certain voltage at the resistance two ends, just can be from the through hole of resistance region top passivation layer extraction voltage.
And does not limit the position that is positioned at array base palte for resistance yet, and the mode of placement resistance as shown in Figure 4 is a kind of embodiment.Actually can as required resistance be positioned over any one position in the array base palte; Only need to guarantee in resistance and the array base palte that separation is not connected thin film switch with pixel electrode area, feasiblely be added in ohmically voltage and can not impact and get final product thin film switch and pixel electrode.
Adopt the method in the array base palte that resistance is integrated into shown in Figure 3,, be integrated in the area that resistance in the array base palte has been practiced thrift pcb board undoubtedly with respect to the mode that in pcb board, adopts Chip-R.Simultaneously; The resistance that is integrated in array base palte is with respect to adopting the programmable integrated circuit source so that the mode of Gamma voltage to be provided; The resistance that only need be integrated in the array base palte can provide gamma electric voltage; And do not need a large amount of electronic components to export required gamma electric voltage, and therefore then power consumption is lower, and cost is lower.
When Gamma voltage being provided, the Gamma voltage of identical magnitude of voltage need be provided for each dot structure for source electrode drive circuit.So preferably mode is that resistance is strip, and said through hole evenly distributes on the length direction of resistance, and is specifically as shown in Figure 5, such is designed with 2 benefits:
One, because resistance is strip; When needs are exported the voltage of specific a certain numerical value; Concrete resistance that can not need know resistance; And just when apply the voltage of a known voltage value at the resistance two ends, the through hole of deriving voltage and resistance two ends are the magnitude of voltage of an end wherein, can through the calculating through hole extremely the distance of an aforementioned wherein end multiply by the known voltage value again divided by the resistance total length that is used to apply the known voltage value part and get final product.Among Fig. 5, be U at the A of strip resistance, the magnitude of voltage that the B two ends are connected, for example so the voltage difference of the 4th through hole (through hole 4) and through hole B can draw through L4/L*U.
Two, through hole evenly distributes on the length direction of resistance, can satisfy easily as long as through hole is identical with distance between the through hole and just can export equal voltage.For example the magnitude of voltage of output just equals the magnitude of voltage of through hole 3 and through hole 4 outputs between through hole among Fig. 41 and the through hole 2, because through hole 1 equals the distance that through hole 3 arrives through hole 4 to the distance of through hole 2.Need to obtain this advantage, the shape of resistance itself is uniform.Like this, the resistance between through hole 1 and the through hole 2 just can and through hole 3 and through hole 4 between resistance identical.
And through hole even distribution on the length direction of resistance can have multiple distribution mode, can arrange the position that through hole carries out according to actual conditions.For example, when need be from per two adjacent through holes all the extraction voltage value equate voltage the time, just can set be useful on the resistance draw dividing potential drop through hole all between any two apart from equal.If desired through hole is divided; As shown in Figure 5, the dividing potential drop that need from through hole 1～6, draw between two two through hole equates, and the dividing potential drop that two two through hole finger tips are drawn from through hole 7～11 equates; But and the dividing potential drop of drawing between two two through hole in the front through hole 1～6 does not wait; Then the distance between two two through hole equates and evenly distributes in the through hole 1～6, and the distance in the through hole 7～11 between two two through hole equates and evenly distribute, but through hole 1, the distance between 2 and through hole 7, the distance between 8 do not wait.
Need to prove that resistance is that strip and through hole even these two designs that distribute on the length direction of resistance are not to exist simultaneously.The effect of having only one of them also can reach a correspondence just has two better effects if.
In the present embodiment, resistance 24 can be made up of the material that difference can be used as resistance, and preferred a-Si (amorphous silicon, amorphous silicon) is as the material of processing resistance in the present embodiment.Amorphous silicon is a kind of semiconductor film material, adopts amorphous silicon to prepare resistance, not only can make it reach the effect of resistance; Also because the characteristic of amorphous silicon itself; Make that the technology of making amorphous silicon resistance is simple relatively, raw materials consumption is little, and price is more cheap.
Lead-in wire in array base palte can be made up of multiple different conductive materials, like conducting metal etc.Preferred ITO (tin indium oxide) is as the material of lead-in wire in the present embodiment.In the present embodiment, through having on the passivation layer of through hole, form the ITO layer, the ohmically component voltage that will connect voltage through ITO layer and contacting of resistance derives.
In order to make lead-in wire can better component voltage be derived, avoid lead-in wire and resistance 24 surface of contact generation oxidations to change, preferably, layer of metal layer 28 can be arranged in through hole as buffering.And the ITO layer 29 that is covered in metal level 28 contacts the voltage derivation that will put on the resistance 24 with metal level 28.
Preferably, N type amorphous silicon layer 27 can also be arranged in the through hole, wherein N type amorphous silicon layer 27 is in through hole and be between said metal level 28 and the resistance 24.
Because the electric conductivity of metal level is strong more a lot of than semiconductor, between metal level and resistive layer, also is easy to produce electric potential difference.So just need between metal level and resistance, add one deck N type amorphous silicon 27 again; The electric conductivity of N type amorphous silicon layer is better, slightly poorer than metal than amorphous silicon, therefore it is positioned over the electric potential difference that can slow down metal level 28 and amorphous silicon 24 between amorphous silicon and the metal level.
In order to increase the conductance of resistive layer; Can on the grid under the gate insulator, increase a voltage that equates with the magnitude of voltage that applies at the resistance two ends (as shown in Figure 6); Because the voltage that applies can make the electronics in the resistance accumulate in the zone that contacts with gate insulator, and in the inner hole that forms of resistance.When applying the voltage that equates with the magnitude of voltage that applies at the resistance two ends in grid, make the concentration of electronics more than or equal to the concentration in hole, so just on the resistance that amorphous silicon constitutes, form the space charge region, be weak inversion layer.After weak inversion layer forms, when applying voltage, can increase the resistance conductance at the resistance two ends.
Array base palte in the present embodiment comprises the sheet resistance that is integrated in wherein, and is covered in the through hole on the ohmically passivation layer.Can be through on resistance, applying voltage, and from through hole, derive voltage so that voltage to be provided.And, therefore when knowing resistance, still can not draw the voltage between the through hole according to the distance between the through hole and resistance two ends distance and the magnitude of voltage that is applied to the resistance two ends apart because through hole is to be evenly distributed on the length direction of strip resistance.And, also be easily each dot structure equivalent voltage be provided.
Display device provided by the invention, as shown in Figure 3, adopt the above-mentioned integrated array base palte of resistance.Through applying voltage so that the Gamma voltage of source electrode drive circuit to be provided for the resistance in the array base palte.
The present invention also provides the method for making above-mentioned array base palte.Below in conjunction with accompanying drawing the method for preparing substrate in the present embodiment is described.
The method for making of array base palte is as shown in Figure 7, comprising:
Step S501 forms grid layer on glass substrate.The formation of grid layer can be accomplished through the step of deposition and etching.Through deposition, form the common method that thin-film electronic element is this area making array base palte through carrying out etching after the mask plate exposure.
Step S502 forms gate insulator on the monolithic glass substrate that forms grid layer.
Step S503, the formation resistance on gate insulator.Method through deposition and etching forms resistance.Because also have N type amorphous silicon layer and metal level in the through hole, said metal level is arranged in through hole, said N type amorphous silicon layer is in through hole and is between said metal level and the resistance.Form for metal level and N type amorphous silicon layer, can deposit etching respectively respectively, full exposure that also can be through a mask plate and half exposure technique form resistance, N type amorphous silicon layer and metal level through step etching again behind single exposure.
Because the material of resistance can be an amorphous silicon, also is amorphous silicon at the thin film switch of array base palte and the material of the active layer in the pixel electrode area.Therefore when forming resistance, can form separately, also can together form with the amorphous silicon structures in the dot structure.And the material of thin film switch in the array base palte and the source-drain layer in the pixel electrode also is a N type amorphous silicon layer, so the N type amorphous silicon layer in the through hole can form with the source-drain layer in thin film switch and the pixel electrode simultaneously, also can separate formation separately.
The material of metal level is a kind of metal or several kinds of alloys that constitute in molybdenum, aluminium, neodymium, titanium, chromium, tantalum or the copper.
Step S504 forms passivation layer on resistance, and through on the zone that is etched in passivation layer covering resistance, forms at least one through hole.The through hole that passivation layer needs forms through a mask plate etching after deposit passivation layer.Metal level that after through hole forms passivation layer is covered originally and N type amorphous silicon layer expose.Said metal level is filled in the through hole, and said N type amorphous silicon layer is filled in the through hole and is between said metal level and the resistance.
At last, above passivation layer, form lead-in wire.Lead-in wire can form through deposition and etching.The material of lead-in wire can be ITO.
In order to increase the usable range of the resistance in the array base palte, can increase the number of openings of passivation layer.And in through hole, all be filled with N type amorphous silicon layer and metal level accordingly.Also form the ITO layer on the metal level in through hole as lead-in wire.When through hole that need to have confirmed as required to use, can only connect required through hole and get final product through the fusing that will go between of heat shock light beam for unwanted through hole.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (11)
1. an array base palte is characterized in that, said array base palte comprises:
Resistance between gate insulator and passivation layer, and on the zone of passivation layer covering resistance, at least one through hole is arranged;
Wherein, said resistance separates setting with active layer, source-drain electrode layer in the array base palte.
2. array base palte according to claim 1 is characterized in that, said resistance is strip.
3. array base palte according to claim 1 and 2 is characterized in that, said through hole evenly distributes on the length direction of resistance.
4. array base palte according to claim 1 is characterized in that, the material of said resistance is an amorphous silicon.
5. array base palte according to claim 1 is characterized in that, in the said through hole metal level is arranged.
6. array base palte according to claim 5 is characterized in that, also has N type amorphous silicon layer in the said through hole, and said N type amorphous silicon layer is between said metal level and resistance.
7. array base palte according to claim 5 is characterized in that, the material of said metal level is a kind of metal or several kinds of alloys that constitute in molybdenum, aluminium, neodymium, titanium, chromium, tantalum or the copper.
8. a display device is characterized in that, this display device comprises aforesaid right requirement 1～7 described any one array base palte.
9. the method for making of an array base palte is characterized in that, this method comprises:
On gate insulator, form resistance, wherein, said resistance separates setting with active layer, source-drain electrode layer in the array base palte;
On resistance, form passivation layer, and cover on the zone of resistance, form at least one through hole at passivation layer.
10. method for making according to claim 9 is characterized in that, said after forming resistance on the gate insulator, this method further comprises:
On said resistance, and the position that needs to form through hole forms metal level.
11. method for making according to claim 9 is characterized in that, said after forming resistance on the gate insulator, this method further comprises:
On said resistance, and need the position of formation through hole to form N type amorphous silicon layer and metal level, said N type amorphous silicon layer is between said metal level and resistance.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210093643.6A CN102645806B (en) | 2012-03-31 | 2012-03-31 | Array substrate and manufacturing method thereof |
| PCT/CN2012/085484 WO2013143312A1 (en) | 2012-03-31 | 2012-11-28 | Array substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210093643.6A CN102645806B (en) | 2012-03-31 | 2012-03-31 | Array substrate and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN102645806A true CN102645806A (en) | 2012-08-22 |
| CN102645806B CN102645806B (en) | 2015-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210093643.6A Expired - Fee Related CN102645806B (en) | 2012-03-31 | 2012-03-31 | Array substrate and manufacturing method thereof |
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| CN (1) | CN102645806B (en) |
| WO (1) | WO2013143312A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013143312A1 (en) * | 2012-03-31 | 2013-10-03 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
| CN105047152A (en) * | 2015-08-05 | 2015-11-11 | 昆山龙腾光电有限公司 | Display module |
| CN106057141A (en) * | 2016-05-04 | 2016-10-26 | 深圳市华星光电技术有限公司 | Gamma reference voltage generation circuit and display |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2677167B2 (en) * | 1993-07-08 | 1997-11-17 | 日本電気株式会社 | Method for manufacturing liquid crystal display device with built-in drive circuit |
| CN1194039A (en) * | 1995-08-07 | 1998-09-23 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
| US6246460B1 (en) * | 1998-11-20 | 2001-06-12 | U.S. Philips Corporation | Active matrix liquid crystal display devices |
| US6639244B1 (en) * | 1999-01-11 | 2003-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN201876643U (en) * | 2010-11-22 | 2011-06-22 | 京东方科技集团股份有限公司 | Array substrate and LCD panel |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102645806B (en) * | 2012-03-31 | 2015-02-18 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
-
2012
- 2012-03-31 CN CN201210093643.6A patent/CN102645806B/en not_active Expired - Fee Related
- 2012-11-28 WO PCT/CN2012/085484 patent/WO2013143312A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2677167B2 (en) * | 1993-07-08 | 1997-11-17 | 日本電気株式会社 | Method for manufacturing liquid crystal display device with built-in drive circuit |
| CN1194039A (en) * | 1995-08-07 | 1998-09-23 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
| US6246460B1 (en) * | 1998-11-20 | 2001-06-12 | U.S. Philips Corporation | Active matrix liquid crystal display devices |
| US6639244B1 (en) * | 1999-01-11 | 2003-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN201876643U (en) * | 2010-11-22 | 2011-06-22 | 京东方科技集团股份有限公司 | Array substrate and LCD panel |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013143312A1 (en) * | 2012-03-31 | 2013-10-03 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
| CN105047152A (en) * | 2015-08-05 | 2015-11-11 | 昆山龙腾光电有限公司 | Display module |
| CN106057141A (en) * | 2016-05-04 | 2016-10-26 | 深圳市华星光电技术有限公司 | Gamma reference voltage generation circuit and display |
| WO2017190429A1 (en) * | 2016-05-04 | 2017-11-09 | 深圳市华星光电技术有限公司 | Gamma reference voltage generating circuit and display device |
| US10152934B2 (en) | 2016-05-04 | 2018-12-11 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Gamma reference voltage generation circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013143312A1 (en) | 2013-10-03 |
| CN102645806B (en) | 2015-02-18 |
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