CN102638247B - Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator - Google Patents
Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator Download PDFInfo
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- CN102638247B CN102638247B CN201210069285.5A CN201210069285A CN102638247B CN 102638247 B CN102638247 B CN 102638247B CN 201210069285 A CN201210069285 A CN 201210069285A CN 102638247 B CN102638247 B CN 102638247B
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Abstract
The invention relates to a clock generating method and a clock generating circuit for a CMOS (complementary metal oxide semiconductor) without a crystal oscillator. The clock generating method includes: generating high-frequency sine oscillation signals by a digital-control oscillator; converting the high-frequency sine oscillation signals into square-wave signals output in single-end mode; underclocking the square-wave signals to obtain clock signals of preset frequency according to preset fractional frequency; regulating duty ratio of the clock signals so that the duty ratio of the clock signals can meet the requirement of preset duty ratio of clock, and outputting the clock signals, wherein a variable capacitor array in the digital-control oscillator is controlled by frequency locking control information. A method for setting the frequency locking control information includes: generating frequency control information according to frequency difference between output signals of an external crystal oscillator and the clock signals underclocked. By the clock generating method, the clock generating circuit can be smaller in size and lower in power consumption, low-cost CMOS technology can be realized in chips, and accordingly, integrity and stability of the system are improved, system realizing cost and power consumption are reduced.
Description
Technical field
The present invention relates to clock generating technology, particularly relate to a kind of without crystal oscillator cmos clock production method and without crystal oscillator cmos clock generation circuit.
Background technology
Clock signal is very important for a lot of electronic products, and the each element in electronic product can collaborative work under the effect of clock signal.
At present, clock generating mode mainly comprises following three kinds:
Mode one, utilize phase-locked loop (Phase Lock Loop, PLL) frequency synthesizer clocking.An object lesson of phase-locked loop frequency integrator as shown in Figure 1.
Phase-locked loop frequency integrator in Fig. 1 mainly comprises: crystal oscillator, frequency divider (comprising the programmable frequency divider in Fig. 1), phase frequency detector, charge pump, low pass filter and voltage controlled oscillator.Phase frequency detector is the phase place of two input signals relatively, and produces the voltage that phase difference is directly proportional therewith.High fdrequency component and noise in the above-mentioned voltage of low pass filter filtering, to increase the stability of system.Voltage controlled oscillator is subject to voltage control, exports corresponding clock signal, and the frequency of this clock signal is the multiple of crystal oscillator frequency normally, as integral multiple or little several times.
Mode two, utilize bulk acoustic wave piezo-electric resonator clocking.
Bulk acoustic wave piezo-electric resonator has very high Q value (can reach 48000), can produce the good oscillator signal of quality (as the phase noise of the clock signal of 10MHz is-125dBc/Hz@1kHz), and can pass through MEMS (Micro-electromechanical System, MEMS (micro electro mechanical system)) technology is embedded into bulk acoustic wave piezo-electric resonator in the encapsulation of chip.
Mode three, utilize thin film bulk acoustic resonator clocking.
Thin film bulk acoustic resonator (FBAR, Film Bulk Acoustic Resonator) utilize the physical characteristic of piezoelectric membrane, Q value higher (being conventionally greater than 1000), not only can produce the good oscillator signal of quality, and power consumption is very low.In addition, FBAR also has higher operating frequency (as > 5GHz), lower temperature coefficient and can adopt the features such as IC (integrated circuit) technique.
Inventor finds realizing in process of the present invention: aforesaid way one exists to be realized outside sheet and the problem such as power consumption height; Concrete, along with the development of large scale integrated circuit technology, the integrated level of chip is more and more higher, and the area of chip is more and more less, and crystal oscillator adopts the outer mode realizing of sheet conventionally; But the outer implementation of sheet can affect area, cost and the reliability of system; In addition, the power consumption of crystal oscillator and adjunct circuit thereof is not low, thereby becomes a development bottleneck of low-power consumption product.MEMS technology in aforesaid way two is incompatible with the integrated circuit CMOS technique of current main flow, has the high and problem such as be of limited application of cost of manufacture.Although aforesaid way three can adopt IC technique,, because needing some special materials, makes as AIN, ZnO piezoelectric membrane, therefore, with standard CMOS process flow process incompatible; In addition, thin film bulk acoustic resonator is the same with bulk acoustic wave piezo-electric resonator, although can be embedded in the encapsulation of chip, is difficult to the real comprehensively integrated of the system that realizes.
Summary of the invention
The object of the invention is to, overcome the problem that existing clock generating technology exists, and provide a kind of without crystal oscillator cmos clock production method and circuit, technical problem to be solved is, allow to that the volume of the clock generation circuit that high accurate clock signal is provided is less and power consumption is lower, and can utilize CMOS technology cheaply to realize in chip, thereby further improve integrated level and the stability of system, and reduce system and realize cost and power consumption.
The object of the invention to solve the technical problems can adopt following technical scheme to realize.
The one proposing according to the present invention, without crystal oscillator cmos clock production method circuit, comprising: utilize digital controlled oscillator to produce high frequency pure oscillation signal; Described high frequency pure oscillation signal is converted to the square-wave signal of single-ended mode output; According to predetermined frequency dividing ratio, described square-wave signal is carried out to down conversion process, obtain the clock signal of preset frequency; Adjust the duty ratio of described clock signal, make the duty ratio of described clock signal meet the requirement of predetermined clock duty ratio, the clock signal after output duty cycle is adjusted; Wherein, variable capacitance array in described digital controlled oscillator is controlled by Frequency Locking control information, and the set-up mode of described Frequency Locking control information comprises: produce Frequency Locking control information according to the difference on the frequency of the clock signal after the output signal of external crystal-controlled oscillation and described down conversion process.
The one proposing according to the present invention produces circuit without crystal oscillator cmos clock, comprising: digital controlled oscillator, and for generation of high frequency pure oscillation signal, and output; Level switch module, is connected with described digital controlled oscillator, for described high frequency pure oscillation signal being converted to the square-wave signal of single-ended mode output; Programmable frequency divider, is connected with described level switch module, for according to predetermined frequency dividing ratio, described square-wave signal being carried out to down conversion process, and exports the clock signal with preset frequency obtaining after down conversion process; Duty-cycle correction circuit, is connected with described programmable frequency divider, for adjusting the duty ratio of described clock signal, makes the duty ratio of described clock signal meet the requirement of predetermined clock duty ratio, the clock signal after output duty cycle is adjusted; Frequency Locking module, be connected with described programmable frequency divider, and arranging in the process of Frequency Locking control information, described Frequency Locking module is also connected with external crystal-controlled oscillation, for producing Frequency Locking control information according to the difference on the frequency of the output signal of the output signal of described external crystal-controlled oscillation and described programmable frequency divider, and output, described Frequency Locking control information is for controlling the variable capacitance array of described digital controlled oscillator; Non-volatility memorizer, be connected respectively with described Frequency Locking module and digital controlled oscillator, for storing the Frequency Locking control information of described Frequency Locking module output, described digital controlled oscillator obtains described Frequency Locking control information from described non-volatility memorizer.
Object of the present invention and solve its technical problem and can also be further achieved by the following technical measures.
Preferably, aforesaid without crystal oscillator cmos clock generation circuit, wherein said digital controlled oscillator comprises: metal-oxide-semiconductor Mn1, Mn2, Mp1, Mp2 and Mp3, LC resonant slots and frequency self calibration module;
Described metal-oxide-semiconductor Mn1, Mn2, Mp1 and Mp2 form cross-coupling unit, are used to described LC resonant slots that negative resistance energy is provided; Described metal-oxide-semiconductor Mp3 is connected with described cross-coupling unit, is used to described cross-coupling unit that biasing tail current is provided; Described LC resonant slots comprises: inductance, fixed capacity and two groups of variable capacitance arrays, and described inductance, fixed capacity and two groups of variable capacitance arrays are connected with described cross-coupling unit respectively, wherein one group of variable capacitance array is controlled by frequency self calibration module, and another group variable capacitance array is controlled by described Frequency Locking control information.
Preferably, aforesaid without crystal oscillator cmos clock generation circuit, wherein said frequency self calibration module comprises: temperature sensor and connected analog to digital converter, and described analog to digital converter is connected with described cross-coupling unit.
Preferably, aforesaid without crystal oscillator cmos clock generation circuit, wherein every group of variable capacitance array includes multiple variable-capacitance unit, and each variable-capacitance unit includes: a variable capacitance and a connected switching tube.
Preferably, aforesaid without crystal oscillator cmos clock generation circuit, wherein variable capacitance comprises: N-type MOS varactor and P type MOS varactor, and N-type MOS varactor and the parallel connection of P type MOS varactor.
Preferably, aforesaidly produce circuit without crystal oscillator cmos clock, wherein said digital controlled oscillator also comprises: amplitude detection unit and common mode feedback unit, and described amplitude detection unit and common mode feedback unit are respectively with described cross-coupling unit and connect.
Preferably, aforesaid without crystal oscillator cmos clock generation circuit, wherein said level switch module comprises: the first conversion submodule, for the high frequency pure oscillation signal of digital controlled oscillator output is converted to single-ended mode sinusoidal signal; The second conversion submodule, for being converted to described single-ended mode sinusoidal signal the square-wave signal of single-ended mode output.
Preferably, aforesaid without crystal oscillator cmos clock generation circuit, wherein said programmable frequency divider is the programmable frequency divider that adopts tandem type structural design.
Preferably, aforesaid without crystal oscillator cmos clock generation circuit, in wherein said programmable frequency divider, store predetermined frequency dividing ratio, and the numerical value of this predetermined frequency dividing ratio can be modified; Described predetermined clock duty ratio requires to comprise: 50%.
By technique scheme, of the present invention at least have following advantages and beneficial effect without crystal oscillator cmos clock production method and circuit: the present invention by only arranging the Frequency Locking control information of the variable capacitance array in digital controlled oscillator in the frequency calibration process of clock signal with crystal oscillator, after the frequency calibration of clock signal, do not re-use crystal oscillator, and carry out each element that clock signal produces operation all with the compatibility completely of integrated circuit CMOS technique cheaply, avoided the problems such as chip arranges, comprehensive integrated and high power consumption that can not be real outward; Thereby provided by the invention without crystal oscillator cmos clock produce circuit owing to need to not use crystal oscillator in course of normal operation, and can adopt standard CMOS process to be integrated in chip, therefore, realize real fully integrated monolithic clock and produced circuit, not only can make the volume of circuit system less, power consumption is lower, cost is also lower, but also can avoid circuit because to be collided and shake and cause circuit damage phenomenon, and then the present invention improved integrated level and the stability of system, and reduced system realize cost and power consumption.
In sum, the present invention has significant progress technically, and has significantly positive technique effect, becomes a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing phase-locked loop frequency integrator;
Fig. 2 is the schematic diagram without crystal oscillator cmos clock generation circuit of the embodiment of the present invention;
Fig. 3 is the schematic diagram of the digital controlled oscillator of the embodiment of the present invention;
Fig. 4 is the schematic diagram of the variable capacitance of the embodiment of the present invention;
Fig. 5 is the C-V characteristic curve schematic diagram of single NMOS varactor and single PMOS varactor;
Fig. 6 is the C-V characteristic curve schematic diagram of variable capacitance of the present invention;
Fig. 7 is the operation principle schematic diagram of Frequency Locking module.
Embodiment
Technological means and effect of taking for reaching predetermined goal of the invention for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to according to the present invention propose without crystal oscillator CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) clock generation method and its embodiment of circuit, structure, feature and effect, be described in detail as follows.
Embodiment mono-, without crystal oscillator cmos clock production method.
The method of the present embodiment is the method that produces high-precision clock signal on the basis of digital controlled oscillator.It should be noted that, " without the crystal oscillator " in the present invention refers to needs the electronic equipment of clock signal in normal use procedure (as after dispatching from the factory) not need to use crystal oscillator, and the clock signal of electronic equipment is not to be provided by crystal oscillator; Crystal oscillator only uses in the time that the Frequency Locking control information of the variable capacitance array in digital controlled oscillator is set, as crystal oscillator only uses before electronic equipment dispatches from the factory or when electronic equipment maintenance.
The method of the present embodiment specifically comprises:
First, digital controlled oscillator produces high frequency pure oscillation signal.The high frequency pure oscillation signal is here the signal after digital controlled oscillator difference processing, and therefore, this high frequency pure oscillation signal also can be called difference sinusoidal signal.Digital controlled oscillator of the present invention can be for having the digital controlled oscillator of frequency self-calibration function (as the frequency self-calibration function based on temperature), to keep constant frequency of oscillation.This digital controlled oscillator can comprise variable capacitance array (as two groups of variable capacitance arrays), and variable capacitance array (as one group of variable capacitance array wherein) can be controlled by Frequency Locking control information.This Frequency Locking control information should pre-set, and after disposable setting completes, can no longer need to reset; For example, in the time that electronic equipment dispatches from the factory, this Frequency Locking control information has just set, and like this, in the normal use procedure of electronic equipment, has carried out setting operation again with regard to not needing.The present embodiment can adopt existing digital controlled oscillator; But in order to improve the precision of clock signal, the present invention can improve existing digital controlled oscillator, as adopted the digital controlled oscillator shown in accompanying drawing 3, the concrete structure of this digital controlled oscillator, as the description in following embodiment bis-, no longer describes in detail at this.
Secondly the high frequency pure oscillation signal, digital controlled oscillator being produced is converted to the square-wave signal of single-ended mode output.The existing signal switch technology that can adopt the present embodiment realizes the conversion of high frequency pure oscillation signal to the square-wave signal of single-ended mode output, for example, can first the high frequency pure oscillation signal of digital controlled oscillator output be converted to single-ended mode sinusoidal signal, then this single-ended mode sinusoidal signal be converted to the square-wave signal of single-ended mode output.The present embodiment can adopt existing element to realize above-mentioned signal conversion.
Again, the square-wave signal above-mentioned conversion being obtained afterwards according to predetermined frequency dividing ratio carries out down conversion process, to obtain the clock signal of preset frequency.The predetermined frequency dividing ratio is here according to electronic equipment, the actual demand of clock frequency to be set in advance.The present embodiment can adopt existing element to realize above-mentioned down conversion process.
Finally, adjust the duty ratio of the clock signal that above-mentioned down conversion process obtains, make the duty ratio of clock signal meet the requirement of predetermined clock duty ratio, the clock signal after output duty cycle is adjusted.The clock signal that duty ratio adjustment is exported is afterwards the high accurate clock signal without crystal oscillator that the present embodiment provides for electronic equipment.The predetermined clock duty ratio requirement is here that the actual demand of the duty ratio to clock signal according to electronic equipment sets in advance, and can be a concrete numerical value, as 50%.The present embodiment can adopt existing element to realize above-mentioned duty ratio adjustment.
The above-mentioned concrete mode that its Frequency Locking control information is set for the variable capacitance array in digital controlled oscillator can be: receive the clock signal after signal and the down conversion process of interim external crystal-controlled oscillation output, determine difference on the frequency between the two, and produce Frequency Locking control information according to this difference on the frequency, this Frequency Locking control information can store, thereby in the time that electronic equipment normally uses, can directly obtain Frequency Locking control information according to this storage, to control the variable capacitance array in digital controlled oscillator.Above-mentioned setting up procedure also can be called the frequency calibration process of clock signal.
Embodiment bis-, without crystal oscillator cmos clock produce circuit.The structure of this circuit as shown in Figure 2.
Comprising without crystal oscillator cmos clock generation circuit in Fig. 2: digital controlled oscillator 101, level switch module 102, programmable frequency divider 103, duty-cycle correction circuit 104, Frequency Locking module 105 and non-volatility memorizer 106.Wherein, digital controlled oscillator 101 is connected respectively with level switch module 102 and non-volatility memorizer 106, programmable frequency divider 103 is connected respectively with level switch module 102, duty-cycle correction circuit 104 and Frequency Locking module 105, and non-volatility memorizer 106 is connected with Frequency Locking module 105.
Digital controlled oscillator 101 is mainly for generation of high frequency pure oscillation signal (also can be called difference sinusoidal signal), and to level switch module 102 these high frequency pure oscillation signals of output.Digital controlled oscillator 101 is core circuits of clocking, there is frequency self-calibration function, for example, in the time that ambient temperature changes, digital controlled oscillator 101 can ensure the constant high frequency pure oscillation signal of output frequency of oscillation by its frequency self-calibration function.
Digital controlled oscillator 101 can comprise: five metal-oxide-semiconductors (being Mn1, Mn2, Mp1, Mp2 and Mp3), LC resonant slots and frequency self calibration module; In addition, this digital controlled oscillator 101 can also comprise: amplitude detection unit 203 and common mode feedback unit 204.Said frequencies self calibration module can be specially temperature sensor 201 and connected analog to digital converter 202.
A concrete example of digital controlled oscillator 101 as shown in Figure 3.
In Fig. 3, four metal-oxide-semiconductors in five metal-oxide-semiconductors are that Mn1, Mn2, Mp1 and Mp2 form cross-coupling unit, cross-coupling unit is mainly used in providing negative resistance energy for LC resonant slots, another metal-oxide-semiconductor is that Mp3 is connected with above-mentioned cross-coupling unit, and Mp3 is mainly used in providing biasing tail current for cross-coupling unit.LC resonant slots comprises: inductance L, fixed capacity C and variable capacitance array, and inductance L, fixed capacity C and two groups of variable capacitance arrays are connected with above-mentioned cross-coupling unit respectively; Variable capacitance array wherein can be divided into two groups, one group forms (m > 2) by m variable capacitance Cf and m switch transistor T f, be controlled by temperature sensor 201, in the time that ambient temperature changes, clock signal can be offset, and temperature sensor 201, after the variation that temperature detected, provides digital signal by analog to digital converter 202 for this group variable capacitance array, can change the size of variable capacitance, thereby adjust the frequency of the signal of its output; Another group forms (n > 2) by n variable capacitance Cr and n switch transistor T r, is controlled by Frequency Locking control information (the Frequency Locking control information reading out from the non-volatility memorizer 106 of Fig. 2).Amplitude detection unit 203 and common mode feedback unit 204 are respectively with above-mentioned cross-coupling unit and connect, and the effect of amplitude detection unit 203 and common mode feedback unit 204 comprises: make the amplitude of the output signal of digital controlled oscillator 101 remain on (being that amplitude output signal keeps stablizing) in a fixing scope, like this, not only be conducive to the processing of late-class circuit, and improved the phase noise performance of digital controlled oscillator 101.
A concrete example of above-mentioned variable capacitance Cf or Cr as shown in Figure 4.
In Fig. 4, variable capacitance Cf or Cr comprise a N-type MOS (being NMOS) varactor Mn0 and a P type MOS (being PMOS) varactor Mp0, and Mn0 and Mp0 are connected in parallel.The C-V characteristic curve of single NMOS varactor and single PMOS varactor as shown in Figure 5.
As can be seen from Figure 5, no matter be single NMOS varactor, or single PMOS varactor, all steeper of its C-V characteristic curve, that is to say, even if control voltage Vctrl, very little variation occurs, the variable capacitance of single NMOS varactor and single PMOS varactor all can be along with producing larger variation, and this phenomenon is unfavorable for the frequency adjustment of digital controlled oscillator 101.
Fig. 6 shows the C-V characteristic curve of the variable capacitance that employing of the present invention Mn0 and Mp0 be connected in parallel.As can be seen from Figure 6, than the NMOS varactor in Fig. 5 and the C-V characteristic curve of PMOS varactor, it is smooth many that the C-V characteristic curve of variable capacitance of the present invention is wanted, and therefore, the variable capacitance of this structure is more suitable for being applied in digital controlled oscillator 101.
The high frequency pure oscillation signal that level switch module 102 is mainly used in that digital controlled oscillator 101 is exported is converted to the square-wave signal of single-ended mode output, so that the processing of subsequent conditioning circuit.Level switch module 102 can comprise: the first conversion submodule and the second conversion submodule.The high frequency pure oscillation signal that the first conversion submodule is mainly used in digital controlled oscillator 101 to export is converted to single-ended mode sinusoidal signal, and exports this single-ended mode sinusoidal signal to the second conversion submodule; The single-ended mode sinusoidal signal that the second conversion submodule is mainly used in being received is converted to the square-wave signal of single-ended mode output.Level switch module 102 also can adopt alternate manner to realize the conversion of signal.
The square-wave signal that programmable frequency divider 103 is mainly used according to predetermined frequency dividing ratio, level switch module 102 being exported carries out down conversion process, obtains having the clock signal of preset frequency, and to duty-ratio calibrating circuit 104 these clock signals of output.Programmable frequency divider 103 can adopt the programmable frequency divider of tandem type structural design.Above-mentioned predetermined frequency dividing ratio can be stored in programmable frequency divider 103, and this predetermined frequency dividing ratio can be according to the frequency shift of required clock signal, be the clock signal that the present invention can make externally to provide without crystal oscillator cmos clock generation circuit by changing the size of predetermined frequency dividing ratio different frequency, and the performance of clock signal can not change.
Duty-cycle correction circuit 104 is mainly used in adjusting the duty ratio of its clock signal receiving, make the duty ratio of clock signal meet the requirement of predetermined clock duty ratio, and the clock signal of output duty cycle after adjusting, thereby provide high-precision clock signal for other element in electronic equipment.Above-mentioned predetermined clock duty ratio require can be a concrete numerical value as 50%, and predetermined clock duty ratio requires can be stored in duty-cycle correction circuit 104.
Frequency Locking module 105 mainly plays a role in the process of Frequency Locking control information that digital controlled oscillator 101 is set, and after successfully having arranged, Frequency Locking module 105 can no longer work on.Arranging in the process of Frequency Locking control information, Frequency Locking module 105 is mainly used in receiving the output signal of external crystal-controlled oscillation and the output signal of programmable frequency divider, and determine both difference on the frequency, thereby produce Frequency Locking control information (also can be called control word) according to this difference on the frequency, and this Frequency Locking control information is stored in non-volatility memorizer 106, be that Frequency Locking module 105 is compared by clock signal and high-precision clock signal that programmable frequency divider 103 is exported, to establish one group of suitable control word, this control word can be controlled the variable capacitance of choosing digital controlled oscillator 101, thereby ensure that crystal oscillator cmos clock produces circuit the clock signal of high stability can be externally provided.
The operation that Frequency Locking module 105 of the present invention is carried out can just be carried out before the formal use of chip that produces circuit place without crystal oscillator cmos clock, realizes disposable calibration.So after calibration is complete, described Frequency Locking module just does not need to work again.As obtained different clock frequencies, by the size of change frequency dividing ratio, do not affect the performance of clock signal.
The operation principle of Frequency Locking module 105 of the present invention as shown in Figure 7.
In Fig. 7, the input of Frequency Locking module 105 comprises the output of programmable frequency divider 103 and the output of external crystal-controlled oscillation, and the process of Frequency Locking is by enable signal control.When produce circuit while working for the first time while dispatching from the factory (as) without crystal oscillator cmos clock, enable signal is high level, represents the process that starts to carry out frequency calibration.Echo signal in Fig. 7 is high frequency pure oscillation signal process level switch module 102 and programmable frequency divider 103 output after treatment that digital controlled oscillator 101 produces.Reference signal in Fig. 7 is the stable high accurate clock signal of external crystal-controlled oscillation output, and both carry out the height of comparison frequency through counter.The minimum frequency difference that can be identified of REF signal and CLK signal determines by the figure place of counter, and the figure place of counter is higher, and the difference on the frequency that can compare is just less, and frequency ratio resolution is just higher; Certainly, the circuit of counter also can be more complicated.Concrete frequency comparison procedure is to carry out in up-down counter in Fig. 7 and state machine.The state if the counter of CLK signal attains to a high place, and the counter of REF signal is not also reset, illustrate that the frequency ratio of CLK signal is higher, require the value of register-stored to increase, thereby increase the capacitance of the LC resonant slots in digital controlled oscillator 101, reduce frequency of oscillation; On the contrary, if the counter of REF signal is reset, and the counter of CLK signal is also at low level, the frequency ratio that CLK signal is described is lower, require the value of register-stored to reduce, thereby reduce the capacitance of the LC resonant slots in digital controlled oscillator 101, improve frequency of oscillation.Through comparison procedure several times, the frequency of last REF signal and CLK signal equates, the frequency accuracy of CLK signal is identical with the frequency accuracy of the clock signal of external crystal-controlled oscillation, thereby frequency calibration process finishes.Now, enable signal becomes low level, and the n-bit byte in register is stored in non-volatility memorizer 106.Next time, while powering on without crystal oscillator cmos clock generation circuit, the control word of the Cr group variable capacitance array in digital controlled oscillator 101 can directly be read from non-volatility memorizer 106, and Frequency Locking module 105 does not need work, has just no longer needed crystal oscillator yet.
Non-volatility memorizer 106 is mainly used in the Frequency Locking control information that storing frequencies locking module 105 is exported, thereby digital controlled oscillator 101 can be from non-volatility memorizer 106 reading frequency locking control informations.This non-volatility memorizer 106 can be specially ROM etc.
The above is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention, any those skilled in the art are not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. without a crystal oscillator cmos clock production method, it is characterized in that, the electronic equipment that is applicable to need clock signal and does not need to use crystal oscillator after the frequency calibration of clock signal, described method comprises:
Utilize digital controlled oscillator to produce high frequency pure oscillation signal;
Described high frequency pure oscillation signal is converted to the square-wave signal of single-ended mode output;
According to predetermined frequency dividing ratio, described square-wave signal is carried out to down conversion process, obtain the clock signal of preset frequency;
Adjust the duty ratio of described clock signal, make the duty ratio of described clock signal meet the requirement of predetermined clock duty ratio, the clock signal after output duty cycle is adjusted;
Wherein, variable capacitance array in described digital controlled oscillator is controlled by Frequency Locking control information, and the set-up mode of described Frequency Locking control information comprises: in the frequency calibration process of clock signal, produce Frequency Locking control information according to the difference on the frequency of the clock signal after the output signal of external crystal-controlled oscillation and described down conversion process.
Without crystal oscillator cmos clock produce a circuit, it is characterized in that, the electronic equipment that is applicable to need clock signal and does not need to use crystal oscillator after the frequency calibration of clock signal, described without crystal oscillator cmos clock produce circuit comprise:
Digital controlled oscillator, for generation of high frequency pure oscillation signal, and output;
Level switch module, is connected with described digital controlled oscillator, for described high frequency pure oscillation signal being converted to the square-wave signal of single-ended mode output;
Programmable frequency divider, is connected with described level switch module, for according to predetermined frequency dividing ratio, described square-wave signal being carried out to down conversion process, and exports the clock signal with preset frequency obtaining after down conversion process;
Duty-cycle correction circuit, is connected with described programmable frequency divider, for adjusting the duty ratio of described clock signal, makes the duty ratio of described clock signal meet the requirement of predetermined clock duty ratio, the clock signal after output duty cycle is adjusted;
Frequency Locking module, be connected with described programmable frequency divider, and arranging in the process of Frequency Locking control information, described Frequency Locking module is also connected with external crystal-controlled oscillation, for the frequency calibration process in clock signal, produce Frequency Locking control information according to the difference on the frequency of the output signal of the output signal of described external crystal-controlled oscillation and described programmable frequency divider, and output, described Frequency Locking control information is for controlling the variable capacitance array of described digital controlled oscillator;
Non-volatility memorizer, be connected respectively with described Frequency Locking module and digital controlled oscillator, for storing the Frequency Locking control information of described Frequency Locking module output, described digital controlled oscillator obtains described Frequency Locking control information from described non-volatility memorizer.
According to claim 2 without crystal oscillator cmos clock produce circuit, it is characterized in that, described digital controlled oscillator comprises: metal-oxide-semiconductor Mn1, Mn2, Mp1, Mp2 and Mp3, LC resonant slots and frequency self calibration module;
Described metal-oxide-semiconductor Mn1, Mn2, Mp1 and Mp2 form cross-coupling unit, are used to described LC resonant slots that negative resistance energy is provided;
Described metal-oxide-semiconductor Mp3 is connected with described cross-coupling unit, is used to described cross-coupling unit that biasing tail current is provided;
Described LC resonant slots comprises: inductance, fixed capacity and two groups of variable capacitance arrays, and described inductance, fixed capacity and two groups of variable capacitance arrays are connected with described cross-coupling unit respectively, wherein one group of variable capacitance array is controlled by frequency self calibration module, and another group variable capacitance array is controlled by described Frequency Locking control information.
4. according to claim 3ly produce circuit without crystal oscillator cmos clock, it is characterized in that, described frequency self calibration module comprises: temperature sensor and connected analog to digital converter, and described analog to digital converter is connected with described cross-coupling unit.
According to claim 3 without crystal oscillator cmos clock produce circuit, it is characterized in that, every group of variable capacitance array includes multiple variable-capacitance unit, and each variable-capacitance unit includes: a variable capacitance and a connected switching tube.
According to claim 5 without crystal oscillator cmos clock produce circuit, it is characterized in that, described variable capacitance comprises: N-type MOS varactor and P type MOS varactor, and described N-type MOS varactor and the parallel connection of P type MOS varactor.
According to described in claim 3 or 4 or 5 or 6 without crystal oscillator cmos clock produce circuit, it is characterized in that, described digital controlled oscillator also comprises: amplitude detection unit and common mode feedback unit, and described amplitude detection unit and common mode feedback unit are respectively with described cross-coupling unit and connect.
According to described in claim 2 or 3 or 4 or 5 or 6 without crystal oscillator cmos clock produce circuit, it is characterized in that, described level switch module comprises:
The first conversion submodule, for being converted to single-ended mode sinusoidal signal by the high frequency pure oscillation signal of digital controlled oscillator output;
The second conversion submodule, for being converted to described single-ended mode sinusoidal signal the square-wave signal of single-ended mode output.
9. according to producing circuit without crystal oscillator cmos clock described in claim 2 or 3 or 4 or 5 or 6, it is characterized in that, described programmable frequency divider is the programmable frequency divider that adopts tandem type structural design.
According to described in claim 2 or 3 or 4 or 5 or 6 without crystal oscillator cmos clock produce circuit, it is characterized in that, in described programmable frequency divider, store predetermined frequency dividing ratio, and the numerical value of this predetermined frequency dividing ratio can be modified; Described predetermined clock duty ratio requires to comprise: 50%.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210069285.5A CN102638247B (en) | 2012-03-16 | 2012-03-16 | Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator |
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| CN201210069285.5A CN102638247B (en) | 2012-03-16 | 2012-03-16 | Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator |
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| CN102638247A CN102638247A (en) | 2012-08-15 |
| CN102638247B true CN102638247B (en) | 2014-11-26 |
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| CN103869875B (en) * | 2012-12-11 | 2019-11-15 | 北京普源精电科技有限公司 | A kind of signal generator with clock reference source circuit |
| CN104539286B (en) * | 2014-12-10 | 2017-12-01 | 深圳市国微电子有限公司 | Base frequency clock generation circuit |
| CN106961260B (en) * | 2017-02-21 | 2019-07-09 | 西安电子科技大学 | The clock generation circuit of low-power consumption adjustable frequency, adjustable duty cycle |
| CN108134602B (en) * | 2017-12-21 | 2021-08-24 | 长鑫存储技术有限公司 | Duty ratio calibration circuit and semiconductor memory |
| CN110932723B (en) * | 2019-12-18 | 2023-05-16 | 上海磐启微电子有限公司 | Crystal oscillator-free wireless receiving and transmitting system |
| CN113900084B (en) * | 2021-09-06 | 2022-06-28 | 珠海正和微芯科技有限公司 | Crystal-oscillator-free FMCW radar transceiver system and frequency calibration method |
| CN113933791B (en) * | 2021-09-06 | 2022-05-27 | 珠海正和微芯科技有限公司 | Crystal-oscillator-free FMCW radar transceiver device and frequency calibration method |
| CN116996045A (en) * | 2022-04-26 | 2023-11-03 | 长鑫存储技术有限公司 | Signal generator and memory |
| US11703905B1 (en) | 2022-04-26 | 2023-07-18 | Changxin Memory Technologies, Inc. | Clock generation circuit, equidistant four-phase signal generation method, and memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150354A (en) * | 1995-11-13 | 1997-05-21 | 财团法人工业技术研究院 | Full-digital phase-locked loop |
| CN1832333A (en) * | 2006-04-14 | 2006-09-13 | 清华大学 | CMOS digital control LC oscillator on chip |
| CN202495917U (en) * | 2012-03-16 | 2012-10-17 | 安徽大学 | CMOS clock generating circuit without using crystal oscillator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005007310B3 (en) * | 2004-12-23 | 2006-02-02 | Texas Instruments Deutschland Gmbh | Integrated CMOS-clock-pulse generator, uses oscillator selection circuit to control switches to select oscillator in first or second oscillator block |
-
2012
- 2012-03-16 CN CN201210069285.5A patent/CN102638247B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150354A (en) * | 1995-11-13 | 1997-05-21 | 财团法人工业技术研究院 | Full-digital phase-locked loop |
| CN1832333A (en) * | 2006-04-14 | 2006-09-13 | 清华大学 | CMOS digital control LC oscillator on chip |
| CN202495917U (en) * | 2012-03-16 | 2012-10-17 | 安徽大学 | CMOS clock generating circuit without using crystal oscillator |
Non-Patent Citations (4)
| Title |
|---|
| 一种基于FPGA实现的全数字锁相环;庞浩等;《自动化与仪器仪表》;20050531;第28页至第30页 * |
| 基于FPGA的全数字锁相环的设计;王文理等;《电子设计工程》;20090131;第17卷(第1期);第39页至第43页 * |
| 庞浩等.一种基于FPGA实现的全数字锁相环.《自动化与仪器仪表》.2005,第28页至第30页. * |
| 王文理等.基于FPGA的全数字锁相环的设计.《电子设计工程》.2009,第17卷(第1期),第39页至第43页. * |
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