CN102637719A - Semiconductor structure and preparation method of semiconductor structure - Google Patents
Semiconductor structure and preparation method of semiconductor structure Download PDFInfo
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- CN102637719A CN102637719A CN2011100355700A CN201110035570A CN102637719A CN 102637719 A CN102637719 A CN 102637719A CN 2011100355700 A CN2011100355700 A CN 2011100355700A CN 201110035570 A CN201110035570 A CN 201110035570A CN 102637719 A CN102637719 A CN 102637719A
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Abstract
The invention relates to a semiconductor structure and a preparation method of the semiconductor structure and belongs to the field of a semiconductor device. The semiconductor structure comprises a semiconductor substrate, an epitaxial layer, a first diffusion region, an oxidation layer, a polycrystalline silicon layer and an insulation layer, wherein the semiconductor substrate has the first semiconductor type, the epitaxial layer is covered on the surface of the semiconductor substrate, the first diffusion region is positioned in the epitaxial layer and has the second semiconductor type, the oxidation layer is arranged on the surface of the first diffusion surface, and in addition, the surface of the oxidation layer is basically aligned with the surface of the epitaxial layer, the polycrystalline silicon layer is positioned on the surface of the epitaxial layer and covers the partial oxidation layer surface, the partial epitaxial layer surface and the exposed first diffusion surface, and the insulation layer is positioned on the exposed oxidation layer surface, the exposed epitaxial surface and the polycrystalline silicon layer surface. Through the adoption of the RESURF technology, a low-doping first doping region is arranged in the semiconductor structure, and during the PN junction reverse deflection, the PN junction can realize the uniform load bearing through the RESURF technology. In addition, the thick oxidation layer can also be used for effectively improving the breakdown voltage of the PN junction. Meanwhile, the semiconductor structure provided by the invention has the advantages that the structure is simple, and the process is simple and convenient.
Description
Technical field
The present invention relates to a kind of semiconductor structure, be specifically related to the structure of guard ring, belong to technical field of semiconductors.
Background technology
Modern high-voltage power semiconductor device is owing to its operating frequency is high, fast, the high application that obtains more and more widely of control efficiency of switching speed; But because semiconductor technology adopts the plane terminal structure; The degree of depth of knot is more shallow, the knot curved edge makes withstand voltage reduction, poor stability, and device is destroyed easily.In order to improve device withstand voltage and withstand voltage stability, taking measures at the device boundaries place usually is that the terminal protection technology reduces surface field intensity, improves the puncture voltage of power device PN junction.
Terminal structure commonly used has following several kinds: field plate (Field Plate; FP), field limiting ring (FieldLimiting Ring; FLR), the knot termination extension (Junction Termination Extention, JTE) with horizontal varying doping (Variation of Lateral Doping, VLD).Wherein, FP and FLR are applicable to the device that current vertical flows to, and make it to have big current handling capability and big current gain, and the two is used in combination and effectively suppresses the electric field that main knot edge curvature effect causes constantly and concentrate; Thereby provide withstand voltage, and with the low-voltage ic process compatible.
Fig. 1 is planar device field limiting ring structure sketch map commonly used.As shown in Figure 1, growth one deck epitaxial loayer 102 on the Semiconductor substrate with first semiconductor type 101; Form 1 main knot 103 and a plurality of field limiting rings 104 on epitaxial loayer 102 surfaces with second semiconductor type; Main knot 103 has doped region 105 with field limiting ring 104 surfaces; Doped region 105 has identical diffusion depth and doping content, and main knot 103 is accomplished diffusion at one time with field limiting ring 104 on technology; Deposited oxide layer 106 and field plate 107 successively on the surface of main knot 103 and field limiting ring 104, and field plate 107, oxide layer 106 have constituted the MIS structure with epitaxial loayer 102; When adding reversed bias voltage for main knot 103; The depletion region of main knot 103 also increases thereupon, outwards expansion, and the MIS structure also is in spent condition; Increase to when voltage before the avalanche breakdown voltage of main knot; The depletion region of main knot 103 and the depletion region of field limiting ring 104 converge, and the two is in pass-through state, and this moment, field limiting ring 104 played the effect of dividing potential drop.
In field limiting ring structure; Between the doping content that needs strict controlled doping district and diffusion depth and main knot and the field limiting ring or the length of the spacing between the adjacent field limiting ring, field plate, thickness of oxide layer etc., so bring difficulty can for structural design, analog simulation.
Summary of the invention
The technical problem that the present invention will solve provides a kind of semiconductor structure, improves the puncture voltage of PN junction, thereby improves the puncture voltage of whole PN junction, improves the performance of entire device, and structure and processing step are simple.
For solving the problems of the technologies described above, semiconductor structure provided by the invention comprises: the Semiconductor substrate with first semiconductor type; Cover the epitaxial loayer of semiconductor substrate surface; Be positioned at first diffusion region with second semiconductor type of epitaxial loayer; Oxide layer on surface, first diffusion region, and remain basically stable with epi-layer surface in its surface; Be positioned at the polysilicon layer of epi-layer surface, and cover part oxide layer surface, part epi-layer surface and the surface, first diffusion region that exposes; And the insulating barrier that is positioned at the oxide layer surface that exposes, the epi-layer surface that exposes and polysilicon layer surface.
In the semiconductor structure provided by the invention, polysilicon layer cover part epi-layer surface, surface, whole first diffusion region and partial oxidation laminar surface, and the dimension D 2 of polysilicon layer capping oxidation laminar surface is 30 microns to 50 microns.The dimension D 1 that polysilicon layer covers surface, first diffusion region and part epi-layer surface is 5 microns to 10 microns.
In the semiconductor structure provided by the invention, first diffusion region injects through diffusion or low energy ion and the high temperature propelling forms, and its doping content is 2E11cm
-3To 3E11cm
-3, its degree of depth is 5 microns to 10 microns.Oxide layer forms through thermal oxidation, and its dielectric material is a silicon dioxide, and its thickness of oxide layer is 2 microns to 3 microns.Polysilicon layer is through the chemical gas-phase deposition method deposition, and its thickness is 0.4 micron to 0.8 micron.Insulating barrier adopts the thermal oxide growth method to form, and its dielectric material is any one among silicon dioxide, silicon nitride, silicon oxynitride, carbon containing Si oxide, the tetraethoxysilane TEOS, and its thickness is 1..5 micron to 2.5 micron.
As the preferred technique scheme, first semiconductor type is the N type, and second semiconductor type is the P type.
As optional technical scheme, first semiconductor type is the P type, and second semiconductor type is the N type.
The present invention also provides a kind of preparation method of above-mentioned semiconductor structure, in order to improving the puncture voltage on PN junction surface, thereby improves the puncture voltage of whole PN junction, improves the durability of device, thereby improves device performance, and its step comprises:
(1) Semiconductor substrate is provided, and at the semiconductor substrate surface grown epitaxial layer;
(2) doping forms first doped region in epitaxial loayer;
(3) in the first doped region superficial growth oxide layer;
(4) at epi-layer surface deposit spathic silicon layer, and polysilicon layer covers first doped region surface, partial oxidation laminar surface and part epi-layer surface;
(5) at the oxide layer surface that exposes, epi-layer surface and polysilicon layer surface deposition one insulating barrier that exposes.
Among the semiconductor structure preparation method provided by the invention, first diffusion region injects through diffusion or low energy ion and the high temperature propelling forms, and its doping content is 2E11cm
-3To 3E11cm
-3, its degree of depth is 5 microns to 10 microns; Oxide layer adopts the thermal oxidation process growth, and its dielectric material is a silicon dioxide, and its thickness is 2 microns to 3 microns; Polysilicon layer is through CVD method deposition; Its thickness is 0.4 micron to 0.8 micron; And it is 30 microns to 50 microns that said polysilicon layer capping oxidation laminar surface is of a size of D2, and the dimension D 1 that polysilicon layer covers surface, first diffusion region and part epi-layer surface is 5 microns to 10 microns; The deposition of insulating barrier adopts thermal oxide growth, 1.5 microns to 2.5 microns of its thickness, the dielectric material of insulating barrier be among silicon dioxide, silicon nitride, silicon oxynitride, carbon containing silicon oxynitride, the tetraethoxysilane TEOS any one.
Among the semiconductor structure preparation method provided by the invention, the formation of the growth of epitaxial loayer, oxide layer, insulating barrier and the preparation of polysilicon layer all adopt the standard normal semiconductor technology to realize.In this preparation method, the doping content of Semiconductor substrate is greater than the doping content of epitaxial loayer, and first doped region is a lightly doped region, and its doping way is diffusion or low energy ion injection, and advances formation through high temperature.
As the preferred technique scheme, first semiconductor type is the N type, and second semiconductor type is the P type.
As optional technical scheme, first semiconductor type is the P type, and second semiconductor type is the N type.
Technique effect of the present invention is through using the RESURF technology, the first low-doped doped region being set in semiconductor structure, and when PN junction was anti-inclined to one side, the RESURF technology made evenly pressure-bearing of PN junction.In the semiconductor structure that the present invention proposes, increased oxide layer, and oxide layer is thicker, also can effectively improve puncture voltage.Simultaneously, the semiconductor structure that proposes among the present invention, simple in structure, technology is easy, has simplified designs, emulation and making greatly.
Description of drawings
Fig. 1 is planar device field limiting ring structure sketch map commonly used;
Fig. 2 is a semiconductor structure cross-sectional view provided by the invention;
Fig. 3 is a semiconductor structure preparation method flow chart provided by the invention;
Fig. 4 a～Fig. 4 e is a semiconductor structure preparation method processing step structural representation provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, the present invention is made further detailed description below in conjunction with accompanying drawing.
Fig. 2 is a semiconductor structure cross-sectional view provided by the invention.
As shown in Figure 2, semiconductor structure 200 comprises: the Semiconductor substrate 201 with first semiconductor type; Cover the epitaxial loayer 202 on Semiconductor substrate 201 surfaces; Be positioned at first diffusion region 206 with second semiconductor type of epitaxial loayer 202; Oxide layer 207 on 206 surfaces, first diffusion region, remain basically stable with epi-layer surface in its surface; Be positioned at the polysilicon layer 208 on epitaxial loayer 202 surface, and polysilicon layer 208 also cover part oxide layer 207 surfaces and 206 surfaces, said first diffusion region that expose; And the insulating barrier 209 that covers oxide layer 207 surfaces that expose, epitaxial loayer 202 surfaces that expose and polysilicon layer 208 surfaces.
In the semiconductor structure provided by the invention, the dimension D 2 on polysilicon layer 208 capping oxidation layers 207 surface is 30 microns to 50 microns, and the dimension D 1 that polysilicon layer 208 covers 206 surfaces, first diffusion region and part epitaxial loayer 202 surfaces is 5 microns to 10 microns.
In this embodiment, first diffusion region 206 of semiconductor structure 200 advances formation through spreading perhaps low energy ion injection and high temperature, and its doping content is 2E11cm
-3To 3E11cm
-3, its degree of depth is 5 microns to 10 microns; Oxide layer 207 forms through thermal oxidation, and its dielectric material is a silicon dioxide, and its thickness is 2 microns to 3 microns; Polysilicon layer 208 is through the chemical gas-phase deposition method deposition, and its thickness is 0.4 micron to 0.8 micron; Insulating barrier 209 adopts the thermal oxide growth method to form, and its dielectric material is any one among silicon dioxide, silicon nitride, silicon oxynitride, carbon containing Si oxide, the tetraethoxysilane TEOS, and its thickness is 1.5 microns to 2.5 microns.
As most preferred embodiment, semiconductor type is the N type.That is: the epitaxial loayer 202 that epitaxial growth one N-mixes on the Semiconductor substrate 201 that N+ mixes; In epitaxial loayer 202, pass through first diffusion region 206 that diffusion or low energy ion injection and high temperature advance formation P-to mix, surperficial in first diffusion region 206 through thermal oxidation process growth oxide layers 207; At epitaxial loayer 202 surface coverage polysilicon layers 208, and polysilicon layer 208 also cover part oxide layer 207 surfaces and 206 surfaces, first diffusion region that expose; And cover expose the insulating barrier 209 on oxide layer 207 surfaces, epitaxial loayer 202 surfaces that expose and polysilicon layer 208 surfaces.
As another embodiment, semiconductor type is the P type.That is: the epitaxial loayer 202 that epitaxial growth one P-mixes on the Semiconductor substrate 201 that P+ mixes; In epitaxial loayer 202, pass through first diffusion region 206 that diffusion or low energy ion injection and high temperature advance formation N-to mix, surperficial in first diffusion region 206 through thermal oxidation process growth oxide layers 207; At epitaxial loayer 202 surface coverage polysilicon layers 208, and polysilicon layer 208 also cover part oxide layer 207 surfaces and 206 surfaces, first diffusion region that expose; And the insulating barrier 209 that covers oxide layer 207 surfaces that expose, the epitaxial loayer that exposes 202 surfaces and polysilicon layer 208 surfaces.
Parameter as most preferred embodiment is selected, and in the semiconductor structure 200, the dimension D 2 on polysilicon layer 208 capping oxidation layers 207 surface is 40 microns, and the dimension D 1 that polysilicon layer 208 covers 206 surfaces, first diffusion region and part epitaxial loayer 202 surfaces is 6 microns; The doping content of first diffusion region 206 is 2.5E11cm
-3, its thickness is 6 microns; The dielectric material of oxide layer 207 is a silicon dioxide, and its thickness is 2.5 microns; The thickness of polysilicon layer 208 is 0.5 micron; The dielectric material of insulating barrier 209 is a tetraethoxysilane, and its thickness is 2 microns.
This embodiment also provides a kind of preparation method of semiconductor structure, the semiconductor structure preparation method flow chart that Fig. 3 provides for this embodiment.
In this embodiment, the preparation method of semiconductor structure 200 may further comprise the steps:
Step 1 provides Semiconductor substrate 201, and at Semiconductor substrate 201 superficial growths one epitaxial loayer 202.
In this step, shown in Fig. 4 a, related Semiconductor substrate 201 and epitaxial loayer 202 are identical semiconductor type and mix, and wherein, epitaxial loayer 202 is positioned at Semiconductor substrate 201 surfaces, and the doping content of Semiconductor substrate 201 is higher than the doping content of epitaxial loayer 202.
Step 2 spreads in epitaxial loayer 202 or low energy ion injects and high temperature advances, and forms first doped region 206.
In this step, shown in Fig. 4 b, on epitaxial loayer 202 surfaces deposition of silica and silicon nitride layer successively, and spread as mask or low energy ion injects and high temperature advances with this, form first doped region 206, its doping content is 2E11cm
-3To 3E11cm
-3, its degree of depth is 5 microns to 10 microns, removes silicon dioxide and silicon nitride layer as mask at last.
Step 3 is passed through thermal oxidation process growth oxide layer 207 on first doped region, 206 surfaces.
In this step, shown in Fig. 4 c, at epitaxial loayer 202 surface deposition silicon nitride layers, adopt thermal oxidation process growth oxide layer 207, the thickness of oxide layer 207 is removed the silicon nitride layer as mask at last less than the degree of depth of first doped region 206.The dielectric material of oxide layer 207 is a silicon dioxide, and its thickness is 2 microns to 3 microns.
Step 4, at epitaxial loayer 202 surface deposition polysilicon layers 208, and polysilicon layer 208 also cover part oxide layer 207 surfaces and 206 surfaces, first diffusion region that expose.
In this step, shown in Fig. 4 d, polysilicon layer 208 adopts lithographic method to remove unnecessary polysilicon through the chemical gas-phase deposition method deposition, and the thickness of this polysilicon layer 208 is 0.4 micron to 0.8 micron.The dimension D 2 of polysilicon layer 208 capping oxidation laminar surfaces is 30 microns to 50 microns, and the dimension D 1 that polysilicon layer 208 covers 206 surfaces, first diffusion region and part epitaxial loayer 202 surfaces is 5 microns to 10 microns.
Step 5 is on exposed oxide layer 207 surfaces and polysilicon layer 208 surface deposition insulating barriers 209.
In this step, shown in Fig. 4 e, insulating barrier 209 adopts the thermal oxide growth method to form, and its thickness is 1.5 microns to 2.5 microns.As optimal technical scheme, the dielectric material of insulating barrier 209 be among silicon dioxide, silicon nitride, silicon oxynitride, carbon containing silicon oxynitride, the tetraethoxysilane TEOS any one.
As the preferred technique scheme, first semiconductor type is the N type, and second semiconductor type is the P type.
As optional technical scheme, first semiconductor type is the P type, and second semiconductor type is the N type.
In embodiment, through using the RESURF technology, the first low-doped doped region is set in semiconductor structure, when PN junction was anti-inclined to one side, the RESURF technology made evenly pressure-bearing of PN junction.In the semiconductor structure that the present invention proposes, increased oxide layer, and oxide layer is thicker, also can effectively improve puncture voltage.Simultaneously, the semiconductor structure that proposes among the present invention, simple in structure, technology is easy, has simplified designs, emulation and making greatly.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the specific embodiment described in the specification.
Claims (16)
1. semiconductor structure comprises:
Semiconductor substrate has first semiconductor type and mixes;
The epitaxial loayer that first semiconductor type mixes is positioned at said semiconductor substrate surface;
It is characterized in that, also comprise:
First diffusion region has second semiconductor type and mixes, and is positioned at said epitaxial loayer;
Oxide layer is located in said first diffusion region, and remains basically stable with said epi-layer surface in its surface;
Polysilicon layer, said oxide layer surface, cover part, the said epi-layer surface of part and the surface, said first diffusion region that exposes;
And insulating barrier, cover the said oxide layer surface that exposes, the said epi-layer surface that exposes and said polysilicon layer surface.
2. semiconductor structure according to claim 1; It is characterized in that; Said polysilicon layer covers said oxide layer surface and is of a size of 30 microns to 50 microns, and said polysilicon layer covers said surface, first diffusion region and the said epi-layer surface of part is of a size of 5 microns to 10 microns.
3. semiconductor structure according to claim 1 is characterized in that, the doping content of said first doped region is 2E11cm
-3To 3E11cm
-3, the degree of depth that the ion of said first doped region injects after the also high temperature propelling is 5 microns to 10 microns.
4. semiconductor structure according to claim 1 is characterized in that, the dielectric material of said oxide layer is a silicon dioxide, and said thickness of oxide layer is 2 microns to 3 microns.
5. semiconductor structure according to claim 1 is characterized in that, the thickness of said polysilicon layer is 0.4 micron to 0.8 micron.
6. semiconductor structure according to claim 1; It is characterized in that; The dielectric material of said insulating barrier is any one among silicon dioxide, silicon nitride, silicon oxynitride, carbon containing Si oxide, the tetraethoxysilane TEOS, and the thickness of said insulating barrier is 1.5 microns to 2.5 microns.
7. according to any described semiconductor structure of claim 1-6, it is characterized in that said first semiconductor type is the N type, said second semiconductor type is the P type.
8. according to any described semiconductor structure of claim 1-6, it is characterized in that said first semiconductor type is the P type, said second semiconductor type is the N type.
9. the preparation method of a semiconductor structure as claimed in claim 1, its step comprises:
(1) semi-conductive substrate is provided, and at said semiconductor substrate surface grown epitaxial layer;
(2) doping forms said first doped region in said epitaxial loayer;
(3) in the said oxide layer of the said first doped region superficial growth;
(4) at said epi-layer surface deposit spathic silicon layer, and said polysilicon layer covers said first doped region surface, part said oxide layer surface and the said epi-layer surface of part;
(5) at the said oxide layer surface that exposes, the said epi-layer surface that exposes and the said insulating barrier of how said crystal silicon layer surface deposition.
10. semiconductor structure preparation method according to claim 9; It is characterized in that; Said polysilicon covers said oxide layer surface and is of a size of 30 microns to 50 microns, and said polysilicon layer covers said surface, first diffusion region and the said epi-layer surface of part is of a size of 5 microns to 10 microns.
11. semiconductor structure preparation method according to claim 9 is characterized in that, said first doped region injects through diffusion or ion and the high temperature propelling forms, and the doping content of said first doped region is 2E11cm
-3To 3E11cm
-3, its degree of depth is 5 microns to 10 microns.
12. semiconductor structure preparation method according to claim 9 is characterized in that, said oxide layer forms through thermal oxidation process, and the dielectric material of said oxide layer is a silicon dioxide, and said thickness of oxide layer is 2 microns to 3 microns.
13. semiconductor structure preparation method according to claim 9 is characterized in that, said polysilicon layer forms through chemical gas-phase deposition method, and the thickness of said polysilicon layer is 0.4 micron to 0.8 micron.
14. semiconductor structure preparation method according to claim 9; It is characterized in that; Said insulating barrier adopts the thermal oxide growth method to form; Its thickness is 1.5 microns to 2.5 microns, and its dielectric material is any one among silicon dioxide, silicon nitride, silicon oxynitride, carbon containing Si oxide, the tetraethoxysilane TEOS.
15. according to any described semiconductor structure of claim 9-14, it is characterized in that said first semiconductor type is the N type, said second semiconductor type is the P type.
16. according to any described semiconductor structure of claim 9-14, it is characterized in that said first semiconductor type is the P type, said second semiconductor type is the N type.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115513172A (en) * | 2022-11-22 | 2022-12-23 | 广东芯粤能半导体有限公司 | Semiconductor structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5003372A (en) * | 1988-06-16 | 1991-03-26 | Hyundai Electronics Industries Co., Ltd. | High breakdown voltage semiconductor device |
| US20100171149A1 (en) * | 2009-01-06 | 2010-07-08 | Texas Instruments Incorporated | Symmetrical bi-directional semiconductor esd protection device |
| US20100181596A1 (en) * | 2009-01-19 | 2010-07-22 | Satoshi Suzuki | Semiconductor device and manufacturing method thereof |
-
2011
- 2011-02-10 CN CN2011100355700A patent/CN102637719A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5003372A (en) * | 1988-06-16 | 1991-03-26 | Hyundai Electronics Industries Co., Ltd. | High breakdown voltage semiconductor device |
| US20100171149A1 (en) * | 2009-01-06 | 2010-07-08 | Texas Instruments Incorporated | Symmetrical bi-directional semiconductor esd protection device |
| US20100181596A1 (en) * | 2009-01-19 | 2010-07-22 | Satoshi Suzuki | Semiconductor device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115513172A (en) * | 2022-11-22 | 2022-12-23 | 广东芯粤能半导体有限公司 | Semiconductor structure and preparation method thereof |
| CN115513172B (en) * | 2022-11-22 | 2023-04-28 | 广东芯粤能半导体有限公司 | Semiconductor structure and preparation method thereof |
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