CN102629192A - Instruction packet for on-chip multi-core concurrent multithreaded processor and operation method of instruction packet - Google Patents
Instruction packet for on-chip multi-core concurrent multithreaded processor and operation method of instruction packet Download PDFInfo
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- CN102629192A CN102629192A CN2012101171107A CN201210117110A CN102629192A CN 102629192 A CN102629192 A CN 102629192A CN 2012101171107 A CN2012101171107 A CN 2012101171107A CN 201210117110 A CN201210117110 A CN 201210117110A CN 102629192 A CN102629192 A CN 102629192A
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Abstract
The invention discloses an instruction packet for an on-chip multi-core concurrent multithreaded processor and an operation method of the instruction packet. According to the instruction packet for the on-chip multi-core concurrent multithreaded processor and the operation method of instruction packet, an innovative hardware system is utilized, only one on-chip multi-core processor is required by the system, and functions of a central processing unit (CPU) and a general-purpose graphics processing unit (GPGPU) can be replaced by the processor. The on-chip multi-core processor is located in a chip and integrates a plurality of processor cores which have the same structure and functions, and the system can also be defined as a homogeneous multi-core system. Besides, each of the processor cores is one concurrent multithreaded processor in itself. The instruction packet for the on-chip multi-core concurrent multithreaded processor and the operation method of the instruction packet have the advantages of being low in power consumption and in cost.
Description
Technical field
The invention belongs to field of computer technology, relate to a kind of instruction bag and method of operating thereof that is used for the concurrent multiline procedure processor of chip multi-core.
Background technology
In general, program all is that serial is carried out, and for improving the travelling speed of serial program, need do the optimization of parallel computation to the slower neck portion of this program operation speed.That is to say that the serial program of a script through after the optimization of parallel computation, can become the parallel program of mixing of a serial.
For carrying out the parallel program of mixing of serial described above, the desktop systems of main flow is to form so at present, and is as shown in Figure 1.Can find out that this system needs at least 1 CPU and at least 1 GPGPU.There is the shortcoming that power consumption is high, cost is high in this configuration for embedded system.
Summary of the invention
For overcoming the above-mentioned shortcoming that exists in the prior art, the present invention adopts a kind of hardware system of innovation, and this system only needs 1 chip multi-core processor, and this processor can replace the function of CPU and GPGPU.This chip multi-core processor is in a chip, the integrated the same processor cores of a plurality of 26S Proteasome Structure and Functions, and this system is also referred to as the isomorphism multiple nucleus system.And; Each processor core itself all is a concurrent multiline procedure processor (Simultaneous multithreading); Can be used for the concurrent multiline procedure processor of chip multi-core, realize to a plurality of hardware threads of a plurality of processor cores unlatching, control function such as close.
For carrying out the parallel program of mixing of serial described above, this chip multi-core processor need be supported a kind of like this application scenario.In this application scenario, need at least 1 thread as main thread, the Serial Control part in this main thread executive routine is used for replacing the function of the CPU in the desktop systems; Need a plurality of threads as branch's thread, the parallel computation part in these branch's thread executive routines is used for replacing the function of the GPGPU in the desktop systems.
The present invention proposes a kind of instruction bag that is used for the concurrent multiline procedure processor of chip multi-core, can let chip multi-core processor support above-mentioned application scenario.
Its technical scheme is:
A kind of instruction bag that is used for the concurrent multiline procedure processor of chip multi-core is made up of inclusion, bag tail,
Said inclusion is made up of many instructions, and said instruction is an ordinary instruction;
Said bag tail is made up of many instructions, and said instruction is a special instruction, comprises that the current thread condition wakes instruction, subject thread PC instruction, subject thread activation instruction, current thread dormancy instruction up.
Said instruction bag also comprises packet header.
Said current thread dormancy instruction is 1.
A kind of method of operating of instruction bag of the present invention may further comprise the steps:
1) main thread operation;
2) main thread activates branch's thread, then, and the main thread dormancy;
3) branch's thread operation;
4) branch's thread dormancy, because the dormancy of branch's thread, main thread can be waken up by condition.
Consisting of of the bag tail of the bag of instruction step 2):
The current thread condition is waken instruction up: 1 or many
Subject thread PC instruction: 1 or many
Subject thread activation instruction: 1 or many
Current thread dormancy instruction: 1.
Consisting of of the bag tail of the bag of instruction described in the step 4):
The current thread condition is waken instruction up: 0
Subject thread PC instruction: 0
Subject thread activation instruction: 0
Current thread dormancy instruction: 1.
Compared with prior art, beneficial effect of the present invention is:
The present invention adopts a kind of hardware system of innovation, and this system only needs 1 chip multi-core processor, and this processor can replace the function of CPU and GPGPU.This chip multi-core processor is in a chip, the integrated the same processor cores of a plurality of 26S Proteasome Structure and Functions, and this system is also referred to as the isomorphism multiple nucleus system.And; Each processor core itself all is a concurrent multiline procedure processor (Simultaneous multithreading); Can be used for the concurrent multiline procedure processor of chip multi-core, realize to a plurality of hardware threads of a plurality of processor cores unlatching, control function such as close.Technical scheme of the present invention has advantage low in energy consumption, that cost is low.
Description of drawings
The composition synoptic diagram of the desktop systems of Fig. 1 CPU+GPGPU;
The composition synoptic diagram of the concurrent multiline procedure processor of the chip multi-core system that Fig. 2 the present invention uses;
Fig. 3 instruct the bag structural drawing;
Fig. 4 current thread condition is waken the instruction synoptic diagram up, wherein: Opcode: operational code, CID: the ID of processor core number, TID: the Thread Id of the processor core that points to by CID number, Reserve: keep the position;
Fig. 5 subject thread PC instructs synoptic diagram, wherein Opcode: operational code, ADDR: address;
Fig. 6 subject thread activation instruction synoptic diagram, wherein Opcode: operational code, CID: the ID of processor core number, TID: the Thread Id of the processor core that points to by CID number, Reserve: keep the position;
Fig. 7 current thread dormancy instruction synoptic diagram, wherein Opcode: operational code, Reserve: keep the position;
Fig. 8 main thread, branch's thread operation synoptic diagram.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done explanation in further detail.
The present invention is a kind of, and to be used for the structure of instruction bag of the concurrent multiline procedure processor of chip multi-core as shown in Figure 3.This instruction bag is made up of many ordinary instruction and many special instructions.Special instruction wherein is a key of the present invention.
The instruction bag is made up of inclusion, bag tail.
Inclusion is made up of many instructions, and these instructions are ordinary instruction.
The bag tail is made up of many instructions, and these instructions are special instructions, also are the key instructions that the present invention proposes.
Packet header can have also and can not have, and can determine as required.The legend here is not have packet header.
Inclusion is made up of many ordinary instruction, and these ordinary instruction are instructions that general processor often has, arithmetic operation instruction for example, and the internal storage access instruction, condition jump instruction or the like, these ordinary instruction and the present invention have nothing to do.
The bag tail is made up of being described below of every kind of special instruction many special instructions:
The current thread condition is waken instruction up, and is as shown in Figure 4:
Opcode: operational code is the unique identifier of this instruction of sign.
CID: the ID of processor core number.
TID: the Thread Id of the processor core that is pointed to by CID number adopts solely heat sign indicating number coding.
Reserve: keep the position.
This instruction list has been shown and has waken current thread up, needs which subject thread (non-current thread) to give and deserves preceding thread transmission interruption.For example:, so, need two should instruct: the CID=0x1 of article one instruction, TID=0x6 if subject thread is to examine 1 thread 2,3 and examine 2 thread 3,4; The CID=0x2 of second instruction, TID=0x18.
In instruction bag, this instruction can be zero bar or many.
Subject thread PC instruction, as shown in Figure 5:
Opcode: operational code is the unique identifier of this instruction of sign.
PC: an address is set, and after subject thread was activated, subject thread can begin from this address to read and execute instruction.
In instruction bag, this instruction can be zero bar or many.
The subject thread activation instruction, as shown in Figure 6:
Opcode: operational code is the unique identifier of this instruction of sign.
CID: the ID of processor core number.
TID: the Thread Id of the processor core that is pointed to by CID number, adopt solely heat sign indicating number coding.
Reserve: keep the position.
This instruction expression activates which thread in which processor core, after this thread is activated, just reads since an address and execute instruction, and this address is to be instructed by subject thread PC before to be provided with.
In instruction bag, this instruction can be zero bar or many.
Current thread dormancy instruction, as shown in Figure 7:
Opcode: operational code is the unique identifier of this instruction of sign.
Reserve: keep the position.
This instruction expression can let current process get into dormant state, after getting into dormant state, has only other threads can wake it up.Wake its condition up, wake instruction up by current thread condition before and be provided with.
In the instruction bag, this instruction has and only has one.
Next, how description should use this instruction bag, reaches the effect of the parallel combination process of operation serial.
Serial part in the program is moved with main thread; Parallel section in the program moves with a plurality of branches thread.As shown in Figure 8.Step is following:
1) main thread operation.
2) main thread activates branch's thread, then, and the main thread dormancy.
3) branch's thread operation.
4) branch's thread dormancy.Because the dormancy of branch's thread, main thread can be waken up by condition.
For step 2), the composition of the bag tail of instruction bag is such:
The current thread condition is waken instruction up: 1 or many
Subject thread PC instruction: 1 or many
Subject thread activation instruction: 1 or many
Current thread dormancy instruction: 1
For step 4), the composition of the bag tail of instruction bag is such:
The current thread condition is waken instruction up: 0
Subject thread PC instruction: 0
Subject thread activation instruction: 0
Current thread dormancy instruction: 1
The above; Be merely the preferable embodiment of the present invention; Protection scope of the present invention is not limited thereto; Any technician who is familiar with the present technique field is in the technical scope that the present invention discloses, and the simple change of the technical scheme that obtains or equivalence replacement all fall in protection scope of the present invention with may be obvious that.
Claims (6)
1. an instruction bag that is used for the concurrent multiline procedure processor of chip multi-core is characterized in that, form by inclusion, bag tail,
Said inclusion is made up of many instructions, and said instruction is an ordinary instruction;
Said bag tail is made up of many instructions, and said instruction is a special instruction, comprises that the current thread condition wakes instruction, subject thread PC instruction, subject thread activation instruction, current thread dormancy instruction up.
2. instruction bag according to claim 1 is characterized in that, said instruction bag also comprises packet header.
3. instruction bag according to claim 1 is characterized in that, said current thread dormancy instruction is 1.
4. the method for operating of each described instruction bag of claim 1-3 is characterized in that, may further comprise the steps:
1) main thread operation;
2) main thread activates branch's thread, then, and the main thread dormancy;
3) branch's thread operation;
4) branch's thread dormancy, because the dormancy of branch's thread, main thread can be waken up by condition.
5. method according to claim 4 is characterized in that step 2) described in the consisting of of bag tail of instruction bag:
The current thread condition is waken instruction up: 1 or many
Subject thread PC instruction: 1 or many
Subject thread activation instruction: 1 or many
Current thread dormancy instruction: 1.
6. method according to claim 4 is characterized in that, the consisting of of the bag tail of instruction bag described in the step 4):
The current thread condition is waken instruction up: 0
Subject thread PC instruction: 0
Subject thread activation instruction: 0
Current thread dormancy instruction: 1.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018014300A1 (en) * | 2016-07-21 | 2018-01-25 | 张升泽 | Power implementation method and system for multi-core chip |
| CN109117333A (en) * | 2018-09-29 | 2019-01-01 | 深圳比特微电子科技有限公司 | Computing chip and its operating method |
| CN114281751A (en) * | 2020-09-28 | 2022-04-05 | 上海商汤智能科技有限公司 | Chip system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1685315A (en) * | 2002-06-03 | 2005-10-19 | 英特尔公司 | Architecture to support multiple concurrent execution contexts on a processor |
| CN1853166A (en) * | 2003-09-30 | 2006-10-25 | 英特尔公司 | Methods and apparatuses for thread management of multi-threading |
| CN101788922A (en) * | 2009-01-22 | 2010-07-28 | 国际商业机器公司 | Method and device for realizing transaction storage system based on auxiliary thread |
-
2012
- 2012-04-20 CN CN2012101171107A patent/CN102629192A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1685315A (en) * | 2002-06-03 | 2005-10-19 | 英特尔公司 | Architecture to support multiple concurrent execution contexts on a processor |
| CN1853166A (en) * | 2003-09-30 | 2006-10-25 | 英特尔公司 | Methods and apparatuses for thread management of multi-threading |
| CN101788922A (en) * | 2009-01-22 | 2010-07-28 | 国际商业机器公司 | Method and device for realizing transaction storage system based on auxiliary thread |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018014300A1 (en) * | 2016-07-21 | 2018-01-25 | 张升泽 | Power implementation method and system for multi-core chip |
| CN109117333A (en) * | 2018-09-29 | 2019-01-01 | 深圳比特微电子科技有限公司 | Computing chip and its operating method |
| CN114281751A (en) * | 2020-09-28 | 2022-04-05 | 上海商汤智能科技有限公司 | Chip system |
| CN114281751B (en) * | 2020-09-28 | 2024-01-02 | 上海商汤智能科技有限公司 | Chip system |
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Application publication date: 20120808 |