CN102629103A - Low-order adjusting method for network clock timekeeping module of satellite time service system - Google Patents
Low-order adjusting method for network clock timekeeping module of satellite time service system Download PDFInfo
- Publication number
- CN102629103A CN102629103A CN2012100899988A CN201210089998A CN102629103A CN 102629103 A CN102629103 A CN 102629103A CN 2012100899988 A CN2012100899988 A CN 2012100899988A CN 201210089998 A CN201210089998 A CN 201210089998A CN 102629103 A CN102629103 A CN 102629103A
- Authority
- CN
- China
- Prior art keywords
- chip microcomputer
- signal
- quartz oscillator
- unit timing
- timing length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
A low-order adjusting method for a network clock timekeeping module of a satellite time service system relates to the technical field of network clocks and solves the technical problem of improving punctuality precision. The method relates to the network clock timekeeping module in the satellite time service system. The network clock timekeeping module comprises a quartz crystal oscillator and a single-chip microcomputer. The method is characterized in that when the single-chip microcomputer of the network clock punctuality module works in a tracking mode, the single-chip microcomputer receives clock (CLK) signals output by the quartz crystal oscillator and outputs corresponding voltage control signals to control working voltage of the quartz crystal oscillator according to pulse frequency of the CLK signals so as to enable the quartz crystal oscillator to adjust pulse frequency of the output CLK signals. The method can control time offset in every 24 hours to be within 5 microseconds compared with a standard clock.
Description
Technical field
The present invention relates to the technology of clock, particularly relate to a kind of technology of the punctual module low order method of adjustment of network clocking of satellite time dissemination system.
Background technology
In the satellite time dissemination system, all be provided with the gps satellite signal receiver module; System receives the gps satellite time service information that includes PPS (pulse per second (PPS)) signal through the gps satellite signal receiver module, and synchronous according to realization system's time service of PPS (pulse per second (PPS)) signal in the gps satellite time service information that receives and network clocking.
In order normally to receive PPS (pulse per second (PPS)) signal in the gps satellite time service information at the gps satellite signal receiver module time, the normal operation that safeguards system time service and network clocking are synchronous all is provided with the punctual module of network clocking in the satellite time dissemination system.
The punctual module of existing network clocking mainly is made up of quartz oscillator (OCXO) and single-chip microcomputer; Quartz oscillator is used to export CLK (clock) signal and gives single-chip microcomputer; The gps satellite signal receiver module receives the time service information that includes PPS (pulse per second (PPS)) signal from satellite; And send to the single-chip microcomputer of the punctual module of network clocking in real time; The single-chip microcomputer of the punctual module of network clocking is followed the tracks of the PPS signal of satellite-signal receiver module output; If it is synchronous to detect the PPS signal and the satellite of the output of satellite receiver module, then is operated in tracing mode, otherwise then is operated in punctual pattern; The single-chip microcomputer of the punctual module of network clocking is operated under the tracing mode directly output from the PPS signal of satellite receiver module, is operated in that the CLK signal according to quartz oscillator output generates local PPS signal output under the punctual pattern.
The punctual module of existing network clocking is in order to guarantee the precision of local PPS signal; All need adopt high-precision quartz oscillator, very big to the index dependence of quartz oscillator, punctual precision is mainly confirmed by quartz oscillator; Therefore the quartz oscillator cost of the punctual module of existing network clock is all higher; Even if adopt high-precision quartz oscillator, its punctual precision is also relatively poor, per 24 hours often will with the about 20us of standard time clock difference.
Summary of the invention
To the defective that exists in the above-mentioned prior art, technical matters to be solved by this invention provides a kind of punctual module low order method of adjustment of network clocking that can improve the satellite time dissemination system of punctual precision.
In order to solve the problems of the technologies described above, the network clocking of a kind of satellite time dissemination system provided by the present invention module low order method of adjustment of keeping time relates to the punctual module of satellite-signal receiver module, network clocking in the satellite time dissemination system; The punctual module of said network clocking comprises quartz oscillator, single-chip microcomputer;
The satellite-signal receiver module receives the time service information that includes the PPS signal from satellite, and sends to the single-chip microcomputer of the punctual module of network clocking in real time;
The single-chip microcomputer of the punctual module of network clocking is followed the tracks of the PPS signal of satellite-signal receiver module output, if it is synchronous to detect the PPS signal and the satellite of the output of satellite receiver module, then is operated in tracing mode, otherwise then is operated in punctual pattern;
When the single-chip microcomputer of the punctual module of network clocking was operated in tracing mode, directly output was from the PPS signal of satellite receiver module;
When the single-chip microcomputer of the punctual module of network clocking was operated in the pattern of keeping time, single-chip microcomputer received the CLK signal of quartz oscillator output, and generated local PPS signal according to the CLK signal that receives;
It is characterized in that:
In single-chip microcomputer, preestablish a per second full sized pules amount; Reach two adjustment dividing values, two unit timing lengths; Said two adjustment dividing values are respectively the first adjustment dividing value, the second adjustment dividing value; Said two unit timing lengths are respectively the first unit timing length, the second unit timing length, and the duration of the said first unit timing length is less than the second unit timing length;
When the single-chip microcomputer of the punctual module of network clocking is operated in tracing mode; Single-chip microcomputer receives the CLK signal of quartz oscillator output; And the real-time pulsed frequency of calculating the CLK signal that receives, according to the pulsed frequency of the CLK signal that calculates, export the WV that corresponding voltage-controlled signal is controlled quartz oscillator; Make the pulsed frequency of the CLK signal of quartz oscillator adjustment output, the concrete steps of Single-chip Controlling quartz oscillator adjustment CLK signal pulse frequency are following:
1) single-chip microcomputer begins the timing of first a new unit timing length;
2) single-chip microcomputer umber of pulse value to the CLK signal of quartz oscillator output in the current first unit timing length is counted;
3), draw the full sized pules amount in the first unit timing length according to the first unit timing length and per second full sized pules amount;
The number of pulses of the CLK signal that single-chip microcomputer is received in the current first unit timing length is designated as A, and the full sized pules amount in the first unit timing length is designated as C, and the first adjustment dividing value is designated as E;
When A＜C, single-chip microcomputer promptly increases the voltage-controlled signal value of output, and the WV of quartz oscillator is strengthened, and makes the pulsed frequency of CLK signal of quartz oscillator output increase, and then goes to step 1;
As A＞C and (A-C)＞and during E, single-chip microcomputer promptly reduces the voltage-controlled signal value exported, and the WV of quartz oscillator is reduced, and make the pulsed frequency of CLK signal of quartz oscillator output reduce, and then go to step 1;
As A＞C and (A-C)≤during E, go to step 4;
4) single-chip microcomputer begins the timing of second a new unit timing length;
5) single-chip microcomputer umber of pulse value to the CLK signal of quartz oscillator output in the current second unit timing length is counted;
6), draw the full sized pules amount in the second unit timing length according to the second unit timing length and per second full sized pules amount;
The number of pulses of the CLK signal that single-chip microcomputer is received in the current second unit timing length is designated as B, and the full sized pules amount in the second unit timing length is designated as D, and the second adjustment dividing value is designated as F;
When B＜D, single-chip microcomputer promptly increases the voltage-controlled signal value of output, and the WV of quartz oscillator is strengthened, and makes the pulsed frequency of CLK signal of quartz oscillator output increase, and then goes to step 1;
As B＞D and (B-D)＞and during F, single-chip microcomputer promptly reduces the voltage-controlled signal value exported, and the WV of quartz oscillator is reduced, and make the pulsed frequency of CLK signal of quartz oscillator output reduce, and then go to step 4;
As B＞D and (B-D)≤during F, single-chip microcomputer finishes the control adjustment of the CLK signal pulse frequency of quartz oscillator output.
The network clocking of the satellite time dissemination system provided by the invention module low order method of adjustment of keeping time; Utilize single-chip microcomputer to detect the pulsed frequency of the CLK signal of quartz oscillator output; And export the WV that corresponding voltage-controlled signal is controlled quartz oscillator according to the pulsed frequency of the CLK signal that calculates; Make the pulsed frequency of the CLK signal of quartz oscillator output make corresponding adjustment; Therefore can improve the precision of local PPS signal, and then the raising precision of keeping time, can per 24 hours time offset be controlled at and differ in about 5us with standard time clock.
Embodiment
Below in conjunction with specific embodiment technical scheme of the present invention is described in further detail.
The network clocking of a kind of satellite time dissemination system that the embodiment of the invention the provided module low order method of adjustment of keeping time relates to the punctual module of satellite-signal receiver module, network clocking in the satellite time dissemination system; The punctual module of said network clocking comprises quartz oscillator (OCXO), single-chip microcomputer;
The satellite-signal receiver module receives the time service information that includes PPS (pulse per second (PPS)) signal from satellite, and sends to the single-chip microcomputer of the punctual module of network clocking in real time;
The single-chip microcomputer of the punctual module of network clocking is followed the tracks of the PPS signal of satellite-signal receiver module output, if it is synchronous to detect the PPS signal and the satellite of the output of satellite receiver module, then is operated in tracing mode, otherwise then is operated in punctual pattern;
When the single-chip microcomputer of the punctual module of network clocking was operated in tracing mode, directly output was from the PPS signal of satellite receiver module;
When the single-chip microcomputer of the punctual module of network clocking was operated in the pattern of keeping time, single-chip microcomputer received CLK (clock) signal of quartz oscillator output, and generated local PPS signal according to the CLK signal that receives;
It is characterized in that:
In single-chip microcomputer, preestablish a per second full sized pules amount; Reach two adjustment dividing values, two unit timing lengths; Said two adjustment dividing values are respectively the first adjustment dividing value, the second adjustment dividing value; Said two unit timing lengths are respectively the first unit timing length, the second unit timing length, and the duration of the said first unit timing length is less than the second unit timing length;
When the single-chip microcomputer of the punctual module of network clocking is operated in tracing mode; Single-chip microcomputer receives the CLK signal of quartz oscillator output; And the real-time pulsed frequency of calculating the CLK signal that receives, according to the pulsed frequency of the CLK signal that calculates, export the WV that corresponding voltage-controlled signal is controlled quartz oscillator; Make the pulsed frequency of the CLK signal of quartz oscillator adjustment output, the concrete steps of Single-chip Controlling quartz oscillator adjustment CLK signal pulse frequency are following:
1) single-chip microcomputer begins the timing of first a new unit timing length;
2) single-chip microcomputer umber of pulse value to the CLK signal of quartz oscillator output in the current first unit timing length is counted;
3), draw the full sized pules amount in the first unit timing length according to the first unit timing length and per second full sized pules amount;
The number of pulses of the CLK signal that single-chip microcomputer is received in the current first unit timing length is designated as A, and the full sized pules amount in the first unit timing length is designated as C, and the first adjustment dividing value is designated as E;
When A＜C, single-chip microcomputer promptly increases the voltage-controlled signal value of output, and the WV of quartz oscillator is strengthened, and makes the pulsed frequency of CLK signal of quartz oscillator output increase, and then goes to step 1;
As A＞C and (A-C)＞and during E, single-chip microcomputer promptly reduces the voltage-controlled signal value exported, and the WV of quartz oscillator is reduced, and make the pulsed frequency of CLK signal of quartz oscillator output reduce, and then go to step 1;
As A＞C and (A-C)≤during E, go to step 4;
4) single-chip microcomputer begins the timing of second a new unit timing length;
5) single-chip microcomputer umber of pulse value to the CLK signal of quartz oscillator output in the current second unit timing length is counted;
6), draw the full sized pules amount in the second unit timing length according to the second unit timing length and per second full sized pules amount;
The number of pulses of the CLK signal that single-chip microcomputer is received in the current second unit timing length is designated as B, and the full sized pules amount in the second unit timing length is designated as D, and the second adjustment dividing value is designated as F;
When B＜D, single-chip microcomputer promptly increases the voltage-controlled signal value of output, and the WV of quartz oscillator is strengthened, and makes the pulsed frequency of CLK signal of quartz oscillator output increase, and then goes to step 1;
As B＞D and (B-D)＞and during F, single-chip microcomputer promptly reduces the voltage-controlled signal value exported, and the WV of quartz oscillator is reduced, and make the pulsed frequency of CLK signal of quartz oscillator output reduce, and then go to step 4;
As B＞D and (B-D)≤during F, single-chip microcomputer finishes the control adjustment of the CLK signal pulse frequency of quartz oscillator output.
In the embodiment of the invention, said satellite-signal receiver module, the punctual module of network clocking, and the synchronous method of single-chip microcomputer detection satellite of the punctual module of network clocking, the method that generates local PPS signal according to the CLK signal is prior art.
In the embodiment of the invention; Predefined per second full sized pules amount is the individual pulse of 60M (million) in single-chip microcomputer, and the first unit timing length is 128 seconds, and the second unit timing length is 1024 seconds; The first adjustment dividing value is 10; The second adjustment dividing value is 10, and the full sized pules amount in the first unit timing length is 128 * 60,000,000 pulses, and the full sized pules amount in the second unit timing length is 1024 * 60,000,000 pulses;
The voltage-controlled signal initial value of single-chip microcomputer output is 31968; When single-chip microcomputer output initial value is 31968 voltage-controlled signal; The voltage-controlled voltage that after digital-to-analog conversion, is input to quartz oscillator is 2V; The every increase of voltage-controlled signal of single-chip microcomputer output or reduce 2048, voltage-controlled signal is input to quartz oscillator after digital-to-analog conversion voltage-controlled voltage also increases or reduces about 0.128v accordingly.
Claims (1)
1. the punctual module low order method of adjustment of the network clocking of a satellite time dissemination system relates to the punctual module of satellite-signal receiver module, network clocking in the satellite time dissemination system; The punctual module of said network clocking comprises quartz oscillator, single-chip microcomputer;
The satellite-signal receiver module receives the time service information that includes the PPS signal from satellite, and sends to the single-chip microcomputer of the punctual module of network clocking in real time;
The single-chip microcomputer of the punctual module of network clocking is followed the tracks of the PPS signal of satellite-signal receiver module output, if it is synchronous to detect the PPS signal and the satellite of the output of satellite receiver module, then is operated in tracing mode, otherwise then is operated in punctual pattern;
When the single-chip microcomputer of the punctual module of network clocking was operated in tracing mode, directly output was from the PPS signal of satellite receiver module;
When the single-chip microcomputer of the punctual module of network clocking was operated in the pattern of keeping time, single-chip microcomputer received the CLK signal of quartz oscillator output, and generated local PPS signal according to the CLK signal that receives;
It is characterized in that:
In single-chip microcomputer, preestablish a per second full sized pules amount; Reach two adjustment dividing values, two unit timing lengths; Said two adjustment dividing values are respectively the first adjustment dividing value, the second adjustment dividing value; Said two unit timing lengths are respectively the first unit timing length, the second unit timing length, and the duration of the said first unit timing length is less than the second unit timing length;
When the single-chip microcomputer of the punctual module of network clocking is operated in tracing mode; Single-chip microcomputer receives the CLK signal of quartz oscillator output; And the real-time pulsed frequency of calculating the CLK signal that receives, according to the pulsed frequency of the CLK signal that calculates, export the WV that corresponding voltage-controlled signal is controlled quartz oscillator; Make the pulsed frequency of the CLK signal of quartz oscillator adjustment output, the concrete steps of Single-chip Controlling quartz oscillator adjustment CLK signal pulse frequency are following:
1) single-chip microcomputer begins the timing of first a new unit timing length;
2) single-chip microcomputer umber of pulse value to the CLK signal of quartz oscillator output in the current first unit timing length is counted;
3), draw the full sized pules amount in the first unit timing length according to the first unit timing length and per second full sized pules amount;
The number of pulses of the CLK signal that single-chip microcomputer is received in the current first unit timing length is designated as A, and the full sized pules amount in the first unit timing length is designated as C, and the first adjustment dividing value is designated as E;
When A＜C, single-chip microcomputer promptly increases the voltage-controlled signal value of output, and the WV of quartz oscillator is strengthened, and makes the pulsed frequency of CLK signal of quartz oscillator output increase, and then goes to step 1;
As A＞C and (A-C)＞and during E, single-chip microcomputer promptly reduces the voltage-controlled signal value exported, and the WV of quartz oscillator is reduced, and make the pulsed frequency of CLK signal of quartz oscillator output reduce, and then go to step 1;
As A＞C and (A-C)≤during E, go to step 4;
4) single-chip microcomputer begins the timing of second a new unit timing length;
5) single-chip microcomputer umber of pulse value to the CLK signal of quartz oscillator output in the current second unit timing length is counted;
6), draw the full sized pules amount in the second unit timing length according to the second unit timing length and per second full sized pules amount;
The number of pulses of the CLK signal that single-chip microcomputer is received in the current second unit timing length is designated as B, and the full sized pules amount in the second unit timing length is designated as D, and the second adjustment dividing value is designated as F;
When B＜D, single-chip microcomputer promptly increases the voltage-controlled signal value of output, and the WV of quartz oscillator is strengthened, and makes the pulsed frequency of CLK signal of quartz oscillator output increase, and then goes to step 1;
As B＞D and (B-D)＞and during F, single-chip microcomputer promptly reduces the voltage-controlled signal value exported, and the WV of quartz oscillator is reduced, and make the pulsed frequency of CLK signal of quartz oscillator output reduce, and then go to step 4;
As B＞D and (B-D)≤during F, single-chip microcomputer finishes the control adjustment of the CLK signal pulse frequency of quartz oscillator output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100899988A CN102629103A (en) | 2012-03-30 | 2012-03-30 | Low-order adjusting method for network clock timekeeping module of satellite time service system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100899988A CN102629103A (en) | 2012-03-30 | 2012-03-30 | Low-order adjusting method for network clock timekeeping module of satellite time service system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102629103A true CN102629103A (en) | 2012-08-08 |
Family
ID=46587370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100899988A Pending CN102629103A (en) | 2012-03-30 | 2012-03-30 | Low-order adjusting method for network clock timekeeping module of satellite time service system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102629103A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026919A (en) * | 2016-05-16 | 2016-10-12 | 南京理工大学 | Time-keeping compensation method for high-precision crystal oscillator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6711230B1 (en) * | 2002-09-27 | 2004-03-23 | Nortel Networks Limited | Reference timing signal oscillator with frequency stability |
| CN1489828A (en) * | 2000-12-21 | 2004-04-14 | ����ɭ�绰�ɷ�����˾ | Oscilating circuit and method for callberating same |
| CN1649287A (en) * | 2005-03-18 | 2005-08-03 | 北京北方烽火科技有限公司 | Digital phase-lock method for clock signal in radio-frequency Layuan module |
| CN102004441A (en) * | 2010-12-15 | 2011-04-06 | 许继集团有限公司 | Adaptive crystal oscillator frequency timekeeping method |
-
2012
- 2012-03-30 CN CN2012100899988A patent/CN102629103A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489828A (en) * | 2000-12-21 | 2004-04-14 | ����ɭ�绰�ɷ�����˾ | Oscilating circuit and method for callberating same |
| US6711230B1 (en) * | 2002-09-27 | 2004-03-23 | Nortel Networks Limited | Reference timing signal oscillator with frequency stability |
| CN1649287A (en) * | 2005-03-18 | 2005-08-03 | 北京北方烽火科技有限公司 | Digital phase-lock method for clock signal in radio-frequency Layuan module |
| CN102004441A (en) * | 2010-12-15 | 2011-04-06 | 许继集团有限公司 | Adaptive crystal oscillator frequency timekeeping method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026919A (en) * | 2016-05-16 | 2016-10-12 | 南京理工大学 | Time-keeping compensation method for high-precision crystal oscillator |
| CN106026919B (en) * | 2016-05-16 | 2019-05-07 | 南京理工大学 | The punctual compensation method of crystal oscillator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103117742B (en) | System tamed by GPS/ Big Dipper dual mode satellite clock crystal oscillator | |
| CN103913753B (en) | High-precision timing system and method with navigation satellite adopted | |
| CN102412957B (en) | High-precision synchronous clock adjusting method | |
| CN105676627A (en) | Time keeping system primary and standby main clock seamless switching system and method | |
| CN104199278B (en) | The anti-high-precise synchronization clock system for blocking and its synchronous method based on many navigation system | |
| CN105049040A (en) | Method for correcting output frequency of CPT (Coherent Population Trapping) atomic clock through GNSS(Global Navigation Satellite System) | |
| CN103532652A (en) | Time synchronizing device and method | |
| CN104300969B (en) | A kind of high-precise synchronization clock implementation method based on all-digital phase-locked loop | |
| CN103840485A (en) | Global synchronization pulse width modulation system and method of distributed grid-connected inverter system | |
| CN104570717A (en) | Time keeping system based on GPS /Beidou satellite and finite-state machine | |
| CN100588280C (en) | Method and device for calibrating sleep clock of TD-SCDMA terminal | |
| CN102509461B (en) | Traffic signal coordinated control smooth transition and deviation correction method | |
| CN105680855A (en) | Automatic frequency control method for smart grid sensing device | |
| CN104485954B (en) | The control method and time device of a kind of time device | |
| CN103795522A (en) | Punctuality compensating circuit and method for pulse per second | |
| CN101043253A (en) | Process for obtaining high-precision time | |
| CN104503222A (en) | Watch and method for synchronizing time thereof | |
| CN103605138A (en) | Clock correction method and device for satellite navigation receiver | |
| CN106383438B (en) | One kind taming and dociling clock method based on sliding window time extension high-precision | |
| CN105759600A (en) | Beidou Satellite-based power grid system time-service system | |
| CN102629103A (en) | Low-order adjusting method for network clock timekeeping module of satellite time service system | |
| CN102096440B (en) | Method for keeping high precision of real time clock circuit | |
| CN107064918B (en) | High-precision radar ranging method | |
| CN102281062A (en) | Method and equipment for outputting clock signals | |
| CN110611544A (en) | Method and device for accurately timing by utilizing RS232 serial port |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120808 |