CN102624401B - Compatible structure and unstructured low density parity check (LDPC) decoder and decoding algorithm - Google Patents
Compatible structure and unstructured low density parity check (LDPC) decoder and decoding algorithm Download PDFInfo
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Abstract
The invention provides a high-efficiency low density parity check (LDPC) decoder structure and a data conflict solution. The decoder adopts a universal serial processing mode, and an LDPC decoding algorithm and a hardware architecture are specially optimized. The classical turbo decoding message passing (TDMP) algorithm cannot be applied to unstructured LDPC codes such as LDPC codes in digital video broadcasting-satellite-second generator (DVB-S2) and China mobile multimedia broadcasting (CMMB). If the TDMP algorithm is directly adopted, a data conflict can be caused, and the performance of LDPC codes can be lowered. The TDMP algorithm is optimized, so that the TDMP algorithm can be well applied to the unstructured LDPC codes. The conventional reading-writing of external information is finished at a time, and a large memory space is required; and improvement is made, so that the memory space required by the decoder is effectively reduced. In terms of a processing unit, the recovery of the external information and the update operation of prior information and posterior information are also optimized. Moreover, in order to achieve compatibility with structured and unstructured LDPC codes, a main decoding time sequence is optimized. By the optimization measures, the hardware utilization efficiency of the decoder is improved.
Description
Technical field
The invention belongs to communication technical field, be specifically related to decoding algorithm and the decoder architecture of forward error correction-LDPC code, mainly comprise compatibility, decoder hardware architecture and the timing optimization of optimization, structuring and the destructuring LDPC decoding of TDMP algorithm.
Background technology
First R.Gallager has proposed LDPC code (Low Density Parity Check Codes low density parity check code) in 1962, but due to calculated level and the understanding deficiency of people to this code at that time, LDPC code did not come into one's own in decades after this.After 1993, the people such as MacKay have rediscovered LDPC code.The performance of this yard is very excellent, even in the time that code length is longer, can approach the Shannon limit, and LDPC also has less decoding error probability and lower decoding complexity.Since the nineties in last century, the world has entered information-based, digitlization Rapid development stage, various communication systems constantly occur, as the IEEE 802.11n(WLAN in broadband wireless access field) and IEEE 802.16e(WiMAX), the European Digital Television satellite transmission standard (DVB-S2) in DMB field, China Digital TV ground transmission standard (DTMB) and be applicable to China Mobile multimedia broadcasting standard (CMMB) of handheld mobile device etc.Due to the outstanding performance of LDPC code, most communication standards have all adopted LDPC code as its forward error correction.
LDPC is divided into two kinds with regard to its structure: structuring and destructuring LDPC code.It is capable great in one submatrix whether its difference is to contain in check matrix.Structurized LDPC code, as the LDPC code in DTMB and IEEE 802.16m, does not comprise this class submatrix in its check matrix, non-structured LDPC code is as comprised this class submatrix in CMMB and DVB-S2.
The decoding algorithm of LDPC mainly contains two kinds: TPMP(Two Phase Message Passing) algorithm or TDMP(Turbo Decoding Message Passing) algorithm.The difference of two class algorithms is ranks update sequence difference.In TPMP algorithm, all row and leu order are upgraded, and all row or column are just carried out the renewal of column or row after upgrading and being over.And the way of TDMP algorithm is row and the renewal of leu order of part, the row that normally first carries out a certain layer upgrades, then by the related row renewal of row of layer therewith.Generally speaking, TDMP convergence of algorithm speed is faster, and storage resources takies also still less.But TDMP will run into the problem of data collision in the time processing destructuring LDPC, induced loss of energy, especially in the time that in the check matrix of LDPC, the great submatrix number in of row is more.
Owing to need to using different communication standards in different occasions in people's daily life, people use conventionally needs different equipment to meet the different needs, very inconvenient.A kind of trend of following hardware designs is restructural for this reason, same hardware configurable to different mode to meet different needs.Therefore ldpc decoder also should be supported various standard, and due to the difference of LDPC structure, make efficient classical TDMP algorithm can not be applied to the decoding of destructuring LDPC code.And between destructuring and structurized LDPC code, there are some difference, make configurable decoder there is certain difficulty on hardware is realized.
Summary of the invention
The object of the present invention is to provide a kind of algorithm the convergence speed fast, ldpc decoder structure and decoding algorithm that hardware availability ratio is high.
The ldpc decoder that the present invention proposes, adopts general serial process mode, and LDPC decoding algorithm and hardware structure has all been carried out to special optimization, makes ldpc decoder compatible structureization and destructuring LDPC code completely.The optimization of TDMP algorithm has improved the algorithm the convergence speed of configurable ldpc decoder, and the optimization of the storage policy of ldpc decoder, main sequential and processing unit has improved the hardware availability ratio of decoder.
One, decoding algorithm
As shown in accompanying drawing 1 (a), each LDPC code is defined by the parity matrix of a M x N.Every a line represents a check-node, and each row represents an information node.Check matrix major part is all 0, and each 1 is representing that corresponding information node and check-node have annexation on Tanner figure, as shown in accompanying drawing 1 (b).
The concrete steps of the decoding algorithm that the present invention proposes are as follows:
(1) initialization
（1）
(2) frontly test information updating
A. when the row of submatrix is heavily for the moment:
（2）
B. in the time that the row of submatrix is heavily two, in carrying out formula (2), additionally produce an information as the formula (3):
（3）
(3) external information is upgraded:
（4）
(4) posterior information is upgraded
A. when the row of submatrix is heavily for the moment, upgrade by formula (5) institute formula:
（5）
B. in the time that the row of submatrix is heavily two, upgrade by formula (6) and (7) institute formula:
（6）
（7）
(5) repeating step (2) and step (4) are until all layers all complete renewal;
(6) hard decision
（8）
(7) when reach maximum iteration time or
time, complete iteration, and output
, otherwise k add 1 and repeating step (2) to step (6);
Wherein,
the intrinsic information of information node V after channel,
the posterior information of information node V in the k time iteration,
be check-node C to information node V the external information in the k time iteration,
information node V tests information before check-node C is in the k time iteration,
normalization factor,
the set that all and check-node C have the information node of annexation,
the set that all and information node V have the check-node of annexation,
to remove symbol,
that information node V firmly sentences result in the k time iteration.
As a comparison, based on normalization the least factor algorithm, classical TDMP algorithm can be expressed as:
1) initialization
（9）
2) check-node upgrades
（10）
（11）
3) information node upgrades:
（12）
4) repeating step 2) and step 3) until all layers all completes renewal;
5) hard decision
（13）
6) when reach maximum iteration time or
time, complete iteration, and output
, otherwise k add 1 and repeating step 2) to step 6).
Classical TDMP algorithm, in the time of decoding destructuring LDPC, can run into data collision problem.As in decoding during as accompanying drawing 1 (a), at lastest imformation node
time, will there are two posterior informations suc as formula shown in (14) and (15) according to formula (10).And due to decoder adopt be serial structure, one of them value will be replaced by another value, causes the loss of information, finally causes the loss of decoding performance.
（14）
（15）。
In order to address this problem, application number is to have adopted SIMD structure to support TPMP algorithm and TDMP algorithm simultaneously in " a kind of multi-standard LDPC encoder circuit based on SIMD structure " technical scheme of 200910054350, in the time of the non-structured LDPC code of decoding, select TPMP algorithm, to avoid this data collision problem.But reduce like this degree of convergence, will increase the power consumption of hardware, and owing to adopting SIMD structure, hardware need to have been supported various instructions, will consume extra hardware resource.The present invention adjusts classical TDMP algorithm for this reason.Still undertaken by formula (10) and (11) carrying out when external information is upgraded, but test information updating before carrying out time by an information of extra generation shown in formula (3)
, for the LDPC code as shown in accompanying drawing 1 (a), its result as the formula (16).Then carry out posterior information upgrade time suc as formula shown in (6) and formula (7).For the LDPC code as shown in accompanying drawing 1 (a), just its result is suc as formula shown in (17) and (18).
（16）
（17）
（18）
Optimization of the present invention makes the effectively non-structured LDPC code of decoding of TDMP, in order to verify feasibility of the present invention, we verify by the LDPC code based on CMMB and DTMB, and accompanying drawing 2 has shown the contrast of the error rate (Bit Error Ratio, BER) curve and traditional algorithm.All emulation has all adopted AWGN (Additive White Gaussian Noise) channel and BPSK(Binary Phase Shift Keying) modulation system.Normalization factor is 0.75, in fixed point emulation posterior information and before test information and be quantified as 8 bits, external information is quantified as 6 bits.Wherein algorithm of the present invention has only used iteration 15 times, and classical algorithm has used iteration 25 times.As we can see from the figure, no matter be in floating-point or fixed-point simulation, the performance of algorithm of the present invention is all higher than classical TDMP algorithm.
Two, decoder architecture
In order to show decoder architecture of the present invention, the present invention has designed a decoder with CMMB and DTMB standard for example, and its main block diagram as shown in Figure 3.This decoder by master controller, posterior information memory module, frontly test information storage module, recovery and accumulation process unit, external information memory module, normalized unit, configurable shifting processing unit and parity check and output module forms; Wherein:
(1) described master controller, is made up of some logical circuits, for realizing the control function of whole decoder, mainly comprises the control of input and output, the coordination of each module etc.
(2) described posterior information memory module, formed by two memory blocks and a local controller, be responsible for the reading and writing of posterior information, comprise the input of intrinsic information as the formula (1), carry out as the formula (2) before test corresponding posterior information before information updating read and complete suc as formula (5) or formula (7) suc as formula after the writing of the complete posterior information of renewal.
(3) before described, test information storage module, formed by some memories and a local controller, before being responsible for upgrading suc as formula (2) or (3), test the storage of information and read testing information before corresponding before the posterior information renewal of carrying out suc as formula (5) or formula (6).
(4) described recovery and accumulation process unit, its structure as shown in Figure 4, has been responsible for the renewal operation suc as formula (2), (3), (5), (6) and (7).
(5) described external information memory module, formed by some memories and a local controller, be responsible for suc as formula before (2), (3), (5), (6) and (7) described operation to the reading of corresponding external information, complete writing of corresponding external information after upgrading suc as formula the external information of (4).Its read-write sequence as shown in Figure 5.
(6) described normalized unit, its structure as shown in accompanying drawing (6), be responsible for from recover and accumulation process unit read renewal before test information, then complete external information as the formula (4) and upgrade and operate.
(7) described configurable shifting processing unit, its structure, as shown in accompanying drawing (7), is responsible in the time processing submatrix corresponding posterior information or the front cyclic shift of testing information.
(8) described parity check and output module, is responsible for completing steps (6) and step (7), the i.e. output of hard decision, parity check and corresponding hard decision information.
The calculating of perfect (2), (3), (5), (6) and (7) is responsible in described recovery and accumulation process unit.Owing to adopting normalization minimum and (Normalized Min Sum, NMS) algorithm, external information can divide minimum value, sub-minimum, minimum value position and all sign bits into.Therefore carrying out algorithm while calculating, traditional way is that the numeral that these values are reverted to a complement form is carried out the calculating suc as formula (2), (3), (5), (6) and (7) again.But this recovery with addition and subtraction in formula is exchanged as broad as long, and in order to reduce the consumption of hardware resource, the decoder in the present invention has only adopted a kind of accumulator, and supports addition and subtraction operation.
For this reason in decoder of the present invention, the recovery of external information and front testing in the same processing unit of being updated in of information and posterior information are carried out, its structure as shown in Figure 4, be made up of some selectors, comparator, XOR unit, finite field adder, it is input as minimum value, sub-minimum, outer information symbol, minimum value index and current index.Selector extracts respective symbol according to current index value from outer information symbol.In the time that current index is identical with minimum value index, absolute value is got sub-minimum, gets minimum value when different.In the time that sign bit is different with computation schema Cal_mode (1 is subtraction, and 0 is addition), when deducting a negative or adding a positive number, signal Hsub_Ladd will be 0, and signal temp will take absolute value, and finite field adder will complete normal add operation.And sign bit is when identical with computation schema Cal_mode, when will subtracting a positive number or adding negative, signal Hsub_Ladd will be 1, and signal temp is by the step-by-step inverted value that is absolute value, and finite field adder will complete subtraction operation.Decoder just can operate the recovery of external information and front testing in the same processing unit of being updated in of information or posterior information like this, has saved the use of hardware, has improved hardware efficiency and can reduce power consumption.
The calculating of perfect (4) is responsible in described normalized unit, and its structure as shown in Figure 6, is made up of absolute value device, multiplier, overflow check module and two comparators.The current information of testing completes after the renewal suc as formula (2), is just passed to this module.Before first obtaining, test the absolute value of information, and then be multiplied by normalization factor
.Because the information of front testing is 8, its absolute value is 7, and external information only has 6, and its absolute value is 5, therefore taking advantage of after normalization factor, still needs to carry out overflow check, to cut position is arrived to the needed bit wide of external information.Be finally by the first and current minimum value comparison of the value after cut position, wherein minimum value is as output minimum value, and sub-minimum wherein compares with current sub-minimum, and wherein minimum value is as exporting sub-minimum.
Described configurable cyclic shifter adopts configurable cyclic shift network as shown in Figure 7, has adopted three grades of flowing water semi-parallel architectures, and every one-level is all made up of some selectors, is responsible for respectively the displacement of a location number.Because the submatrix of LDPC check matrix is cyclic shift matrix, and the storage of external information is carried out according to natural order, therefore test information or posterior information renewal before carrying out time, corresponding posterior information or the front information of testing need to be carried out to certain displacement ability with external information is corresponding one by one accordingly, therefore need cyclic shifter.Due to the LDPC numeral matrix size difference of various criterion, and the cyclic shift ordinal number difference of submatrix, cyclic shifter need to be supported different width and displacement ordinal number, therefore this shift unit must be configurable.
Configurable cyclic shift network of the present invention, has adopted three grades of flowing water semi-parallel architectures.Its displacement width can be arranged to different value according to the standard of decoding, realizes the configurable of width.Approve of in right shift P-m position to the m position that moves to left, therefore cyclic shifter can only be supported a direction.And displacement ordinal number offset this as 8, be divided into three parts: offset[2:0], offset[5:3], offset[7:6].The first order a=offset[2:0 that is responsible for being shifted] position, and the second level b=8 x offset[2:0 that are responsible for being shifted] position, the afterbody c=64 x offset[2:0 that are responsible for being shifted] position.
Brief description of the drawings
Fig. 1 LDPC check matrix schematic diagram.
Fig. 2 algorithm performance comparison diagram.
Fig. 3 decoder overall construction drawing.
Fig. 4 recovers and accumulator module schematic diagram.
Fig. 5 external information storage sequential chart.
Fig. 6 normalized cellular construction figure.
The configurable cyclic shifter of Fig. 7.
Fig. 8 is capable, and schematic diagram divided in the great submatrix in.
The main sequential chart of Fig. 9.
Figure 10 decoder rear end domain.
Embodiment
According to the solution providing in summary of the invention, during with decoding architecture LDPC code, adopt classical TDMP algorithm, in the time of decoding destructuring LDPC code, adopt the TDMP decoding algorithm after adjusting of the present invention.The present invention has also optimized external information storage policy.Lower outsidely external information storage policy of the present invention, main sequential and the comparison with other decoders will be introduced respectively.
External information storage policy
Conventionally decoder can complete the read-write operation of the external information of certain one deck in one-period, but the different code checks of various criterion check matrix structure is before different.Subordinate list 1 has been listed the major parameter of external information storage in CMMB and DTMB.If adopt traditional storage policy, relevant parameter need to adopt each code check maximum before so, is 36 x 128 x 42=193,536 bits.This will greatly waste memory space.
The storage of external information is divided into several cycles by the present invention for this reason, and each external information is only processed some bits in each cycle, and sequential chart as shown in Figure 5.In the time of CMMB code check 1/2 and DTMB code check 2/5, need three cycles like this, when CMMB code check 3/4 and DTMB code check 3/5, need four cycles, when DTMB code check 4/5, need 6 cycles.The degree of depth of memory will be taken advantage of in the required cycle for the number of plies like this, and maximum is 36 x 3=108.The bit of each period treatment is 7 x 128=896.The memory space altogether needing is 108x896=96, and 768 bits are only the half of conventional store strategy.
The main sequential of decoding
About the check matrix of CMMB, can provide 2 statements: 1) in certain one deck, only may contain a row great in one submatrix; 2) going the great submatrix in can be divided into a standard cell battle array and a cyclic shift matrix.The check matrix of accompanying drawing 1 has similar feature, and it can be divided into the submatrix shown in accompanying drawing 8, and wherein identical posterior information shared in submatrix 0 and submatrix 1.Below by the LDPC code taking shown in accompanying drawing 1 as example illustrates the main sequential of decoding of the present invention.
Great during in one submatrix when going in layer, as the LDPC in DTMB, hardware operates by classical TDMP algorithm, and its main sequential is shown in accompanying drawing 9 (a).
1, while testing information and external information renewal before carrying out, first decoder reads corresponding posterior information from posterior information memory module, and (reading of external information is divided into several cycles with writing, in accompanying drawing 9, do not show), and from Hrom, read out corresponding displacement ordinal number.Then configurable cyclic shifter is by the displacement completing posterior information.After being shifted, recover and accumulation process unit by the posterior information reading after displacement, and complete as the formula (2) before test information updating.Last normalized unit by read after renewal before test information and the external information that completes is as the formula (4) upgraded, test before information will be stored into before after meanwhile upgrading and test information storage module.
2,, in the time carrying out posterior information renewal, decoder will be tested information before testing first in the past and reading out accordingly in information storage module.Then recovery and accumulation process unit upgrade by testing information before reading the posterior information completing as the formula (5).Posterior information after renewal will be shifted back original order in configurable cyclic shift network.Last corresponding posterior information will be stored in posterior information memory module.
When there being row great during in one submatrix in layer, as the LDPC in CMMB, hardware operates by the modified model TDMP algorithm shown in right one, and its main sequential is shown in accompanying drawing 9 (b).
3,, while testing information and external information renewal before carrying out, the operation of submatrix 1 is the same with the operation of the submatrix 0 shown in Fig. 9 (a).And decoder can clock once can complete antithetical phrase 0 before test information updating, and do not need through cyclic shift, because submatrix 0 is a standard cell battle array.Then at clock two, before submatrix 0, test information and will in configurable circular shift module, complete displacement.Then at clock three, recovery and accumulation process unit will complete as the formula (16) to extraneous information according to testing information before the submatrix 0 after displacement
generation.Finally
to before clock four is treated as, test before information stores into and test in information storage module.
4,, carrying out posterior information while upgrading, decoder will be first be tested in the past and in information storage module, read out extraneous information
.Then at clock 6, recovery and accumulation process unit will read
to complete as the formula (17)
generation.At clock 7,
to in configurable cyclic shifter, be moved back to normal sequence.Then at clock 8, recovery and accumulation process unit will read after displacement
complete as the formula (18) to posterior information
renewal.Last corresponding posterior information will be stored in posterior information memory module.
In the above-described embodiment, adopt the algorithm after adjustment provided by the invention, decoder can use same hardware cell to complete the decoding of structuring and destructuring LDPC, does not need extra processing unit, save hardware resource, improved hardware availability ratio.And can realize configurableization of decoder, improve the flexibility of decoder.
Result comparison
In order to verify the present invention program's efficiency, based on SMIC0.13um standard CMOS process, we have designed the ldpc decoder of all code checks of a support destructuring CMMB and structuring DTMB.Its rear end domain as shown in Figure 10.The kernel area of this decoder is 2.16x2.20mm
2. maximum operating frequency can reach 200MHz, and maximum gulps down rate can reach 365.7Mbps.Under 5 iterated conditionals, the rear imitative power consumption of chip is that 48.4mW is while being operated in 25MHz and CMMB standard, when 130.9mW is operated in 50MHz and DTMB standard.Subordinate list 2 has compared the hardware result of decoder of the present invention and some documents, as can be seen from the table, of the present invention can completing supports the ldpc decoder of CMMB and DTMB to have the less chip area of ldpc decoder of supporting single standard (CMMB or DTMB) than other, this shows the high efficiency of decoder of the present invention.
The major parameter of the external information storage of table 1 CMMB and DTMB
The ratio of table 2 decoder of the present invention and other decoders
。
With reference to selected works:
[1]Kai Zhang, Xinming Huang, Zhongfeng Wang, "An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems", in PROC.IEEE ASAP, pp. 235-238,July. 2009.
[2]Kai Zhang, Xinming Huang, Zhongfeng Wang, "A dual-rate LDPC decoder for china multimedia mobile broadcasting systems", IEEE Transactions on Consumer Electronices, vol. 56, pp. 399-407, May. 2010
[3]Bo Xiang, Rui Shen , An pan, Dan Bao, Xiaoyang Zeng, "An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes", IEEE Transactions on Very Large Scale Integration (VLSI) Systems ,vol.18, pp. 1447-1460, Oct. 2010
[4]M. M. Mansour and N. R. Shanbhag, "A 640-Mb/s 2048-bit programmable LDPC decoder chip," IEEE J. Solid-State Circuits, vol. 41, pp. 634-698, March. 2006。
Claims (2)
1. a follow-on TDMP interpretation method, is characterized in that carrying out special processing for non-structured LDPC code, and its concrete steps are as follows:
(1) initialization:
（1）
(2) frontly test information updating:
When the row of submatrix is heavily for the moment:
（2）
In the time that the row of submatrix is heavily two, in carrying out formula (2), additionally produce an information as the formula (3):
（3）
(3) external information is upgraded:
（4）
(4) posterior information is upgraded
When the row of submatrix is heavily for the moment, upgrade by formula (5) institute formula:
（5）
In the time that the row of submatrix is heavily two, upgrade by formula (6) and (7) institute formula:
（6）
（7）
(5) repeating step (2) and step (4) are until all layers all complete renewal;
(6) hard decision
（8）
(7) when reach maximum iteration time or
time, complete iteration, and output
, otherwise k add 1 and repeating step (2) to step (6);
Wherein,
the intrinsic information of information node V after channel,
the posterior information of information node V in the k time iteration,
be check-node C to information node V the external information in the k time iteration,
information node V tests information before check-node C is in the k time iteration,
normalization factor,
the set that all and check-node C have the information node of annexation,
the set that all and information node V have the check-node of annexation,
to remove symbol,
that information node V firmly sentences result in the k time iteration.
2. a decoder for the compatible structureization based on modified model TDMP interpretation method claimed in claim 1 and destructuring LDPC code, is characterized in that:
Described modified model TDMP interpretation method concrete steps are as follows:
(1) initialization:
（1）
(2) frontly test information updating:
When the row of submatrix is heavily for the moment:
（2）
In the time that the row of submatrix is heavily two, in carrying out formula (2), additionally produce an information as the formula (3):
（3）
(3) external information is upgraded:
（4）
(4) posterior information is upgraded
When the row of submatrix is heavily for the moment, upgrade by formula (5) institute formula:
（5）
In the time that the row of submatrix is heavily two, upgrade by formula (6) and (7) institute formula:
（6）
（7）
(5) repeating step (2) and step (4) are until all layers all complete renewal;
(6) hard decision
（8）
(7) when reach maximum iteration time or
time, complete iteration, and output
, otherwise k add 1 and repeating step (2) to step (6);
Wherein,
the intrinsic information of information node V after channel,
the posterior information of information node V in the k time iteration,
be check-node C to information node V the external information in the k time iteration,
information node V tests information before check-node C is in the k time iteration,
normalization factor,
the set that all and check-node C have the information node of annexation,
the set that all and information node V have the check-node of annexation,
to remove symbol,
that information node V firmly sentences result in the k time iteration;
Described decoder by master controller, posterior information memory module, frontly test information storage module, recovery and accumulation process unit, external information memory module, normalized unit, configurable shifting processing unit and parity check and output module forms; Wherein:
(1) described master controller, is made up of some logical circuits, for realizing the control function of whole decoder, mainly comprises the control of input and output, the coordination of each module;
(2) described posterior information memory module, formed by two memory blocks and a local controller, be responsible for the reading and writing of posterior information, comprise the input of the intrinsic information shown in formula (1), carry out shown in formula (2) before test the corresponding posterior information before information updating
read and the writing of posterior information that renewal after perfect (5) or formula (7) is complete;
(3) before described, test information storage module, formed by some memories and a local controller, before responsible perfect (2) or formula (3) renewal, test the storage of information and read testing information before corresponding before the posterior information of carrying out formula (5) or formula (6) is upgraded;
(4) described recovery and accumulation process unit, is responsible for the renewal operation of perfect (2), (3), (5), (6) and (7);
(5) described external information memory module, formed by some memories and a local controller, be responsible for suc as formula before (2), (3), (5), (6) and (7) described operation to the reading of corresponding external information, the writing of the corresponding external information after the external information of perfect (4) is upgraded;
(6) described normalized unit, be responsible for from recover and accumulation process unit read renewal before test information, then the external information shown in perfect (4) upgrade operate;
(7) described configurable shifting processing unit, is responsible in the time processing submatrix corresponding posterior information or the front cyclic shift of testing information;
(8) described parity check and output module, has been responsible for step (6) and step (7), the i.e. output of hard decision, parity check and corresponding hard decision information of described method.
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| CN101771421A (en) * | 2010-03-11 | 2010-07-07 | 复旦大学 | Ultrahigh-speed and low-power-consumption QC-LDPC code decoder based on TDMP |
| CN101800559A (en) * | 2010-03-11 | 2010-08-11 | 复旦大学 | High-speed configurable QC-LDPC code decoder based on TDMP |
| CN102291153A (en) * | 2011-06-13 | 2011-12-21 | 电子科技大学 | Decoding algorithm and partially parallel decoder for low density parity check (LDPC) code in China mobile multimedia broadcasting (CMMB) |
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