CN102623448A - Multiple patterning method - Google Patents
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- CN102623448A CN102623448A CN201110032839XA CN201110032839A CN102623448A CN 102623448 A CN102623448 A CN 102623448A CN 201110032839X A CN201110032839X A CN 201110032839XA CN 201110032839 A CN201110032839 A CN 201110032839A CN 102623448 A CN102623448 A CN 102623448A
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Abstract
The invention discloses an integrated circuit memory which comprises a group of lines. Each line possesses line portion objects which are parallel to an X direction in a first region and the line portion objects which are parallel to a Y direction in a second region. The second region is separated from the first region. The lengths of the X directional line portion objects are substantially longer than the lengths of the Y directional line portion objects. The X directional line portion objects and the Y directional line portion objects possess a first spacing and a second spacing respectively. The second spacing is 3 times or more than 3 times of the first spacing. A contact pickup area is located in the Y directional line portion objects. In some embodiments, the lines comprise a word line or a bit line. A material line can be made by using the multiple patterning method, and then the line portion objects which are parallel to the X direction and the line portion objects which are parallel to the Y direction can be made so as to make the memory.
Description
Technical field
The invention relates to the manufacturing of integrated circuit, and particularly relevant for making the multiple patterning method of integrated circuit with assistance through accepting formed wire material
Background technology
Integrated circuit is widely used in different electric devices, for example memory chip usually.Reduce extremely for the micro on the integrated circuit size at present and look forward to, can increase the density of individual component thus, and then strengthen the function of integrated circuit.The minimum spacing on the integrated circuit (distance between the identical point in two adjacent structures of identical kenel, for example: two adjacent gate conductors) be used to representative tolerance usually as current densities.
Increase the resolution that current densities is subject to the gold-tinted lithographic equipment usually.The minimum size feature that one of gold-tinted lithographic equipment can make for the bonding part is relevant with the resolution capabilities of this gold-tinted lithographic equipment with the space.
The sum total of giving minimal characteristic width that the bonding part can make and minimum space width of gold-tinted lithographic equipment is the minimum spacing that can make of equipment for this reason.The minimal characteristic width can be approximately the several times of minimum space usually, and therefore the minimum spacing of giving the bonding part manufacturing by the gold-tinted lithographic equipment is approximately to be twice in the minimal characteristic that the gold-tinted lithographic equipment can produce.
A method that is used for reducing less than the spacing of the IC apparatus of photolithographic fabrication minimum spacing is the use through two times or four times patternings, is commonly referred to multiple patterning at this.Through the method, a single mask is used on substrate, make a series of parallel line material.Then, available distinct methods is the multiple parallel wire material with each parallel line material transition.These various methods typically use a series of deposition and etching step is carried out." being used for the analysis of the more high-grade spacing portion below the 32nm " that these methods have been delivered in people such as Xie, Peng and Smith, Bruce W in the Optical Microlithography XXII meeting of SPIE in 2009 discusses.A method of in the following example, being discussed is to use self-aligned clearance wall (selfaligned sidewall spacer) to make two or four parallel line materials, and its each wire material is made by mask originally.
Summary of the invention
The present invention is the basis of confirming as according to the problem of part through spacing being reduced to time lithographic dimensioned (sub lithographicdimension).In other words,, yet generally to accept the receiving unit that these lines institute will pass through even the spacing between wire material possibly be time lithographic dimensioned, a vertical studs (plug) for example, possibly not be meet fully inferior lithographic dimensioned.Mask in order to the definition embolism is the size of photoetching, and, for allowing the mask alignment error to increase for the desired size of region of acceptance.
According to an integrated circuit memory of one embodiment of the invention, comprise one group of line, this group each bar line in line have a plurality of in one first district parallel directions X line part thing and a plurality of in one second district parallel Y traverse line part thing.The length that the length of directions X line part thing is longer than Y traverse line part thing in fact.Directions X and Y traverse line part thing have first and second spacings separately, 3 times of second spacing, first spacing.The contact zone is in Y traverse line part thing.In certain embodiments, these lines are word line or bit line.
In gold-tinted photoetch integrated circuit processing step, an embodiment who is used to make the multiple patterning method of line implements as follows.Be that one group of first wire material selected one group of line pattern.On a substrate, forming should group first wire material.This each first wire material of organizing in first wire material defines the pattern with a directions X part thing and a Y steering portion thing.The length of the directions X part thing of first wire material is longer than the length of the Y steering portion thing of first wire material in fact.A little for this reason directions X part things and Y steering portion thing are selected a plurality of first spacings and second spacing, and second spacing is greater than first spacing.Directions X part thing is for parallel, and Y steering portion thing is parallel.Formation is parallel at least two second wire materials of each first wire material, to produce a plurality of word lines that comprise a plurality of parallel directions X line part things and a plurality of parallel Y traverse line part things.Second wire material of Y traverse line part thing comprises a plurality of bottom district.A plurality of supplementary features things (supplemental features) are formed at the place of part at least in this a little bottom district.In certain embodiments, second spacing is at least four times of first spacing, and in other embodiments, second spacing is at least the octuple of first spacing.In certain embodiments, form the supplementary features thing and comprise the contact zone (contact pickup area) that forms expansion.
Others of the present invention, characteristic and advantage can be inspected from accompanying drawing, and detailed explanation and claim please refer to hereinafter.
Description of drawings
Fig. 1-8 illustrates first embodiment of one or four times of Patternized techniques with simplified way;
Fig. 1 illustrates the vertical view of the interior nido annular of a substrate (nested ring-like) wire material of corresponding mask shape; Wire material has parallel directions X part thing and parallel Y steering portion thing, in the spacing between the directions X part thing less than the spacing between Y steering portion thing;
Fig. 2 illustrates the making of the sept on each limit of Fig. 1 wire material, thereby makes the line density diplodization through the reduction of spacing;
Fig. 3 illustrates the making of the sept on each limit of Fig. 2 wire material, thereby makes four times of changes of line density of Fig. 1 through the reduction of spacing;
Fig. 4 illustrates the vertical view of a mask that is used for Fig. 3 structure;
Fig. 5 illustrates the figure of Fig. 3 structure of cover part Y steering portion thing with Fig. 4 mask work aligning;
Fig. 6 illustrates the figure as a result in the bottom district of the produced wire material of part Y steering portion thing that removes the covering of Fig. 4 mask;
Fig. 7 illustrates a mask vertical view that is used for Fig. 6 structure, and it is in order to make the supplementary features thing;
Fig. 8 illustrates the figure as a result that uses Fig. 7 mask and subsequent process steps, particularly be positioned at along contact mat and the bit line or the word line in the bottom district of Y steering portion thing, and follow-up processing step for example be develop and etching with making supplementary features thing;
Fig. 9-16 illustrates one second embodiment of one or four times of Patternized techniques of similar Fig. 1-8 with simplified way, however the form that its nido toroid material is a L type part thing;
Figure 17 A-17C illustrates three groups of additional embodiment of nido toroid material;
Figure 18 is a simplified flow chart, and this flow chart shows the practiced basic step of of the present invention multiple patterning method with reference to Fig. 1-17 of above-mentioned discussion;
Figure 19-32 illustrates the technological process of an embodiment who uses four times of patternings of BESONOS WL;
Figure 33 illustrates the calcspar that concerns between word line district, contact zone and the peripheral circuit drive zone.
[main element symbol description]
10: assembly
12: the first wire materials
14: substrate
16,40:X steering portion thing
18,38:Y steering portion thing
20,22: spacing
24,26: length
28,30: width
32: the second wire materials (sept)
34: the three wire materials (sept)
36,44,54: mask
38,40,124: word line
42: the bottom district
46: contact mat
48: the circuit interconnect
55: the position
56: bottom end assemblies
60,62,64,66,68,70: step
78,82,88,102: polysilicon
80,84: silicon dioxide
86: tungsten silicide
90:BE-SONOS charge-trapping structure
92: silicon
94: the photoresist trace
96: structure
98: silicon nitride layer
100: clearance wall
104: polysilicon gap wall
106,110: the photoresist shielding
107,114: the polysilicon segment thing
108,112,116: storehouse spare
109,113,118: silicon dioxide part thing
120: memory cell
122: be etched element
126,130: selection wire
128: charge storaging area
132: the word line district
134: the contact zone
136: the peripheral circuit drive zone
Embodiment
At this embodiment that provides the present invention one to specify, please refer to Fig. 1 to Figure 33.At this illustrated processing step and structure is not the complete process that is used for making an integrated circuit.The present invention can with this area commonly used or develop other different integrated circuits that makes skills and does to link enforcements in the future.
Description is the reference of special construction embodiment and method.Embodiment and method in that this disclosed are not that the present invention can implement with further feature, element, method and embodiment in order to qualification the present invention.The explanation of preferred embodiment of the present invention is not in order to limit the defined scope of claim of the present invention.This area has the general knowledge, and the person should discern the difference variation of following explanation.Generally discuss with the similar components in the example at different embodiment with similar reference number.
Fig. 1-8 illustrates first embodiment that merges one or four times of Patternized techniques of the present invention with simplified way.
Fig. 1 is the assembly 10 by mask manufacturing one group of nido annular (nested ring-like) first wire material 12 on a substrate 14 of corresponding shape.First wire material 12 has a plurality of parallel directions X part things 16, and a plurality of parallel Y steering portion thing 18.In the spacing 20 between the directions X part thing 16 less than the spacing 22 between Y steering portion thing 18.Spacing 20 is preferably and is no more than about 25% spacing 22, and better be to be no more than about 15% spacing 22.Greater than the length 26 of a plurality of Y steering portion things 18, the length that is surpassed generally is to discuss with the order of magnitude (orders of magnitude) to the length 24 of a plurality of directions X part things 16 in fact.Yet for the reference of drawing, the length 24 of directions X part thing 16 is not according to actual size, but significantly reduction.In this embodiment, the width 28 of each directions X part thing 16 can for example approximately be 30nm, and the width 30 of each Y steering portion thing 18 can for example approximately be 110nm.Because spacing 22 is much larger than spacing 20, so the additional width of this Y steering portion thing 18 can be received.
Fig. 2 illustrates the manufacturing of the sept 32 (spacer) on each limit of directions X part thing 16 and Y steering portion thing 18 of first wire material 12 of Fig. 1.Sept 32 is expressed as one group of second wire material 32.Compared to the density of first wire material 12, the spacing of these effective two times of line densities is reduced.In ensuing processing step, remove the directions X part thing 16 and Y steering portion thing 18 of first wire material 12, only stay second wire material, like sept 32.
Fig. 3 illustrates the manufacturing of the sept 34 on each limit of second wire material 32 of Fig. 2, and it has the spacing of reduction, and is four times of line density of Fig. 1.As part thing 16 and part thing 18, in ensuing processing step, remove second wire material 32, only stay sept 34 and be used as the 3rd wire material 34.
Fig. 4 illustrates the vertical view that uses the mask 36 with Fig. 3 structure.Mask 36 is used to the part Y steering portion thing 38 of the sept 34 of mask separation graph 3.In the Fig. 5 shown in this embodiment, directions X part thing 40 does not use mask 36 to revise.Use the Y steering portion thing 38 of the part of mask 36 removable septs 34.Result after Fig. 6 illustrates and removes, it is produced along the bottom district 42 of Y steering portion thing 38.
Fig. 7 is for using a vertical view of the mask 44 with Fig. 6 structure, to form the supplementary features thing.In this embodiment, supplementary features thing (supplemental feature) comprises a plurality of contact mats in the bottom district 42 that is applied in Y steering portion thing 38, and a plurality of circuit interconnect (circuitinterconnect line).Fig. 8 illustrates the result of use mask 44 and processing step thereafter, for example makes public and etching step, and to make supplementary features thing and circuit interconnect 48, wherein the supplementary features thing particularly is positioned at along the contact mat 46 in the bottom district 42 of Y direction part thing 38.As far as the pad spare (pad) and the aligning admissible error of lithographic dimensionedization of gold-tinted, the spacing of Y steering portion thing 38 is preferably must be enough, and because the relation of these factors, the spacing of directions X part thing 40 then is unrestricted, therefore can be time photoetching.
With the distances when compared of directions X part thing 40 time; The spacing that between the bottom district 42 of Y steering portion thing 38, is increased is important; This is because the spacing of this increase allows otherwise to form the contact mat 46 of general lithographic dimensionedization of use gold-tinted or bigger contact mat, so that the directions X part thing 40 of electrical passage to the 3rd wire material 34 of time lithographic dimensionedization of gold-tinted and spatialization to be provided.The 3rd wire material 34 is generally word line or bit line, therefore makes directions X part thing 40 and Y steering portion thing 38 be respectively directions X word/bit line portion thing 40 and Y direction word/bit line portion 38 usually.Be positioned at the enough spaces of the inner most directions X part thing of wire material 34 40 through providing, circuit interconnect 48 can be as shown in Figure 8, is arranged between the inner most directions X part thing.In other embodiments, circuit interconnect 48 can be set at the periphery of wire material 34 outermost directions X part things 40.Circuit interconnect 48 can be the line of lithographic dimensionedization of gold-tinted or the line of inferior lithographic dimensionedization of gold-tinted.
Fig. 9-16 illustrates second embodiment of four times of Patternized techniques of similar Fig. 1-8 with simplified way.Therefore, this second embodiment will not remake detailed explanation in this, and main difference is described below.The assembly 10 of nido toroid material 12 is the profile of L type part thing 52.Therefore, pair of L type part thing 52 can be produced nido toroid material.The mask 54 of Figure 12 can be electrically connected to each other through bottom end assemblies shown in Figure 11 56 in abutting connection with sept 34 to cover Y steering portion thing 38 and the directions X part thing 40 among Figure 13, to make by sized.
Figure 17 A-17C illustrates the structure 10 of three additional embodiment of nido toroid material 12, and wherein nido toroid material 12 has directions X part thing 16 and Y steering portion thing 18.Figure 17 A illustrates the sketch map of the open loop-shaped (open ringconfiguration) with first wire material 12 that two U type part things are oppositely arranged, and has gap (gaps) 19 along Y steering portion thing 18 between the two U type part things.
Figure 17 B illustrates the sketch map of another open loop-shaped with first wire material 12 that two L type part things are oppositely arranged, and also has gap (gaps) 19 along Y steering portion thing 18 between the two L type part things.Yet Y steering portion thing 18 is position pair of end (alternating ends) at two adjacent directions X part things 16.Directions X part thing 16 has first end 15 and second end 17.In this embodiment, the Y steering portion thing 18 on nido toroid material 12 outer shrouds is position first ends 15 at directions X part thing 16, and the Y steering portion thing 18 on the ring is position second ends 17 at directions X part thing 16 in the nido toroid material 12.
Figure 17 C illustrates the distortion of the open loop-shaped of Figure 17 B, and the Y steering portion thing 18 of wherein same toroid material 12 lays respectively at first end 15 and second end 17 of directions X part thing 16.Therefore two gaps 21 that produced are respectively between first end 15 and second end 17 of Y steering portion thing 18 and two relative directions X part things 16.In this embodiment, the outer shroud of toroid material 12 comprises first and second directions X part thing 16.1 and 16.2, and first and second Y steering portion thing 18.1 and 18.2.The one Y steering portion thing 18.1 is that first end, 15, the two Y steering portion things 18.2 that are positioned at the first directions X part thing 16.1 are second ends 17 that are positioned at the second directions X part thing 16.2.The interior ring of toroid material 12 comprises third and fourth directions X part thing 16.3 and 16.4, and third and fourth Y steering portion thing 18.3 and 18.4.The 3rd Y steering portion thing 18.3 is that second end, 17, the four Y steering portion things 18.4 that are positioned at the 3rd directions X part thing 16.3 are first ends 15 that are positioned at the 4th directions X part thing 16.4.
Figure 18 is a simplified flow chart, and it illustrates the basic steps of being implemented in the multiple patterning method of the present invention.In the step 60 of beginning, one group of parallel line pattern generally is the nido circular pattern, and the assembly 10 of parallel first wire material 12 is selected.First wire material 12 has the parallel directions X part thing 16 of being longer than parallel Y steering portion thing 18 in fact, for example is the length of 100 times or 1000 times.Then in step 62, first spacing 20 and second spacing 22 of directions X part thing 16 and Y steering portion thing 18 are selected.In the selecteed spacing, second spacing 22 for example is 4-8 times greater than first spacing 20.In step 64, the assembly 10 that forms parallel first wire material 12 is to cover a substrate 14.2 second wire materials 32 are formed at step 66.Second wire material 32 is parallel to first wire material 12.Form two the 3rd wire materials 34 in step 68 and be parallel to each second wire material 32.Produce parallel directions X part thing 40 with the same practice and be used as the 3rd wire material with parallel Y steering portion thing 38.The Y steering portion thing 38 of second wire material 34 comprises bottom district 42.Producing the supplementary features thing in step 70, for example is expansion contact mat 46 and the circuit interconnect 48 that is positioned at bottom district 42.
Figure 19-32 illustrates the process chart of use energy band engineering SONOS quadword line (BE-SONOS WLquadruple) self-aligned spacer patternsization (self-aligned spacer patterning) embodiment, and BE-SONOS is a charge capturing storage unit.Figure 19 illustrates a substrate 76, and substrate 76 comprises eight layers of 78-92 of ground floor to the, and is formed at the photoresist trace 94 on the ground floor 78.In this embodiment, ground floor 78, the 3rd layer 82 and layer 6 88 are polysilicon, and the second layer 80 and the 4th layer 84 are silicon dioxide.Layer 5 86 is a tungsten silicide.The 8th layer 92 is silicon.Layer 7 90 is the combination of First Five-Year Plan layer, is the charge-trapping structure for BE-SONOS, and it has interchangeable silicon dioxide layer and silicon nitride layer, and wherein silicon dioxide layer comes ground floor, the 3rd layer and layer 5 for superstructure number from then on.Because ground floor 78, the second layer 80 and the 3rd layer 82 can fully remove in Patternized technique, are sacrifice layer therefore.The setting of other material and material also can be used.
Among Figure 26, photoresist shielding 106 is used to cover the part of the structure that Figure 25 is not removed.The mask 36 that photoresist shielding 106 can be regarded as in contrast to Fig. 4.Figure 27 illustrates to remove not by the polysilicon gap wall 104 of photoresist shielding 106 protections and then remove photoresist and shields 106 result.Figure 28 illustrates etching of silicon nitride clearance wall 100 and the part of the second layer 80 that do not covered by clearance wall 104; Stay the polycrystalline silicon/silicon dioxide storehouse spare 108 that is positioned on the 3rd layer 82 with the method.Storehouse spare 108 comprises the polysilicon segment thing 107 on upper strata and the silicon dioxide part thing 109 of lower floor.The polycrystalline silicon/silicon dioxide storehouse spare 108 that is positioned at dexter two structures 96 of the 20th graph structure and be positioned on the 28th graph structure right-hand side is made comparisons, and the number that can find vertical stratification has increased by four times for from 2 to 8.
Figure 29 illustrates the photoresist shielding 110 that is positioned on the 28th graph structure, photoresist shielding 110 masks 44 corresponding to Fig. 7.Figure 30 illustrates in etching Figure 29 structure not by the 3rd layer 82 part of storehouse spare 108 or photoresist shielding 110 coverings.The polysilicon segment thing 107 on upper strata is removed, and stays storehouse spare 112.Storehouse spare 112 comprises the silicon dioxide part thing 113 on a upper strata and the polysilicon segment thing 114 of a lower floor.In Figure 30, photoresist shielding 110 has been removed.Figure 31 illustrates the etched result of oxide layer, and this etching has removed the part that is not covered by polysilicon segment thing 114 in oxide layer part thing 113 and the 4th layer 84 (silicon dioxide) on upper strata.This etching step is produced storehouse spare 116.Storehouse spare 116 comprises polysilicon segment thing 114 and silicon dioxide part thing 118.
Figure 32 illustrates layer 5 86, layer 6 88 and layer 7 90 parts that etching is not covered by storehouse spare 116; And remove polysilicon segment thing 114 and remove part silicon dioxide part thing 118; Stay next column to have the result of the memory cell 120 that is etched assembly 122,124 of corresponding tungsten silicide and polysilicon; Wherein, the composition of word line 124 row are positioned on the charge storaging area 128.In this embodiment, memory cell 120 forms NAND string.Etching step is in this embodiment also produced to be same as a string selection wire 130 that word line 124 directions are extended.After whole layer 7 90 was etched, the silicon dioxide part thing 118 of part can be retained.This is because the 4th layer 84 thickness generally is the thickness much larger than layer 7 90.
Figure 33 is a calcspar that illustrates in a word line district 132 the Y direction word line part thing 38 of the directions X word line part thing 40 that closely is provided with and looser setting.Usually in a memory circuitry, have thousands of word line 124.In this embodiment, provide two different contact zone 134 in abutting connection with being coupled to word line district 132.Contact mat 46 is positioned at along the contact zone 134 of the Y direction word line part thing 38 of looser setting (bigger spacing).One peripheral circuit drive zone 136 is coupled between two contact zones 134 and with two contact zones 134.Wherein, kenel being set is many word lines that (1) is arranged in a word line district 132; (2) word line district 132, and suppose that one or more contact zone 134 comprises along the contact mat 46 of Y direction character to part thing 38; (3) peripheral circuit drive zone 136 contact zones 134 of one or more combination, this is provided with kenel and to high-density storage an effective integrated circuit layout (layout) on actual the setting is provided.
The disclosure of above-mentioned arbitrary and all patents, patent application case and the open file that printed is incorporated into way of reference at this totally.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (28)
1. integrated circuit memory comprises:
One group of line, each the bar line in this group line have a plurality of parallel directions X line part things in one first district, and in one second district a plurality of parallel Y traverse line part things, separate each other in this second district and this first district;
The length of those directions X line part things is longer than the length of those Y traverse line part things in fact;
Those directions X line part things have a plurality of first spacings and second spacing respectively with those Y traverse line part things, and this second spacing is greater than this first spacing; And
Be positioned at a plurality of contact zones of those Y traverse line part things.
2. memory as claimed in claim 1, wherein those lines comprise a plurality of word lines or a plurality of bit line.
3. memory as claimed in claim 1, wherein those lines form with photolithographicallpatterned, and this first spacing has once lithographic dimensioned.
4. memory as claimed in claim 1, wherein those Y traverse line part things and those directions X line part things define one group of nido annular parallel line (nested ring-like parallel lines).
5. memory as claimed in claim 4; Wherein this group nido annular parallel line comprises many first and second annular parallel lines with a plurality of relative U type part things, and those U type part things along those Y traverse line part things at least some and have several gaps.
6. memory as claimed in claim 5, wherein those gaps are positioned at along the centre of at least some of those Y traverse line part things.
7. memory as claimed in claim 5, wherein those gaps are each positioned at along the every centre of this Y traverse line part thing.
8. memory as claimed in claim 4, wherein:
This group nido annular parallel line comprises many first and second annular parallel lines with a plurality of relative L type part things, and those L type part things have several gaps along those Y traverse line part things, and those first and second annular parallel lines are adjacent one another are;
Those directions X line part things with first end and second end;
Those Y traverse line part things of those first annular parallel lines are positioned at first end of those directions X line part things; With
Those Y traverse line part things of those second annular parallel lines are positioned at second end of those directions X line part things.
9. memory as claimed in claim 4, wherein:
This group nido annular parallel line comprises a plurality of the first and second annular parallel lines with a plurality of relative L type part things, and those L type part things have several gaps along those Y traverse line part things, and those first and second annular parallel lines are adjacent one another are;
Those first annular parallel lines comprise a plurality of first and second directions X line part things and the first and second Y traverse line part things; Whenever this first and second directions Xs line part thing has first end and second end; The one Y traverse line part thing is positioned at first end of this first directions X line part thing, and the 2nd Y traverse line part thing is positioned at second end of this second directions X line part thing; And
Those second annular parallel lines comprise a plurality of third and fourth directions X line part things and the third and fourth Y traverse line part thing; Whenever this third and fourth directions X line part thing has first end and second end; The 3rd Y traverse line part thing is positioned at second end of the 3rd directions X line part thing, and the 4th Y traverse line part thing is positioned at first end of the 4th directions X line part thing.
10. memory as claimed in claim 1, wherein this second spacing is at least 6 times of this first spacing.
11. memory as claimed in claim 1, wherein those lines form with photolithographicallpatterned, and those contact zones have lithographic dimensioned.
12. a multiple patterning method that in gold-tinted photoetch integrated circuit processing step, is used for making integrated circuit memory comprises:
Be that one group of first wire material selected one group of line pattern;
On a substrate, form and to organize first wire material; This each first wire material of organizing in first wire material defines the pattern with a directions X part thing and a Y steering portion thing, and the length of this directions X part thing of those first wire materials is longer than the length of those Y steering portion things of those first wire materials in fact;
Select a plurality of first spacings and second spacing for those directions X part things and those Y steering portion things, this second spacing is greater than this first spacing, and those directions X part things are parallel, and those Y steering portion things are parallel;
Formation is parallel at least two second wire materials of each first wire material, and to produce a plurality of word lines that comprise a plurality of parallel directions X line part things and a plurality of parallel Y traverse line part things, second wire material of those Y traverse line part things comprises a plurality of bottom district; And
Form a plurality of supplementary features things (supplemental features) in those bottom districts at least partly.
13. method as claimed in claim 12, wherein those lines comprise a plurality of word lines or a plurality of bit line.
14. method as claimed in claim 12, wherein the formation step of these at least two second wire materials also comprises:
Form 2 second wire materials and be parallel to each first wire material; And
Form 2 the 3rd wire materials and be parallel to each second wire material to make those lines.
15. method as claimed in claim 12, wherein those parallel line patterns are selected step to be included as one group of parallel first wire material of nido annular and are selected one group of nido annular parallel line pattern.
16. method as claimed in claim 12 comprises that also the Y traverse line part thing that removes at least partly is to make this bottom district.
17. method as claimed in claim 12, wherein one in those first wire materials be defined as following at least one: a continuous rectangle, have a gap (gap) of one in those Y steering portion things a rectangle, have (both) simultaneously along the rectangle in a gap of those Y steering portion things and have an only rectangle of a Y steering portion thing.
18. method as claimed in claim 12, wherein those length of those directions X line part things are 30 times of those length of those Y traverse line part things at least.
19. method as claimed in claim 12, wherein this second spacing is at least four times of this first spacing.
20. method as claimed in claim 12, wherein this second spacing is at least the octuple of this first spacing.
21. method as claimed in claim 12, wherein those supplementary features things formation steps comprise the contact zone that forms a plurality of expansions.
22. method as claimed in claim 16 also is included in to remove and forms a conductor material after the step.
23. method as claimed in claim 22, wherein a plurality of first conductor materials and a plurality of second conductor material are formed in the zone that is surrounded by those second wire materials.
24. method as claimed in claim 22, wherein a plurality of first conductor materials and a plurality of second conductor material are formed on the outside and a plurality of relative edge in a zone that is surrounded by those second wire materials.
25. method as claimed in claim 22, wherein this conductor material comprises a circuit interconnect (circuit interconnect line).
26. method as claimed in claim 12, wherein the formation step of this supplementary features thing is after those bottom districts form a plurality of contact zones.
27. a multiple patterning method that in gold-tinted photoetch integrated circuit processing step, is used for making line comprises:
Be that one group of parallel first wire material is selected one group of parallel line pattern;
On a substrate, form and to organize parallel first wire material; This each first wire material of organizing parallel first wire material defines the pattern with a directions X part thing and a Y steering portion thing, and the length of this directions X part thing of those first wire materials is at least 30 times of length of those Y steering portion things of this first wire material;
Select a plurality of first spacings and second spacing for those directions X part things and those Y steering portion things, this second spacing is at least 3 times of this first spacing, and those directions X part things are parallel, and those Y steering portion things are parallel;
Formation is parallel at least two second wire materials of each first wire material; To produce a plurality of word/bit lines that comprise a plurality of parallel directions X words/bit line portion thing and a plurality of parallel Y direction words/bit line portion thing, those Y direction word/bit line portion things comprise a plurality of bottom district;
Form the contact zone of a plurality of expansions in those bottom districts; And
Form a conductor material.
28. method as claimed in claim 27; Wherein this conductor material comprises and forms a plurality of first conductor wire materials and a plurality of second conductor wire material in the zone that (1) is surrounded by at least two second wire materials, or on the outside and a plurality of relative edge in a zone that is surrounded by this at least two second wire material in (2).
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| CN201110032839XA CN102623448A (en) | 2011-01-26 | 2011-01-26 | Multiple patterning method |
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| CN201110032839XA CN102623448A (en) | 2011-01-26 | 2011-01-26 | Multiple patterning method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070215874A1 (en) * | 2006-03-17 | 2007-09-20 | Toshiharu Furukawa | Layout and process to contact sub-lithographic structures |
| CN101090121A (en) * | 2006-06-16 | 2007-12-19 | 株式会社东芝 | Semiconductor device and a manufacturing method thereof |
| US20080006869A1 (en) * | 2006-06-27 | 2008-01-10 | Takeshi Kamigaichi | Nonvolatile semiconductor memory |
-
2011
- 2011-01-26 CN CN201110032839XA patent/CN102623448A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070215874A1 (en) * | 2006-03-17 | 2007-09-20 | Toshiharu Furukawa | Layout and process to contact sub-lithographic structures |
| CN101090121A (en) * | 2006-06-16 | 2007-12-19 | 株式会社东芝 | Semiconductor device and a manufacturing method thereof |
| US20080006869A1 (en) * | 2006-06-27 | 2008-01-10 | Takeshi Kamigaichi | Nonvolatile semiconductor memory |
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Application publication date: 20120801 |