CN102623048A - Nonvolatile memory cell and data programming, reading and erasure method thereof - Google Patents
Nonvolatile memory cell and data programming, reading and erasure method thereof Download PDFInfo
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- CN102623048A CN102623048A CN2011100300534A CN201110030053A CN102623048A CN 102623048 A CN102623048 A CN 102623048A CN 2011100300534 A CN2011100300534 A CN 2011100300534A CN 201110030053 A CN201110030053 A CN 201110030053A CN 102623048 A CN102623048 A CN 102623048A
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Abstract
The invention discloses a nonvolatile memory cell and a data programming, reading and erasure method thereof. The nonvolatile memory cell comprises a transistor, wherein the transistor comprises a drain electrode, a source electrode, a grid electrode and a substrate; the grid electrode is connected to a word line; the drain electrode is connected to a bit line; the source electrode is connected to a source line; and the substrate is connected to a substrate line. The nonvolatile memory cell and a manufacturing method thereof are completely compatible with the existing logical technology, especially with a deep submicron logical technology. An area of the nonvolatile memory cell can be reduced with reduction of the minimum processing size of a logical technology.
Description
Technical field
The present invention relates generally to semiconductor storage unit, relates in particular to a kind of non-volatile memory cells and data programing thereof, reads, method for deleting.
Background technology
Nonvolatile memory chip is widely used in electronic product, computing machine, communication device, consumer electronics and other to be needed in the application that the data power down preserves.Nonvolatile memory comprises polytype, and wherein, EPROM, flash memory types such as (Flash Memory) all have programming and erase function.
Summary of the invention
In view of this; The object of the present invention is to provide a kind of non-volatile memory cells and data programing thereof, read, method for deleting; Itself and existing logic process especially deep-submicron logic process are compatible fully, and the area of storage unit can dwindling and dwindle with technology.
According to an aspect of the present invention, a kind of non-volatile memory cells is provided,
Comprise transistor,
Said transistor comprises: drain electrode, source electrode, grid and substrate, wherein,
Said grid is connected with word line;
Said drain electrode is connected with bit line;
Said source electrode is connected with the source line;
Said substrate is connected with substrate lines.
According to a characteristic of the present invention,
Said transistor comprises:
First heavily doped region, second heavily doped region, polysilicon layer, substrate, asymmetric light doping section, first side wall, second side wall and silicon oxide layer; Wherein,
Said silicon oxide layer is positioned on the said substrate;
Said polysilicon layer, said first side wall, said second side wall all are positioned on the said silicon oxide layer;
Said first side wall, said second side wall lay respectively at the both sides of said silicon oxide layer;
Said asymmetric light doping section is adjacent to said second heavily doped region and said silicon oxide layer.
According to another characteristic of the present invention,
Said first side wall is positioned on said first, second drain electrode, is used for stored charge.
According to another characteristic of the present invention,
The thickness of said silicon oxide layer equals the thickness of the transistorized silicon oxide layer of thick grid oxygen under the standard semiconductor logic process.
According to a further aspect in the invention, a kind of data programing method of non-volatile memory cells is provided, wherein,
Said non-volatile memory cells comprises transistor,
Said transistor comprises: drain electrode, source electrode, grid and substrate, wherein,
Said grid is connected with word line;
Said drain electrode is connected with bit line;
Said source electrode is connected with the source line;
Said substrate is connected with substrate lines;
Said programmed method comprises:
On word line, apply word line program voltage;
On bit line, apply bit line program voltage;
On the line of source, apply source line program voltage;
On substrate lines, apply the substrate lines program voltage.
According to a characteristic of the present invention,
The preliminary setting data storage rule is programmed to said non-volatile memory cells according to the data storage rule and to be realized the storage of data.
According to another characteristic of the present invention,
Said data storage rule comprises:
To transistor 1 programming expression storage data " 1 ", not to transistor 1 programming expression storage data " 0 "; Perhaps
To transistor 1 programming expression storage data " 0 ", not to transistor 1 programming expression storage data " 1 ".
According to another characteristic of the present invention,
Conducting electric current between the transistorized source-drain electrode of process programming is less than initial conducting electric current;
Do not equal initial conducting electric current through the conducting electric current between the transistorized source-drain electrode of programming.
According to a further aspect in the invention, a kind of method for reading data of non-volatile memory cells is provided, wherein,
Said non-volatile memory cells comprises the first transistor,
Said the first transistor comprises: first drain electrode, first source electrode, first grid and first substrate, wherein,
Said first grid is connected with word line;
Said first drain electrode is connected with bit line;
Said first source electrode is connected with the source line;
Said first substrate is connected with substrate lines;
Said read method comprises:
On word line, apply word line read voltage;
On bit line, apply bit line and read voltage;
On the line of source, apply the source line and read voltage;
On substrate lines, apply substrate lines and read voltage;
Through the conducting electric current between the source-drain electrode that detects said the first transistor, confirm the data of storing in the non-volatile memory cells.
According to a characteristic of the present invention,
Reference unit is read in setting;
The said reference unit that reads comprises transistor seconds,
Said transistor seconds comprises: second drain electrode, second source electrode, second grid and second substrate, wherein,
Said second grid is connected with word line;
Said second drain electrode is connected with reference bit lines;
Said second source electrode is connected with the reference source line;
Said second substrate is connected with substrate lines;
Through said reference bit lines is applied predetermined voltage; Make conducting electric current between the source-drain electrode of said transistor seconds less than not through the conducting electric current between the source-drain electrode of the first transistor of programming, but greater than through the conducting electric current between the source-drain electrode of the first transistor of programming.
According to another characteristic of the present invention,
Through the conducting electric current between more said first, second transistorized source-drain electrode, confirm the data of storing in the non-volatile memory cells.
According to another characteristic of the present invention,
Selected cell is set, and said selected cell comprises input end and at least two output terminals, wherein,
Apply the source line at said input end and read voltage;
The corresponding connection of a root line in each output terminal and the Nonvolatile storage array;
Said selected cell is used for selecting the said Nonvolatile storage array of conducting need carry out the source line of the said non-volatile memory cells that data read.
According to a further aspect in the invention, a kind of method for deleting of non-volatile memory cells is provided, wherein,
Said non-volatile memory cells comprises transistor,
Said transistor comprises: drain electrode, source electrode, grid and substrate, wherein,
Said grid is connected with word line;
Said drain electrode is connected with bit line;
Said source electrode is connected with the source line;
Said substrate is connected with substrate lines;
Said method for deleting comprises:
On word line, apply word line erase voltage;
On bit line, apply bit line erase voltage;
On the line of source, apply source line erasing voltage;
On substrate lines, apply the substrate lines erasing voltage; Wherein,
Conducting electric current through between the said transistorized source-drain electrode of wiping equals initial conducting electric current.
Non-volatile memory cells of the present invention and data programing thereof, read, method for deleting; Compatible fully with existing logic process especially deep-submicron logic process, the area of the non-volatile memory cells among the present invention can dwindling and dwindle with existing logic process.Non-volatile memory cells among the present invention utilizes the transistorized side wall stored charge of asymmetric light doping section; Through the conducting resistance between the source-drain electrode that how much comes the control store unit of stored charge of control side wall; Changing the conducting electric current between the transistorized source-drain electrode in the storage unit, thereby can confirm the data of storing through the difference of the conducting electric current between a plurality of transistorized source-drain electrode of storage unit relatively.
Description of drawings
Fig. 1 is the transistorized structural drawing of the thick grid oxygen of the standard of logic-based technology;
Fig. 2 is as the transistorized structural drawing of non-volatile memory cells in the embodiment of the invention;
Fig. 3 is the structural drawing of non-volatile memory cells in the embodiment of the invention;
Fig. 4 is for carrying out the synoptic diagram of data programing in the embodiment of the invention to non-volatile memory cells;
Fig. 5 carries out the synoptic diagram that data read in the embodiment of the invention to non-volatile memory cells;
Fig. 6 carries out the synoptic diagram that data read in the embodiment of the invention to non-volatile memory cells;
Fig. 7 is for carrying out the synoptic diagram of data erase in the embodiment of the invention to non-volatile memory cells.
Embodiment
Describe specific embodiment of the present invention in detail below in conjunction with accompanying drawing.
Fig. 1 is the transistorized structural drawing of the thick grid oxygen of the standard of logic-based technology, and among Fig. 1, the thick grid oxygen of standard transistor comprises:
First heavily doped region 101, second heavily doped region 102, polysilicon layer 103, substrate 104, first light doping section 105, second light doping section 106, first side wall 107, second side wall 108 and silicon oxide layer 109.
Can know that according to Fig. 1 the thick grid oxygen of standard transistor comprises first light doping section 105, second light doping section 106 of symmetry.Wherein, first heavily doped region 101, second heavily doped region 102 are N type heavily doped region, and substrate 104 is a P type trap.The thick grid oxygen of standard transistor is used to realize imput output circuit in logic process.Under 0.13 micron semiconductor fabrication process, the thickness of the transistorized silicon oxide layer 109 of the thick grid oxygen of standard is generally the 6-8 nanometer.Under different semiconductor fabrication process, the thickness of the transistorized silicon oxide layer 109 of the thick grid oxygen of standard is also different.
Fig. 2 be in the embodiment of the invention as the transistorized structural drawing of non-volatile memory cells, among Fig. 2, the transistor as non-volatile memory cells in the embodiment of the invention comprises:
First heavily doped region 201, second heavily doped region 202, polysilicon layer 203, substrate 204, light doping section 205, first side wall 206, second side wall 207 and silicon oxide layer 208.Wherein,
The thickness of silicon oxide layer 208 equals the thickness of the transistorized silicon oxide layer of thick grid oxide layer under the standard semiconductor logic process.
Can know that according to Fig. 2 the transistor as non-volatile memory cells in the embodiment of the invention only comprises light doping section 205, belong to asymmetric light doping section transistor npn npn.
There are not first side wall of light doping section, 206 places with being arranged at as the transistorized storage area of non-volatile memory cells in the embodiment of the invention; Promptly adopt first side wall, 206 stored charges; Control as the conducting resistance between the transistorized source-drain electrode of non-volatile memory cells through controlling first side wall, 206 charge stored numbers; With the conducting size of current between the transistorized source-drain electrode that changes non-volatile memory cells, thereby can confirm the data of storing according to the conducting size of current between the transistorized source-drain electrode of non-volatile memory cells.
Transistor as non-volatile memory cells in the embodiment of the invention passes through to use asymmetric light doping section, has not only reduced program erase voltage, and has improved program erase speed.
Fig. 3 is the structural drawing of non-volatile memory cells in the embodiment of the invention, and among Fig. 3, non-volatile memory cells is made up of transistor 1, and transistor 1 comprises: drain D, source S, grid G and substrate B.
In the non-volatile memory cells, the grid G of transistor 1 and word line (WL, Word Line) connect in embodiments of the present invention; The drain D of transistor 1 and bit line (BL; Bit Line) connect, the source S of transistor 1 and source line (SL, Source Line) connect; The substrate B of transistor 1 and substrate lines (SUBL, Substrate Line) connect.
In the non-volatile memory cells, can pass through the preliminary setting data storage rule in embodiments of the present invention, promptly how transistor 1 programmed and realize the storage of data " 0 " and " 1 ".For example, to transistor 1 programming expression storage data " 1 ", not to transistor 1 programming expression storage data " 0 "; Perhaps to transistor 1 programming expression storage data " 0 ", not to transistor 1 programming expression storage data " 1 ".
For the ease of understanding; Below with expression storage data " 1 " that transistor 1 is programmed; To transistor 1 programming expression storage data " 0 " as predefined storage rule, in the embodiment of the invention to the data programing of non-volatile memory cells, read with erase process and be described in detail.Certainly; The designer also can be with expression storage data " 0 " that transistor 1 is programmed; To transistor 1 programming expression storage data " 1 " as predefined storage rule, realize to non-volatile memory cells in the embodiment of the invention data programing, read and wipe.
Fig. 4 is for carrying out the synoptic diagram of data programing in the embodiment of the invention to non-volatile memory cells, the non-volatile memory cells among Fig. 4 is made up of transistor A, wherein,
On word line WL0, apply word line program voltage V
WL0
On bit line BL0, apply bit line program voltage V
BL0
On the line SL0 of source, apply source line program voltage V
SL0
On substrate lines SUBL, apply substrate lines program voltage V
SUBLWherein,
As bit line program voltage V
BL0=4V, word line program voltage V
WL0=4V, source line program voltage V
SL0==0V, substrate lines program voltage V
SUBLDuring=0V, be illustrated in and apply the big or small bit line program voltage V of 4V that is on the bit line BL0 that is connected with the drain electrode of transistor A
BL0, at bit line program voltage V
BL0Effect under, electronics is injected into the side wall that is positioned at a side that does not have light doping section above the transistor A drain electrode, increase the conducting resistance between the transistor A source-drain electrode, thereby reduce the conducting electric current I between the source-drain electrode of transistor A
A
Among Fig. 4, comprise also and read reference unit that this reads reference unit and is made up of transistor R,
Transistor R comprises: drain electrode, source electrode, grid and substrate, wherein,
Grid is connected with word line, and drain electrode is connected with reference bit lines, and source electrode is connected with the reference source line, and substrate is connected with substrate lines;
Through the reference bit lines with transistor R is applied predetermined voltage V
R, make the conducting electric current I between the transistor R source-drain electrode
RConducting electric current less than between the source-drain electrode of the transistor A that does not pass through programming is initial conducting electric current I
0, but greater than the conducting electric current I between the source-drain electrode of the transistor A that passes through programming
A, i.e. I
0＞I
R＞I
A
Fig. 5 carries out the synoptic diagram that data read in the embodiment of the invention to non-volatile memory cells,
For the transistor A in the non-volatile memory cells,
On word line WL0, apply word line read voltage V '
WL0
On bit line BL0, apply bit line and read voltage V '
BL0
On the line SL0 of source, apply the source line and read voltage V '
SL0
On substrate lines SUBL, apply substrate lines and read voltage V '
SUBL
Read the transistor R in the reference unit for conduct,
On word line WL0, apply word line read voltage V '
WL0
On reference bit lines BLR, apply bit line and read voltage V
BLR
On reference source line SLR, apply the source line and read voltage V
SLR
On substrate lines SUBL, apply substrate lines and read voltage V '
SUBL
For example, bit line reads voltage V '
BL0=V
BLR=0V, word line read voltage V '
WL0=2.5V, the source line reads voltage V '
SL0=V
SLR=2.5V, substrate lines reads voltage V '
SUBL=0V, wherein,
If detect through the conducting electric current I between the source-drain electrode of transistor A of programming through sense amplifier
ALess than the conducting electric current I between the transistor R source-drain electrode
R, i.e. I
A＜I
R, think that then the data of storing in the non-volatile memory cells are " 1 ".
If detect not through the conducting electric current I between the source-drain electrode of the transistor A of programming through sense amplifier
0Greater than the conducting electric current I between the transistor R source-drain electrode
R, i.e. I
0＞I
R, think that then the data of storing in the non-volatile memory cells are " 0 ".
By the way, read data in the non-volatile memory cells that constitutes by transistor A.
In addition, for the Nonvolatile storage array that forms by a plurality of non-volatile memory cells, be provided with in can the every row in this Nonvolatile storage array and read reference unit.
Fig. 6 carries out the synoptic diagram that data read in the embodiment of the invention to non-volatile memory cells; Among Fig. 6; Can be through selected cell 601 be set, be used for selecting the conducting Nonvolatile storage array need carry out the source line of the non-volatile memory cells that data read.Selected cell 601 comprises input end and at least two output terminals, wherein, applies the source line at input end and reads voltage V '
SL, the corresponding connection of a root line in each output terminal and the Nonvolatile storage array.Among Fig. 6, when needs read the data in the non-volatile memory cells that is made up of transistor A, the source line of the non-volatile memory cells that selected cell 601 will be selected to be made up of transistor A in the conducting Nonvolatile storage array.
Fig. 7 is for carrying out the synoptic diagram of data erase in the embodiment of the invention to non-volatile memory cells, the non-volatile memory cells among Fig. 7 comprises transistor A and transistor B, wherein,
On word line WL0, apply word line erase voltage V "
WL0
On bit line BL0, apply bit line erase voltage V "
BL0
On the line SL0 of source, apply source line erasing voltage V "
SL0
On substrate lines SUBL, apply substrate lines erasing voltage V "
SUBL
For example, the non-volatile memory cells of storage data " 1 " is wiped, made bit line erase voltage V "
BL0=4V, word line erase voltage V "
WL0=-4V, source line erasing voltage V "
SL0=0V, substrate lines erasing voltage V "
SUBL=0V; Wherein,
As bit line erase voltage V "
BL0=4V, word line erase voltage V "
WL0=-4V, source line erasing voltage V "
SL0=0V, substrate lines erasing voltage V "
SUBLDuring=0V, be illustrated in and apply size on the bit line BL0 that is connected with the drain electrode of transistor A and be the bit line erase voltage V of 4V "
BL0, at bit line erasing voltage V "
BL0Effect under, the hole is injected into the side wall that is positioned at a side that does not have light doping section above the transistor A drain electrode, in programming process in injected electrons in the side wall on transistor A drain electrode, make the conducting electric current I between the source-drain electrode of transistor A
ARevert to initial conducting electric current I
0, according to the storage rule of above-mentioned predetermined set, promptly to transistor 1 programming expression storage data " 1 ", not to transistor 1 programming expression storage data " 0 ".Therefore, because the conducting electric current between the source-drain electrode of transistor A reverts to initial conducting electric current I
0, this initial conducting electric current I
0Greater than the conducting electric current I between the transistor R source-drain electrode
R, think that then the data of storing in the non-volatile memory cells are " 0 ", the data " 1 " that are about to store in the non-volatile memory cells are wiped.
Among the invention described above embodiment; Though 0.13 micron the logic process that with the WV is 3.3V is an example; To data programmings, read with erase process in each voltage be provided with; But be not limited to the present invention, along with the variation of logic process, data programing, read with erase process in above-mentioned each voltage can change with the variation of WV.Wherein,
Each voltage in the data programing process comprises: word line program voltage V
WL0, bit line program voltage V
BL0, source line program voltage V
SL0, substrate lines program voltage V
SUBL
Each voltage in the data read process comprises: word line read voltage V '
WL0, bit line reads voltage V '
BL0, reference bit lines reads voltage V
BLR, the source line reads voltage V '
SL0, the reference source line reads voltage V
SLR, substrate lines reads voltage V '
SUBL
Each voltage in the data erasing process comprises: word line erase voltage V "
WL0, bit line erase voltage V "
BL0, source line erasing voltage V "
SL0, substrate lines erasing voltage V "
SUBL
The above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification, the change that the embodiment of the invention is done, make up, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. a non-volatile memory cells is characterized in that, comprises transistor,
Said transistor comprises: drain electrode, source electrode, grid and substrate, wherein,
Said grid is connected with word line;
Said drain electrode is connected with bit line;
Said source electrode is connected with the source line;
Said substrate is connected with substrate lines.
2. non-volatile memory cells according to claim 1 is characterized in that,
Said transistor comprises:
First heavily doped region, second heavily doped region, polysilicon layer, substrate, asymmetric light doping section, first side wall, second side wall and silicon oxide layer; Wherein,
Said silicon oxide layer is positioned on the said substrate;
Said polysilicon layer, said first side wall, said second side wall all are positioned on the said silicon oxide layer;
Said first side wall, said second side wall lay respectively at the both sides of said silicon oxide layer;
Said asymmetric light doping section is adjacent to said second heavily doped region and said silicon oxide layer.
3. non-volatile memory cells according to claim 1 is characterized in that,
Said first side wall is positioned on said first, second drain electrode, is used for stored charge.
4. non-volatile memory cells according to claim 1 is characterized in that,
The thickness of said silicon oxide layer equals the thickness of the transistorized silicon oxide layer of thick grid oxygen under the standard semiconductor logic process.
5. the data programing method of a non-volatile memory cells is characterized in that,
Said non-volatile memory cells comprises transistor,
Said transistor comprises: drain electrode, source electrode, grid and substrate, wherein,
Said grid is connected with word line;
Said drain electrode is connected with bit line;
Said source electrode is connected with the source line;
Said substrate is connected with substrate lines;
Said programmed method comprises:
On word line, apply word line program voltage;
On bit line, apply bit line program voltage;
On the line of source, apply source line program voltage;
On substrate lines, apply the substrate lines program voltage.
6. data programing method according to claim 5 is characterized in that,
The preliminary setting data storage rule is programmed to said non-volatile memory cells according to the data storage rule and to be realized the storage of data.
7. data programing method according to claim 5 is characterized in that,
Said data storage rule comprises:
To transistor 1 programming expression storage data " 1 ", not to transistor 1 programming expression storage data " 0 "; Perhaps
To transistor 1 programming expression storage data " 0 ", not to transistor 1 programming expression storage data " 1 ".
8. data programing method according to claim 5 is characterized in that,
Conducting electric current between the transistorized source-drain electrode of process programming is less than initial conducting electric current;
Do not equal initial conducting electric current through the conducting electric current between the transistorized source-drain electrode of programming.
9. the method for reading data of a non-volatile memory cells is characterized in that,
Said non-volatile memory cells comprises the first transistor,
Said the first transistor comprises: first drain electrode, first source electrode, first grid and first substrate, wherein,
Said first grid is connected with word line;
Said first drain electrode is connected with bit line;
Said first source electrode is connected with the source line;
Said first substrate is connected with substrate lines;
Said read method comprises:
On word line, apply word line read voltage;
On bit line, apply bit line and read voltage;
On the line of source, apply the source line and read voltage;
On substrate lines, apply substrate lines and read voltage;
Through the conducting electric current between the source-drain electrode that detects said the first transistor, confirm the data of storing in the non-volatile memory cells.
10. method for reading data according to claim 9 is characterized in that,
Reference unit is read in setting;
The said reference unit that reads comprises transistor seconds,
Said transistor seconds comprises: second drain electrode, second source electrode, second grid and second substrate, wherein,
Said second grid is connected with word line;
Said second drain electrode is connected with reference bit lines;
Said second source electrode is connected with the reference source line;
Said second substrate is connected with substrate lines;
Through said reference bit lines is applied predetermined voltage; Make conducting electric current between the source-drain electrode of said transistor seconds less than not through the conducting electric current between the source-drain electrode of the first transistor of programming, but greater than through the conducting electric current between the source-drain electrode of the first transistor of programming.
11. method for reading data according to claim 10 is characterized in that,
Through the conducting electric current between more said first, second transistorized source-drain electrode, confirm the data of storing in the non-volatile memory cells.
12. method for reading data according to claim 9 is characterized in that,
Selected cell is set, and said selected cell comprises input end and at least two output terminals, wherein,
Apply the source line at said input end and read voltage;
The corresponding connection of a root line in each output terminal and the Nonvolatile storage array;
Said selected cell is used for selecting the said Nonvolatile storage array of conducting need carry out the source line of the said non-volatile memory cells that data read.
13. the method for deleting of a non-volatile memory cells is characterized in that,
Said non-volatile memory cells comprises transistor,
Said transistor comprises: drain electrode, source electrode, grid and substrate, wherein,
Said grid is connected with word line;
Said drain electrode is connected with bit line;
Said source electrode is connected with the source line;
Said substrate is connected with substrate lines;
Said method for deleting comprises:
On word line, apply word line erase voltage;
On bit line, apply bit line erase voltage;
On the line of source, apply source line erasing voltage;
On substrate lines, apply the substrate lines erasing voltage; Wherein,
Conducting electric current through between the said transistorized source-drain electrode of wiping equals initial conducting electric current.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102354528A (en) * | 2011-07-13 | 2012-02-15 | 北京兆易创新科技有限公司 | Nonvolatile memory cell, and data programming, reading and erasing methods therefor |
| CN109427793A (en) * | 2017-08-25 | 2019-03-05 | 亿而得微电子股份有限公司 | The electronics write-in formula of erasing of low-voltage difference can make carbon copies read-only memory and operating method |
| CN114765042A (en) * | 2021-09-28 | 2022-07-19 | 杭州存对半导体技术有限公司 | Single-tube nonvolatile memory cell array with paired structure and operation method thereof |
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| US6163482A (en) * | 1999-08-19 | 2000-12-19 | Worldwide Semiconductor Manufacturing Corporation | One transistor EEPROM cell using ferro-electric spacer |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102354528A (en) * | 2011-07-13 | 2012-02-15 | 北京兆易创新科技有限公司 | Nonvolatile memory cell, and data programming, reading and erasing methods therefor |
| CN109427793A (en) * | 2017-08-25 | 2019-03-05 | 亿而得微电子股份有限公司 | The electronics write-in formula of erasing of low-voltage difference can make carbon copies read-only memory and operating method |
| CN109427793B (en) * | 2017-08-25 | 2020-08-21 | 亿而得微电子股份有限公司 | Low voltage difference electronic writing-erasing type rewritable read-only memory and operation method |
| CN114765042A (en) * | 2021-09-28 | 2022-07-19 | 杭州存对半导体技术有限公司 | Single-tube nonvolatile memory cell array with paired structure and operation method thereof |
| CN114765042B (en) * | 2021-09-28 | 2023-08-01 | 杭州领开半导体技术有限公司 | Single-tube nonvolatile memory cell array of pairing structure and operation method thereof |
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