CN102623048A - Nonvolatile memory cell and data programming, reading and erasure method thereof - Google Patents
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Abstract
The invention discloses a nonvolatile memory cell and a data programming, reading and erasure method thereof. The nonvolatile memory cell comprises a transistor, wherein the transistor comprises a drain electrode, a source electrode, a grid electrode and a substrate; the grid electrode is connected to a word line; the drain electrode is connected to a bit line; the source electrode is connected to a source line; and the substrate is connected to a substrate line. The nonvolatile memory cell and a manufacturing method thereof are completely compatible with the existing logical technology, especially with a deep submicron logical technology. An area of the nonvolatile memory cell can be reduced with reduction of the minimum processing size of a logical technology.
Description
Technical Field
The present invention relates generally to semiconductor memory devices, and more particularly to a nonvolatile memory cell and data programming, reading, and erasing methods thereof.
Background
Non-volatile memory chips are widely used in electronic products, computers, communication devices, consumer electronics, and other applications requiring power-down storage of data. The non-volatile Memory includes various types, wherein the types of EPROM, Flash Memory, and the like have programming and erasing functions.
Disclosure of Invention
It is therefore an objective of the present invention to provide a nonvolatile memory cell and a data programming, reading and erasing method thereof, which are fully compatible with the existing logic process, especially the deep submicron logic process, and the area of the memory cell can be reduced with the reduction of the process.
According to an aspect of the present invention, there is provided a nonvolatile memory cell,
comprises a transistor and a plurality of transistors, wherein,
the transistor includes: a drain, a source, a gate, and a substrate, wherein,
the grid is connected with a word line;
the drain electrode is connected with a bit line;
the source electrode is connected with a source line;
the substrate is connected to a substrate line.
In accordance with one feature of the present invention,
the transistor includes:
the silicon substrate comprises a first heavily doped region, a second heavily doped region, a polycrystalline silicon layer, a substrate, an asymmetric lightly doped region, a first side wall, a second side wall and a silicon oxide layer; wherein,
the silicon oxide layer is positioned on the substrate;
the polycrystalline silicon layer, the first side wall and the second side wall are all positioned on the silicon oxide layer;
the first side wall and the second side wall are respectively positioned on two sides of the silicon oxide layer;
the asymmetric lightly doped region is adjacent to the second heavily doped region and the silicon oxide layer.
In accordance with a further feature of the present invention,
the first side wall is positioned above the first drain electrode and the second drain electrode and used for storing electric charges.
In accordance with a further feature of the present invention,
the thickness of the silicon oxide layer is equal to that of the silicon oxide layer of the thick gate oxide transistor under the standard semiconductor logic process.
According to another aspect of the present invention, there is provided a data programming method of a nonvolatile memory cell, wherein,
the non-volatile memory cell includes a transistor,
the transistor includes: a drain, a source, a gate, and a substrate, wherein,
the grid is connected with a word line;
the drain electrode is connected with a bit line;
the source electrode is connected with a source line;
the substrate is connected with a substrate line;
the programming method comprises the following steps:
applying a word line programming voltage on a word line;
applying a bit line programming voltage on the bit line;
applying a source line programming voltage on a source line;
a substrate line programming voltage is applied on the substrate line.
In accordance with one feature of the present invention,
presetting a data storage rule, and programming the nonvolatile memory unit according to the data storage rule to realize data storage.
In accordance with a further feature of the present invention,
the data storage rules include:
In accordance with a further feature of the present invention,
the conduction current between the source and the drain of the programmed transistor is smaller than the initial conduction current;
the on-current between the source and drain of the unprogrammed transistor is equal to the initial on-current.
According to another aspect of the present invention, there is provided a data reading method of a nonvolatile memory cell, wherein,
the non-volatile memory cell includes a first transistor,
the first transistor includes: a first drain, a first source, a first gate, and a first substrate,
the first grid is connected with a word line;
the first drain electrode is connected with a bit line;
the first source electrode is connected with a source line;
the first substrate is connected with a substrate line;
the reading method comprises the following steps:
applying a word line read voltage on a word line;
applying a bit line read voltage on the bit line;
applying a source line read voltage on a source line;
applying a substrate line read voltage on the substrate line;
and determining data stored in the nonvolatile memory cell by detecting the conduction current between the source and the drain of the first transistor.
In accordance with one feature of the present invention,
setting a reading reference unit;
the read reference cell includes a second transistor,
the second transistor includes: a second drain, a second source, a second gate, and a second substrate, wherein,
the second grid is connected with a word line;
the second drain electrode is connected with a reference bit line;
the second source electrode is connected with a reference source line;
the second substrate is connected with the substrate line;
and applying a preset voltage to the reference bit line to enable the conduction current between the source and the drain of the second transistor to be smaller than the conduction current between the source and the drain of the first transistor which is not programmed but larger than the conduction current between the source and the drain of the first transistor which is programmed.
In accordance with a further feature of the present invention,
and determining data stored in the nonvolatile memory cell by comparing the conduction current between the source and drain electrodes of the first and second transistors.
In accordance with a further feature of the present invention,
a selection unit is provided, said selection unit comprising an input and at least two outputs, wherein,
applying a source line read voltage at the input;
each output end is correspondingly connected with one source line in the nonvolatile memory array;
the selection unit is used for selecting and conducting a source line of the nonvolatile memory unit which needs to read data in the nonvolatile memory array.
According to another aspect of the present invention, there is provided an erasing method of a nonvolatile memory cell, wherein,
the non-volatile memory cell includes a transistor,
the transistor includes: a drain, a source, a gate, and a substrate, wherein,
the grid is connected with a word line;
the drain electrode is connected with a bit line;
the source electrode is connected with a source line;
the substrate is connected with a substrate line;
the erasing method comprises the following steps:
applying a word line erase voltage on a word line;
applying a bit line erase voltage on the bit line;
applying a source line erase voltage on a source line;
applying a substrate line erase voltage on the substrate line; wherein,
and the conduction current between the source electrode and the drain electrode of the erased transistor is equal to the initial conduction current.
The nonvolatile memory unit and the data programming, reading and erasing method thereof are completely compatible with the existing logic process, particularly the deep submicron logic process, and the area of the nonvolatile memory unit in the invention can be reduced along with the reduction of the existing logic process. The nonvolatile memory cell utilizes the side walls of the transistors in the asymmetric lightly doped regions to store charges, controls the on-resistance between the source and the drain of the memory cell by controlling the amount of the stored charges of the side walls to change the on-current between the source and the drain of the transistors in the memory cell, and thus can determine the stored data by comparing the difference of the on-currents between the source and the drain of a plurality of transistors in the memory cell.
Drawings
FIG. 1 is a block diagram of a standard thick gate oxide transistor based logic process;
FIG. 2 is a diagram showing a structure of a transistor as a nonvolatile memory cell in the embodiment of the present invention;
FIG. 3 is a block diagram of a non-volatile memory cell in an embodiment of the present invention;
FIG. 4 is a schematic diagram of data programming of a non-volatile memory cell according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an embodiment of a method for reading data from a non-volatile memory cell;
FIG. 6 is a diagram illustrating an embodiment of a method for reading data from a non-volatile memory cell;
FIG. 7 is a diagram illustrating data erasing from a nonvolatile memory cell according to an embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a structural diagram of a standard thick gate oxide transistor based on a logic process, and in fig. 1, the standard thick gate oxide transistor includes:
a first heavily doped region 101, a second heavily doped region 102, a polysilicon layer 103, a substrate 104, a first lightly doped region 105, a second lightly doped region 106, a first sidewall 107, a second sidewall 108, and a silicon oxide layer 109.
As shown in fig. 1, the standard thick-gate oxide transistor includes a first lightly doped region 105 and a second lightly doped region 106 that are symmetrical. The first heavily doped region 101 and the second heavily doped region 102 are N-type heavily doped regions, and the substrate 104 is a P-type well. Standard thick-gate oxide transistors are used in logic processes to implement input-output circuits. The thickness of the silicon oxide layer 109 of a standard thick gate oxide transistor is typically 6-8 nanometers for a 0.13 micron semiconductor fabrication process. The thickness of the silicon oxide layer 109 of a standard thick-gate oxide transistor varies from semiconductor manufacturing process to semiconductor manufacturing process.
Fig. 2 is a structural diagram of a transistor as a nonvolatile memory cell in an embodiment of the present invention, and in fig. 2, the transistor as a nonvolatile memory cell in an embodiment of the present invention includes:
a first heavily doped region 201, a second heavily doped region 202, a polysilicon layer 203, a substrate 204, a lightly doped region 205, a first sidewall 206, a second sidewall 207, and a silicon oxide layer 208. Wherein,
a silicon oxide layer 208 is located on the substrate 204;
the polysilicon layer 203, the first side wall 206 and the second side wall 207 are all positioned on the silicon oxide layer 208;
the first sidewall 206 and the second sidewall 207 are respectively located at two sides of the silicon oxide layer 208;
the lightly doped region 205 is adjacent to the second heavily doped region 202 and the silicon oxide layer 208.
The thickness of the silicon oxide layer 208 is equal to the thickness of the silicon oxide layer of a thick gate oxide transistor under standard semiconductor logic processing.
As can be seen from fig. 2, the transistor as the nonvolatile memory cell in the embodiment of the present invention includes only the lightly doped region 205, and belongs to an asymmetric lightly doped region type transistor.
The storage region of the transistor serving as the nonvolatile memory cell in the embodiment of the present invention is disposed at the first sidewall 206 without the lightly doped region, that is, the first sidewall 206 is used to store charges, and the number of the charges stored in the first sidewall 206 is controlled to control the on-resistance between the source and the drain of the transistor serving as the nonvolatile memory cell, so as to change the magnitude of the on-current between the source and the drain of the transistor of the nonvolatile memory cell, thereby determining the stored data according to the magnitude of the on-current between the source and the drain of the transistor of the nonvolatile memory cell.
The transistor serving as the nonvolatile memory unit in the embodiment of the invention not only reduces the programming and erasing voltage, but also improves the programming and erasing speed by using the asymmetric lightly doped region.
Fig. 3 is a structural diagram of a nonvolatile memory cell in an embodiment of the present invention, in fig. 3, the nonvolatile memory cell is formed by a transistor 1, and the transistor 1 includes: drain electrode D, source electrode S, grid electrode G and substrate B.
In the nonvolatile memory cell in the embodiment of the present invention, the gate G of the transistor 1 is connected to a Word Line (WL, Word Line), the drain D of the transistor 1 is connected to a Bit Line (BL, Bit Line), the Source S of the transistor 1 is connected to a Source Line (SL), and the Substrate B of the transistor 1 is connected to a Substrate Line (SUBL).
In the nonvolatile memory cell in the embodiment of the present invention, the storage of data "0" and "1" can be realized by presetting a data storage rule, i.e., how to program the transistor 1. For example, programming transistor 1 means storing data "1", and not programming transistor 1 means storing data "0"; alternatively, programming transistor 1 means storing data "0" and not programming transistor 1 means storing data "1".
For convenience of understanding, the data programming, reading and erasing processes of the nonvolatile memory cell in the embodiment of the present invention will be described in detail below with reference to programming the transistor 1 to store data "1" and not programming the transistor 1 to store data "0" as a predetermined storage rule. Of course, the designer may also use the programming of the transistor 1 to represent the storage data "0" and not programming the transistor 1 to represent the storage data "1" as the preset storage rule to implement data programming, reading and erasing of the nonvolatile memory cell in the embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating data programming of a nonvolatile memory cell according to an embodiment of the present invention, the nonvolatile memory cell of fig. 4 is formed of a transistor a, wherein,
applying a word line programming voltage V on word line WL0WL0；
Applying a bit line programming voltage V on the bit line BL0BL0；
Applying a Source line Programming Voltage V on the Source line SL0SL0；
Applying a substrate line programming voltage V on the substrate line SUBLSUBL(ii) a Wherein,
when the bit line programming voltage VBL04V, word line programming voltage VWL0Source line programming voltage V4V SL00V, substrate line programming voltage VSUBLWhen the voltage is 0V, the bit line programming voltage V of 4V is applied to the bit line BL0 connected to the drain of the transistor aBL0On bit line programming voltage VBL0Under the action of the electron injection device, electrons are injected into the side wall on the side without the light doped region on the drain electrode of the transistor A, and the on-resistance between the source electrode and the drain electrode of the transistor A is increased, so that the on-current I between the source electrode and the drain electrode of the transistor A is reducedA。
In fig. 4, there is also included a read reference cell, which is constituted by a transistor R,
the transistor R includes: a drain, a source, a gate, and a substrate, wherein,
the grid is connected with the word line, the drain is connected with the reference bit line, the source is connected with the reference source line, and the substrate is connected with the substrate line;
by applying a predetermined voltage V to the reference bit line of the AND transistor RRTo make the conduction current I between the source and the drain of the transistor RRThe initial conduction current I is smaller than the conduction current between the source electrode and the drain electrode of the transistor A which is not programmed0But greater than the on-state current I between the source and drain of the programmed transistor AAI.e. I0＞IR＞IA。
FIG. 5 is a diagram illustrating a data read from a non-volatile memory cell according to an embodiment of the present invention,
for transistor a in a non-volatile memory cell,
a word line read voltage V 'is applied to word line WL 0'WL0；
Bit line read voltage V 'is applied to bit line BL 0'BL0；
Source line read voltage V 'is applied to the source line SL 0'SL0；
Substrate line read voltage V 'is applied to substrate line SUBL'SUBL；
For the transistor R to be in the read reference cell,
a word line read voltage V 'is applied to word line WL 0'WL0；
Applying a bit line read voltage V on a reference bit line BLRBLR；
Applying a source line read voltage V to the reference source line SLRSLR；
Applying a substrate on the substrate line SUBLLine read Voltage V'SUBL；
For example, bit line read voltage V'BL0＝V BLR0V, word line read voltage V'WL02.5V, Source line read Voltage V'SL0＝VSLR2.5V, substrate line read Voltage V'SUBL0V, wherein,
if the conduction current I between the source and the drain of the programmed transistor A is detected by a sensitive amplifierALess than the conduction current I between the source and drain of the transistor RRI.e. IA＜IRThe data stored in the nonvolatile memory cell is considered to be "1".
If the conduction current I between the source and the drain of the transistor A which is not programmed is detected by the sensitive amplifier0Greater than the conduction current I between the source and drain of the transistor RRI.e. I0＞IRThe data stored in the nonvolatile memory cell is considered to be "0".
In the above manner, data in the nonvolatile memory cell including the transistor a is read.
In addition, for a nonvolatile memory array formed of a plurality of nonvolatile memory cells, a read reference cell may be provided in each column in the nonvolatile memory array.
Fig. 6 is a schematic diagram illustrating data reading performed on a nonvolatile memory cell according to an embodiment of the present invention, and in fig. 6, a selection unit 601 may be provided for selecting and turning on a source line of a nonvolatile memory cell in a nonvolatile memory array, where data reading is required. The selection unit 601 includes an input terminal to which a source line read voltage V 'is applied and at least two output terminals'SLAnd each output end is correspondingly connected with one source line in the nonvolatile memory array. In fig. 6, when data needs to be read from a nonvolatile memory cell composed of a transistor a, a selection unit 601 will select to turn on a source line of the nonvolatile memory cell composed of the transistor a in the nonvolatile memory array.
Fig. 7 is a schematic diagram of data erasing a nonvolatile memory cell according to an embodiment of the present invention, where the nonvolatile memory cell in fig. 7 includes a transistor a and a transistor B, wherein,
a word line erase voltage V "is applied to word line WL0WL0；
A bit line erase voltage V "is applied to bit line BL0BL0；
A source line erase voltage V "is applied to the source line SL0SL0；
Applying a substrate line erase voltage V "on the substrate line SUBLSUBL；
For example, a nonvolatile memory cell storing data "1" is erased, and the bit line erase voltage V ″, is appliedBL0Word line erase voltage V ″', 4VWL0-4V, source line erase voltage V ″)SL00V, substrate line erase voltage V ″)SUBL0V; wherein,
when the bit line erase voltage V ″)BL0Word line erase voltage V ″', 4VWL0-4V, source line erase voltage V ″)SL00V, substrate line erase voltage V ″)SUBLWhen the voltage is 0V, the bit line erase voltage V ″, which is 4V, is applied to the bit line BL0 connected to the drain of the transistor aBL0At bit line erase voltage V ″)BL0Injecting holes into the side wall of the drain of the transistor A on the side without the lightly doped region, and neutralizing electrons injected into the side wall of the drain of the transistor A in the programming process to make the conduction current I between the source and the drain of the transistor AAIs restored to the initial on-state current I0According to the predetermined set storage rule, that is, programming the transistor 1 means storing data "1", and not programming the transistor 1 means storing data "0". Therefore, the on-state current between the source and drain of the transistor A is restored to the initial on-state current I0The initial on-state current I0Greater than the conduction current I between the source and drain of the transistor RRThen it is considered as notThe data stored in the volatile memory cell is "0", that is, the data "1" stored in the nonvolatile memory cell is erased.
In the above embodiment of the present invention, although the operation voltage of the logic process of 0.13 μm, which is 3.3V, is taken as an example to set the respective voltages in the data programming, reading and erasing processes, the invention is not limited thereto, and the respective voltages in the data programming, reading and erasing processes may be changed according to the change of the operation voltage as the logic process is changed. Wherein,
the various voltages during data programming include: word line programming voltage VWL0Bit line programming voltage VBL0Source line programming voltage VSL0Substrate line programming voltage VSUBL。
The various voltages during data read include: word line read voltage V'WL0Bit line read voltage V'BL0Reference bit line read voltage VBLRSource line read Voltage V'SL0Reference source line reading voltage VSLRSubstrate line read voltage V'SUBL。
The various voltages during data erase include: word line erase voltage V ″)WL0Bit line erase voltage V ″)BL0Source line erase voltage V ″)SL0Substrate line erase voltage V ″)SUBL。
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, and any modifications, alterations, combinations, equivalents, improvements and the like made to the embodiments of the present invention within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (13)
1. A non-volatile memory cell comprising a transistor,
the transistor includes: a drain, a source, a gate, and a substrate, wherein,
the grid is connected with a word line;
the drain electrode is connected with a bit line;
the source electrode is connected with a source line;
the substrate is connected to a substrate line.
2. The non-volatile memory cell of claim 1,
the transistor includes:
the silicon substrate comprises a first heavily doped region, a second heavily doped region, a polycrystalline silicon layer, a substrate, an asymmetric lightly doped region, a first side wall, a second side wall and a silicon oxide layer; wherein,
the silicon oxide layer is positioned on the substrate;
the polycrystalline silicon layer, the first side wall and the second side wall are all positioned on the silicon oxide layer;
the first side wall and the second side wall are respectively positioned on two sides of the silicon oxide layer;
the asymmetric lightly doped region is adjacent to the second heavily doped region and the silicon oxide layer.
3. The non-volatile memory cell of claim 1,
the first side wall is positioned above the first drain electrode and the second drain electrode and used for storing electric charges.
4. The non-volatile memory cell of claim 1,
the thickness of the silicon oxide layer is equal to that of the silicon oxide layer of the thick gate oxide transistor under the standard semiconductor logic process.
5. A data programming method of a nonvolatile memory cell is characterized in that,
the non-volatile memory cell includes a transistor,
the transistor includes: a drain, a source, a gate, and a substrate, wherein,
the grid is connected with a word line;
the drain electrode is connected with a bit line;
the source electrode is connected with a source line;
the substrate is connected with a substrate line;
the programming method comprises the following steps:
applying a word line programming voltage on a word line;
applying a bit line programming voltage on the bit line;
applying a source line programming voltage on a source line;
a substrate line programming voltage is applied on the substrate line.
6. The data programming method of claim 5,
presetting a data storage rule, and programming the nonvolatile memory unit according to the data storage rule to realize data storage.
7. The data programming method of claim 5,
the data storage rules include:
programming transistor 1 means storing data "1", and not programming transistor 1 means storing data "0"; or
Programming transistor 1 means storing data "0" and not programming transistor 1 means storing data "1".
8. The data programming method of claim 5,
the conduction current between the source and the drain of the programmed transistor is smaller than the initial conduction current;
the on-current between the source and drain of the unprogrammed transistor is equal to the initial on-current.
9. A data reading method of a nonvolatile memory cell is characterized in that,
the non-volatile memory cell includes a first transistor,
the first transistor includes: a first drain, a first source, a first gate, and a first substrate,
the first grid is connected with a word line;
the first drain electrode is connected with a bit line;
the first source electrode is connected with a source line;
the first substrate is connected with a substrate line;
the reading method comprises the following steps:
applying a word line read voltage on a word line;
applying a bit line read voltage on the bit line;
applying a source line read voltage on a source line;
applying a substrate line read voltage on the substrate line;
and determining data stored in the nonvolatile memory cell by detecting the conduction current between the source and the drain of the first transistor.
10. The data reading method according to claim 9,
setting a reading reference unit;
the read reference cell includes a second transistor,
the second transistor includes: a second drain, a second source, a second gate, and a second substrate, wherein,
the second grid is connected with a word line;
the second drain electrode is connected with a reference bit line;
the second source electrode is connected with a reference source line;
the second substrate is connected with the substrate line;
and applying a preset voltage to the reference bit line to enable the conduction current between the source and the drain of the second transistor to be smaller than the conduction current between the source and the drain of the first transistor which is not programmed but larger than the conduction current between the source and the drain of the first transistor which is programmed.
11. A data reading method according to claim 10,
and determining data stored in the nonvolatile memory cell by comparing the conduction current between the source and drain electrodes of the first and second transistors.
12. The data reading method according to claim 9,
a selection unit is provided, said selection unit comprising an input and at least two outputs, wherein,
applying a source line read voltage at the input;
each output end is correspondingly connected with one source line in the nonvolatile memory array;
the selection unit is used for selecting and conducting a source line of the nonvolatile memory unit which needs to read data in the nonvolatile memory array.
13. A method of erasing a non-volatile memory cell,
the non-volatile memory cell includes a transistor,
the transistor includes: a drain, a source, a gate, and a substrate, wherein,
the grid is connected with a word line;
the drain electrode is connected with a bit line;
the source electrode is connected with a source line;
the substrate is connected with a substrate line;
the erasing method comprises the following steps:
applying a word line erase voltage on a word line;
applying a bit line erase voltage on the bit line;
applying a source line erase voltage on a source line;
applying a substrate line erase voltage on the substrate line; wherein,
and the conduction current between the source electrode and the drain electrode of the erased transistor is equal to the initial conduction current.
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| CN109427793A (en) * | 2017-08-25 | 2019-03-05 | 亿而得微电子股份有限公司 | The electronics write-in formula of erasing of low-voltage difference can make carbon copies read-only memory and operating method |
| CN109427793B (en) * | 2017-08-25 | 2020-08-21 | 亿而得微电子股份有限公司 | Low voltage difference electronic writing-erasing type rewritable read-only memory and operation method |
| CN114765042A (en) * | 2021-09-28 | 2022-07-19 | 杭州存对半导体技术有限公司 | Single-tube nonvolatile memory cell array with paired structure and operation method thereof |
| CN114765042B (en) * | 2021-09-28 | 2023-08-01 | 杭州领开半导体技术有限公司 | Single-tube nonvolatile memory cell array of pairing structure and operation method thereof |
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