CN102621751A - Liquid crystal display panel and drive method thereof as well as liquid crystal display device - Google Patents
Liquid crystal display panel and drive method thereof as well as liquid crystal display device Download PDFInfo
- Publication number
- CN102621751A CN102621751A CN2011100334899A CN201110033489A CN102621751A CN 102621751 A CN102621751 A CN 102621751A CN 2011100334899 A CN2011100334899 A CN 2011100334899A CN 201110033489 A CN201110033489 A CN 201110033489A CN 102621751 A CN102621751 A CN 102621751A
- Authority
- CN
- China
- Prior art keywords
- source electrode
- pixel
- sub
- subpixels
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a liquid crystal display panel and a drive method thereof as well as a liquid crystal display device. The liquid crystal display panel comprises a plurality of grid electrode lines, a plurality of source electrode lines and a plurality of pixels, wherein each pixel comprises three sub-pixels; and a 2i-1<th> sub-pixel on each row is coupled with a 2i <th> sub-pixel onto an i<th> source electrode line, the 2i-1<th> sub-pixel and the 2i <th> sub-pixel are respectively coupled onto two different grid electrode lines, and i is a natural number. Through the liquid crystal display panel and the drive method thereof as well as the liquid crystal display device, drive passages of a source electrode drive can be reduced, the power consumption can also be effectively reduced, and the cost can be saved.
Description
Technical field
The present invention relates to appliance field, in particular to a kind of display panels and driving method thereof, LCD.
Background technology
A pixel of the LCD of existing correlation technique is made up of red R, green G, blue B three subpixels, is example with full HD LCD, and the pixel number is 1920 (columns) *, 1080 (line numbers).So the sub-pixel of column direction just the number of thin film transistor (TFT) be 1920*3=5760.
Fig. 1 is the structural representation according to the display panels of correlation technique.As shown in Figure 1; When gate drivers (being scanning drive chip) control Gi gate line is opened the capable pixel of i; Source electrode driver (being the data source chip for driving) converts digital signal into simulating signal and is added on the data line Dj; This data line Dj connects the source electrode of all TFT of these row, but can only signal be added in the drain electrode of the R sub-pixel TFT that grid opened, thereby lights the zone of this TFT control.This shows the arrangement of subpixels mode of Fig. 1 has determined how many bar source electrode data lines are how many subpixels just need, and then just needs what data source drive channels.Equally, gate drivers (being scanning drive chip) also is consistent with line number.
Source electrode driver (being the data source chip for driving) is as the DC-AC conversion chip, and major function is exactly to convert the digital signal that time schedule controller provides into simulating signal according to set polarity mode.And the sequential that scanning drive signal provides according to time schedule controller will be gone the thin film transistor (TFT) of pixel successively and opened and closed.This shows that the center of gravity of whole drive system all concentrates on the source electrode driver (being the data source chip for driving).This just causes source electrode driver (being the data source chip for driving) complex design, and power consumption is bigger.Existing correlation technique reduces the power consumption of source electrode driver (being the data source chip for driving) through adopting the way that changes the polar switching frequency, but this method reduces the limited in one's ability of power consumption, and has no idea to reduce the port number of source electrode driver IC.
To above-mentioned prior art in the process that reduces the source electrode driver power consumption, can't reduce the passage of source electrode driver IC, cause reducing the weak effect and the high problem of cost of power consumption of driver, effective solution is not proposed at present as yet.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of display panels and driving method thereof, LCD; With solve prior art in the process that reduces the source electrode driver power consumption; Can't reduce the passage of source electrode driver IC, cause reducing the weak effect and the high problem of cost of power consumption of driver.
To achieve these goals, according to an aspect of the present invention, a kind of display panels is provided.
Display panels according to the present invention comprises: many gate lines; Many source electrode lines; A plurality of pixels, each pixel comprises three subpixels; Wherein, 2i-1 subpixels and 2i subpixels on each row are coupled on the i bar source electrode line, and the 2i-1 subpixels is coupled in respectively on two different gate lines with the 2i subpixels, and i is a natural number.
Further, sub-pixel comprises thin film transistor (TFT), and wherein, the 2i-1 subpixels has the first film transistor, and the transistorized grid of the first film is coupled on the first grid polar curve, and source electrode is coupled on the i bar source electrode line; The 2i subpixels has second thin film transistor (TFT), and the grid of second thin film transistor (TFT) is coupled on the second grid line, and source electrode is coupled on the i bar source electrode line.
Further, constantly open first grid polar curve, be the transistorized gate charges of the first film of 2i-1 subpixels, and first deflection voltage is transferred to the transistorized source electrode of the first film through i bar source electrode line first; Constantly open the second grid line second, be the gate charges of second thin film transistor (TFT) of 2i subpixels, and second deflection voltage is transferred to the source electrode of second thin film transistor (TFT) through i bar source electrode line.
Further, sub-pixel comprises thin film transistor (TFT), and wherein, the 2i subpixels has second thin film transistor (TFT), and the grid of second thin film transistor (TFT) is coupled on the first grid polar curve, and source electrode is coupled on the i bar source electrode line; The 2i-1 subpixels has the first film transistor, and the transistorized grid of the first film is coupled on the second grid line, and source electrode is coupled on the i bar source electrode line.
Further, constantly open first grid polar curve, be the gate charges of second thin film transistor (TFT) of 2i subpixels, and the 3rd deflection voltage is transferred to the source electrode of second thin film transistor (TFT) through i bar source electrode line first; Constantly open the second grid line second, be the transistorized gate charges of the first film of 2i-1 subpixels, and quadrupole deflector voltage is transferred to the transistorized source electrode of the first film through i bar source electrode line.
Further, the drain electrode of any thin film transistor (TFT) is connected with MM CAP and liquid crystal capacitance, and MM CAP is the liquid crystal capacitance charging.
To achieve these goals, according to another aspect of the present invention, a kind of driving method of display panels is provided.
Driving method according to display panels of the present invention comprises: open the first grid polar curve in many gate lines constantly first; To open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the first grid polar curve, sub-pixel is the 2i-1 subpixels that couples on the first grid polar curve; First deflection voltage is transferred to the 2i-1 subpixels through i bar source electrode line; Constantly open the second grid line in many gate lines second, to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the second grid line, sub-pixel is the 2i subpixels that couples on the second grid line; Second deflection voltage is transferred to the 2i subpixels through i bar source electrode line; Wherein, i is a natural number.
To achieve these goals, according to a further aspect of the invention, a kind of driving method of display panels is provided.
Driving method according to display panels of the present invention comprises: open the first grid polar curve in many gate lines constantly first; To open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the first grid polar curve, sub-pixel is the 2i subpixels that couples on the first grid polar curve; First deflection voltage is transferred to the 2i subpixels through i bar source electrode line; Constantly open the second grid line in many gate lines second, to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the second grid line, sub-pixel is the 2i-1 subpixels that couples on the second grid line; Second deflection voltage is transferred to the 2i-1 subpixels through i bar source electrode line; Wherein, i is a natural number.
To achieve these goals, in accordance with a further aspect of the present invention, a kind of LCD is provided, this LCD comprises above-mentioned any one display panels.
Further, LCD also comprises: time schedule controller is used to generate data-signal, clock signal and polarity switch signal; Gate drivers is used for opening or closing the thin film transistor (TFT) that couples on the gate line according to the order of sequence successively according to clock signal; Source electrode driver, being used for according to polarity switch signal is that the thin film transistor (TFT) that couples on the source electrode line provides deflection voltage.
Through the present invention, adopt many gate lines; Many source electrode lines; A plurality of pixels, each pixel comprises three subpixels; Wherein, 2i-1 subpixels and 2i subpixels on each row are coupled on the i bar source electrode line, and the 2i-1 subpixels is coupled in respectively on two different gate lines with the 2i subpixels, and i is a natural number; Solved prior art in the process that reduces the source electrode driver power consumption; Can't reduce the passage of source electrode driver IC, cause reducing the weak effect and the high problem of cost of power consumption of driver, reach the drive channels that reduces source electrode driver; More effectively reduce power consumption, cost-effective effect.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the structural representation according to the display panels of correlation technique;
Fig. 2 is the structural representation according to the display panels of the embodiment of the invention one;
Fig. 3 is the structural representation according to the display panels of the embodiment of the invention two;
Fig. 4 is the process flow diagram according to the driving method of the display panels of the embodiment of the invention three; And
Fig. 5 is the process flow diagram according to the driving method of the display panels of the embodiment of the invention four.
Embodiment
Need to prove that under the situation of not conflicting, embodiment and the characteristic among the embodiment among the application can make up each other.Combine embodiment to specify the present invention below with reference to accompanying drawing and 3.
The invention provides a kind of display panels.Fig. 2 is the structural representation according to the display panels of the embodiment of the invention one; Fig. 3 is the structural representation according to the display panels of the embodiment of the invention two.Shown in Fig. 2 and 3, this display panels comprises: many gate lines; Many source electrode lines; A plurality of pixels, each pixel comprises three subpixels; Wherein, 2i-1 subpixels and 2i subpixels on each row are coupled on the i bar source electrode line, and the 2i-1 subpixels is coupled in respectively on two different gate lines with the 2i subpixels, and i is a natural number.Wherein, i bar source electrode line can be source electrode lines such as Dj, Dj+1 or Dj+2.
The embodiment of the invention is divided into each sub-pixel of going by two gate lines controls, simultaneously; Two adjacent subpixels are coupled on same the source electrode line, and these two adjacent sub-pixels are respectively sub-pixel and the sub-pixel on the even bit on the odd bits, in the process of display panels work; When sweep signal is opened article one gate line of this delegation's sub-pixel; Source electrode line is transferred to signal one in two subpixels that couple on this source electrode line, when sweep signal when next opens the second gate line of this delegation's sub-pixel constantly, likewise; Source electrode line is transferred to signal the another one sub-pixel in two subpixels that couple on this source electrode line; So just realized that two periods of sub data transmission of each row sub-pixel carry out respectively, the source electrode line of adjacent daughter element can be shared by two subpixels, so just when the assurance data are effectively transmitted; Again source electrode line has been saved half the; Thereby make the port number of source electrode driver reduce half, reduced the cost of driver, realize more effective reduction power consumption.
In the concrete application process, the thin film transistor (TFT) of new LCD provided by the invention (hereinafter to be referred as TFT) method for designing.The capable sub-pixel of LCD is divided into two gate control lines, controls odd number sub-pixel TFT and even sub-pixel TFT respectively.Odd number sub-pixel TFT and even sub-pixel TFT are by data line transmission data simultaneously.Do not change the RGB TFT arrangement mode that current display group becomes pixel like this; Only change the connected mode of each transistor gate and source electrode; Gate drivers (being scanning drive chip) port number is doubled; The passage of source electrode driver (being the data source chip for driving) reduces by half, and reduces whole driving cost.
As shown in Figure 2, the sub-pixel of the above embodiment of the present invention can comprise thin film transistor (TFT), and wherein, the 2i-1 subpixels has the first film transistor, and the transistorized grid of the first film is coupled on the first grid polar curve, and source electrode is coupled on the i bar source electrode line; The 2i subpixels has second thin film transistor (TFT), and the grid of second thin film transistor (TFT) is coupled on the second grid line, and source electrode is coupled on the i bar source electrode line.Wherein, First grid polar curve can be Gi, Gi+2 or Gi+4 bar gate line; The second grid line can be Gi+1, Gi+3 or Gi+5 bar gate line; I bar source electrode line can be Dj, a Dj+1 or Dj+2 source electrode line, and the 2i-1 subpixels is the sub-pixel on the odd column, and the 2i subpixels is the sub-pixel on the even column.This embodiment has further described the connected mode of each sub-pixel on display panel; Make two subpixels on each row share a gate line; Because the sub-pixel that is connected on the same gate line is coupled in respectively on the different gate lines, and these two gate lines are adjacent, therefore; Connect subpixels and open in the different moment respectively, do not influence source electrode line transmission data.
Preferably, the above embodiment of the present invention can be the transistorized gate charges of the first film of 2i-1 subpixels, and first deflection voltage is transferred to the transistorized source electrode of the first film through i bar source electrode line when first open first grid polar curve constantly; When second constantly opens the second grid line, be the gate charges of second thin film transistor (TFT) of 2i subpixels, and second deflection voltage is transferred to the source electrode of second thin film transistor (TFT) through i bar source electrode line.
Embodiment as shown in Figure 2; Can be the example explanation with the pixel of frame choosing more specifically; This embodiment shown in Figure 2 is divided into two gate control lines with sub-pixel of each row, representes with GI and GI+1 respectively, and the grid of R sub-pixel is connected on the gate control lines Gi+1; The grid of G sub-pixel is connected on the gate control lines GI, and the two source electrode of R sub-pixel and G sub-pixel is connected on the common source line Dj.Like this.Time schedule controller is seen the line scanning start signal off to gate drivers (for example scanning control chip); This gate drivers requires to export high level cut-in voltage Vgh successively to Gi according to the sequential of time schedule controller; Gi+1; ..., the Gi+N gate line makes the gate charges of the TFT that the gate control lines of connecting for each gate drivers at different time section output Vgh couples.After the TFT gate charges that couples on the capable gate line of Gi, can be with the TFT source electrode and drain electrode conducting of G sub-pixel.At this moment; Source electrode driver (for example data source control chip) receives the digital signal of the G sub-pixel of time schedule controller, and is converted into simulating signal through the DC-AC converter, and the data line DJ that connects for source electrode driver (for example data source control chip) then provides a deflection voltage V0; And because the source electrode of G pixel TFT and the conducting that drains at this moment; Therefore this deflection voltage is given MM CAP Cs charging, treat that the Cs charging finishes after, the scanning control chip output low level is closed voltage Vgl to the Gi gate line; The TFT grid voltage of this G sub-pixel is become low level Vgl, and source electrode breaks off with drain electrode.Scanning control chip requires Vgh voltage is added on the Gi+1 gate line to R sub-pixel TFT gate charges according to the sequential of time schedule controller then.After treating this TFT source electrode and gate turn-on, the data source control chip is to be added on the shared data transmission line DJ after the simulating signal with R sub-pixel numeral conversion of signals, so just can the deflection voltage V1 of R sub-pixel be added on the MM CAP for this sub-pixel.Though and this moment the G sub-pixel the TFT source voltage be equal to the deflection voltage V1 of R sub-pixel; But because the grid voltage of G sub-pixel is that low level is closed voltage Vgl; So the grid voltage of the G sub-pixel of this moment is V0 still, MM CAP is charged to V0 to Clc, forms voltage difference with common voltage Vcom like this; The liquid crystal molecule that drives the Clc control area rotates to the angle of formulation, thereby makes this zone show the color of appointment.
The B sub-pixel point of first pixel that connects on delegation's gate line in like manner is same as the previously described embodiments with the connected mode and the principle of work of the R sub-pixel point of second pixel, therefore, and the same reason of other pixel connected modes of whole liquid crystal display panel.
This shows that the transmission of the sub-pixel data of each row divides two time periods to carry out respectively among Fig. 2, and the data line of adjacent subpixels can be shared.So promptly guaranteed the orderly transmission of data, the traditional monitor that can data line be reduced again half the, thus reduce the port number of data-switching chip half the.Reduce chip cost and power consumption greatly.
As shown in Figure 3, the sub-pixel of the above embodiment of the present invention comprises thin film transistor (TFT), and wherein, the 2i subpixels has second thin film transistor (TFT), and the grid of second thin film transistor (TFT) is coupled on the first grid polar curve, and source electrode is coupled on the i bar source electrode line; The 2i-1 subpixels has the first film transistor, and the transistorized grid of the first film is coupled on the second grid line, and source electrode is coupled on the i bar source electrode line.Wherein, First grid polar curve can be Gi, Gi+2 or Gi+4 bar gate line; The second grid line can be Gi+1, Gi+3 or Gi+5 bar gate line; I bar source electrode line can be Dj, a Dj+1 or Dj+2 source electrode line, and the 2i-1 subpixels is the sub-pixel on the odd column, and the 2i subpixels is the sub-pixel on the even column.This embodiment is identical with the effect of embodiment shown in Figure 2, two kinds of real-time modes relatively, and difference is that two subpixels that are connected on the identical gate line are opened through two source electrode lines respectively; The mode that two subpixels connect two source electrode lines has two kinds, and two kinds of situation are opposite, promptly in embodiment as shown in Figure 2; First sub-pixel connects article one gate line; Second subpixels is coupled on the second gate line, and in embodiment as shown in Figure 3, first sub-pixel is coupled on the second gate line; First sub-pixel is coupled on article one gate line, but the effect that two kinds of situation reach is identical.
Preferably, also can when first constantly open first grid polar curve, be the gate charges of second thin film transistor (TFT) of 2i subpixels, and the 3rd deflection voltage is transferred to the source electrode of second thin film transistor (TFT) through i bar source electrode line in the above embodiment of the present invention; When second constantly opens the second grid line, be the transistorized gate charges of the first film of 2i-1 subpixels, and quadrupole deflector voltage is transferred to the transistorized source electrode of the first film through i bar source electrode line.
Embodiment as shown in Figure 3; Can be the example explanation with the pixel of frame choosing more specifically; This embodiment shown in Figure 3 is divided into two gate control lines with sub-pixel of each row, representes with GI and GI+1 respectively, and the grid of G sub-pixel is connected on the gate control lines Gi+1; The grid of R sub-pixel is connected on the gate control lines GI, and the two source electrode of R sub-pixel and G sub-pixel is connected on the common source line Dj.Like this.Time schedule controller is seen the line scanning start signal off to gate drivers (for example scanning control chip); This gate drivers requires to export high level cut-in voltage Vgh successively to Gi according to the sequential of time schedule controller; Gi+1; ..., the Gi+N gate line makes the gate charges of the TFT that the gate control lines of connecting for each gate drivers at different time section output Vgh couples.After the TFT gate charges that couples on the capable gate line of Gi, can be with the TFT source electrode and drain electrode conducting of R sub-pixel.At this moment; Source electrode driver (for example data source control chip) receives the digital signal of the R sub-pixel of time schedule controller, and is converted into simulating signal through the DC-AC converter, and the data line DJ that connects for source electrode driver (for example data source control chip) then provides a deflection voltage V0; And because the source electrode of R pixel TFT and the conducting that drains at this moment; Therefore this deflection voltage is given MM CAP Cs charging, treat that the Cs charging finishes after, the scanning control chip output low level is closed voltage Vgl to the Gi gate line; The TFT grid voltage of this R sub-pixel is become low level Vgl, and source electrode breaks off with drain electrode.Scanning control chip requires Vgh voltage is added on the Gi+1 gate line to G sub-pixel TFT gate charges according to the sequential of time schedule controller then.After treating this TFT source electrode and gate turn-on, the data source control chip is to be added on the shared data transmission line DJ after the simulating signal with G sub-pixel numeral conversion of signals, so just can the deflection voltage V1 of G sub-pixel be added on the MM CAP for this sub-pixel.Though and this moment the R sub-pixel the TFT source voltage be equal to the deflection voltage V1 of G sub-pixel; But because the grid voltage of R sub-pixel is that low level is closed voltage Vgl; So the grid voltage of the R sub-pixel of this moment is V0 still, MM CAP is charged to V0 to Clc, forms voltage difference with common voltage Vcom like this; The liquid crystal molecule that drives the Clc control area rotates to the angle of formulation, thereby makes this zone show the color of appointment.
The B sub-pixel point of first pixel that connects on delegation's gate line in like manner is same as the previously described embodiments with the connected mode and the principle of work of the R sub-pixel point of second pixel, therefore, and the same reason of other pixel connected modes of whole liquid crystal display panel.
This shows that the transmission of the sub-pixel data of each row divides two time periods to carry out respectively among Fig. 3, and the data line of adjacent subpixels can be shared.So promptly guaranteed the orderly transmission of data, the traditional monitor that can data line be reduced again half the, thus reduce the port number of data-switching chip half the.Reduce chip cost and power consumption greatly.
Because what the embodiment of the invention adopted is the display panels of single-point reverse drive mode; Therefore the pixel polarity each other on the display panels any direction is opposite; And the drain electrode of the thin film transistor (TFT) in the pixel is connected with MM CAP and liquid crystal capacitance arbitrarily, and MM CAP is the liquid crystal capacitance charging.
To sum up the display panels among the embodiment is a Thin Film Transistor-LCD, and its driving comprises source electrode driver (being the data source chip for driving) and gate drivers (being scanning drive chip), respectively the source electrode and the grid of control TFT.The LCD panel that promptly the present invention relates to can also comprise: time schedule controller is used to generate data-signal, clock signal and polarity switch signal; Gate drivers is used for opening or closing the thin film transistor (TFT) that couples on the gate line according to the order of sequence successively according to clock signal; Source electrode driver, being used for according to polarity switch signal is that the thin film transistor (TFT) that couples on the source electrode line provides deflection voltage.Because each pixel of LCD is made up of RGB three subpixels; The port number of source electrode driver (being the data source chip for driving) generally equals 3 times of display row number of pixels; And the port number of gate drivers (being scanning drive chip) equals the capable number of pixels of display; Source electrode driver (being the data source chip for driving) is the DC-AC chip, will adopt pixel method of attachment of the present invention far above gate drivers (being scanning drive chip) on the cost; Can be so that the decreased number of the gate line of source electrode driver, the cost of manufacture of hardware chip reduces.
The above embodiment of the present invention is under the situation of the arrangement mode that does not change traditional pixel; Realize reducing the gate line of gate drivers; Make related transistor connected mode can not cause the liquid crystal display production cost to increase; Do not increase technology difficulty yet, reduced cost of labor, prolonged the life-span of driver.
Fig. 4 is the process flow diagram according to the driving method of the display panels of the embodiment of the invention three.As shown in Figure 4, this method comprises the steps:
Step S102; Constantly open the first grid polar curve in many gate lines first through the gate drivers among Fig. 2; To open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the first grid polar curve, sub-pixel is the 2i-1 subpixels that couples on the first grid polar curve.This step is implemented in first and has opened the sub-pixel (for example, the R sub-pixel of first pixel) that couples on Gi is capable constantly, and this sub-pixel is the sub-pixel on the odd bits in this row.
Step S104 is transferred to the 2i-1 subpixels with first deflection voltage through i bar source electrode line.This step was implemented in the time of first frame scan, and the sub-pixel of the source electrode driver among Fig. 2 on odd bits applies first deflection voltage, and this first deflection voltage can be positive voltage or negative voltage.
Step S106 constantly opens the second grid line in many gate lines second, and to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the second grid line, sub-pixel is the 2i subpixels that couples on the second grid line.This step is implemented in second and has opened the sub-pixel (for example, the G sub-pixel of first pixel) that couples on Gi+1 is capable constantly, and this sub-pixel is the sub-pixel on the even bit in this row.
Step S108 is transferred to the 2i subpixels with second deflection voltage through i bar source electrode line; Wherein, i is a natural number.This step was implemented in the time of second frame scan, and the sub-pixel on even bit among Fig. 2 applies second deflection voltage, and second deflection voltage can be positive voltage or negative voltage, and opposite with first deflection voltage.
The above embodiment of the present invention realizes gate line multiplexing of gate drivers; The sub-pixel data transmission of each row divides two periods to carry out respectively; Thereby when guaranteeing that data are transmitted in order; Reduced gate line, the port number that is about to gate drivers has reduced half, has reduced chip cost and power consumption.
Fig. 5 is the process flow diagram according to the driving method of the display panels of the embodiment of the invention four.As shown in Figure 4, this method comprises the steps:
Step S202; Constantly open the first grid polar curve in many gate lines first through the gate drivers among Fig. 3; To open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the first grid polar curve, sub-pixel is the 2i subpixels that couples on the first grid polar curve.This step is implemented in first and has opened the sub-pixel (for example, the G sub-pixel of first pixel) that couples on Gi is capable constantly, and this sub-pixel is the sub-pixel on the even bit in this row.
Step S204 is transferred to the 2i subpixels with first deflection voltage through i bar source electrode line.This step was implemented in the time of first frame scan, and the sub-pixel of the source electrode driver among Fig. 3 on even bit applies first deflection voltage, and this first deflection voltage can be positive voltage or negative voltage.
Step S206 constantly opens the second grid line in many gate lines second, and to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the second grid line, sub-pixel is the 2i-1 subpixels that couples on the second grid line.This step is implemented in second and has opened the sub-pixel (for example, the R sub-pixel of first pixel) that couples on Gi+1 is capable constantly, and this sub-pixel is the sub-pixel on the odd bits in this row.
Step S208 is transferred to the 2i-1 subpixels with second deflection voltage through i bar source electrode line; Wherein, i is a natural number.This step was implemented in the time of second frame scan, and the sub-pixel on odd bits among Fig. 3 applies second deflection voltage, and second deflection voltage can be positive voltage or negative voltage, and opposite with first deflection voltage.
The above embodiment of the present invention realizes gate line multiplexing of gate drivers; The sub-pixel data transmission of each row divides two periods to carry out respectively; Thereby when guaranteeing that data are transmitted in order; Reduced gate line, the port number that is about to gate drivers has reduced half, has reduced chip cost and power consumption.
Need to prove; Can in processor system, carry out in the step shown in the process flow diagram of accompanying drawing such as one group of executable instruction, and, though logical order has been shown in process flow diagram; But in some cases, can carry out step shown or that describe with the order that is different from here.
From above embodiment described, can find out that the present invention has realized following technique effect: the present invention realized reducing the drive channels of source electrode driver, more effectively reduces power consumption, saved cost.Do not change the arrangement mode of traditional pixel simultaneously, wherein related transistor connected mode can not cause the liquid crystal display production cost to increase, and does not increase technology difficulty yet.
The embodiment of the invention also provides a kind of LCD, and this LCD comprises above-mentioned any one display panels.Promptly on any one LCD, can use the display panels that arrives involved in the present invention; Using the LCD of this display panels to make has remarkable meaning increasing product aspect serviceable life, especially in the electric equipment products performance history, use this method to have to reduce power consumption, energy-conservation effect.The LCD usable range that the present invention relates to is extensive, and is compatible good.
Preferably, this LCD also comprises: time schedule controller is used to generate data-signal, clock signal and polarity switch signal; Gate drivers is used for opening or closing the thin film transistor (TFT) that couples on the gate line according to the order of sequence successively according to clock signal; Source electrode driver, being used for according to polarity switch signal is that the thin film transistor (TFT) that couples on the source electrode line provides deflection voltage.
Obviously, it is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element; Thereby; Can they be stored in the memory storage and carry out, perhaps they are made into a plurality of integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize by calculation element.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a display panels is characterized in that, comprising:
Many gate lines;
Many source electrode lines;
A plurality of pixels, each said pixel comprises three subpixels;
Wherein, 2i-1 the said sub-pixel on each row and 2i said sub-pixel are coupled on the i bar source electrode line, and 2i-1 said sub-pixel be coupled in respectively on two different gate lines with 2i said sub-pixel, and i is a natural number.
2. display panels according to claim 1 is characterized in that said sub-pixel comprises thin film transistor (TFT), wherein,
Said 2i-1 subpixels has the first film transistor, and the transistorized grid of said the first film is coupled on the first grid polar curve, and source electrode is coupled on the i bar source electrode line;
Said 2i subpixels has second thin film transistor (TFT), and the grid of said second thin film transistor (TFT) is coupled on the second grid line, and source electrode is coupled on the i bar source electrode line.
3. display panels according to claim 2 is characterized in that,
Constantly open first grid polar curve first, be the transistorized gate charges of said the first film of said 2i-1 subpixels, and first deflection voltage is transferred to the transistorized source electrode of said the first film through i bar source electrode line;
Constantly open the second grid line second, be the gate charges of said second thin film transistor (TFT) of said 2i subpixels, and second deflection voltage is transferred to the source electrode of said second thin film transistor (TFT) through i bar source electrode line.
4. display panels according to claim 1 is characterized in that said sub-pixel comprises thin film transistor (TFT), wherein,
Said 2i subpixels has second thin film transistor (TFT), and the grid of said second thin film transistor (TFT) is coupled on the first grid polar curve, and source electrode is coupled on the i bar source electrode line;
Said 2i-1 subpixels has the first film transistor, and the transistorized grid of said the first film is coupled on the second grid line, and source electrode is coupled on the i bar source electrode line.
5. display panels according to claim 4 is characterized in that,
Constantly open first grid polar curve first, be the gate charges of said second thin film transistor (TFT) of said 2i subpixels, and the 3rd deflection voltage is transferred to the source electrode of said second thin film transistor (TFT) through i bar source electrode line;
Constantly open the second grid line second, be the transistorized gate charges of said the first film of said 2i-1 subpixels, and quadrupole deflector voltage is transferred to the transistorized source electrode of said the first film through i bar source electrode line.
6. according to each described display panels among the claim 2-5, it is characterized in that the drain electrode of any said thin film transistor (TFT) is connected with MM CAP and liquid crystal capacitance, said MM CAP is said liquid crystal capacitance charging.
7. the driving method of a display panels is characterized in that, comprising:
Constantly open the first grid polar curve in many gate lines first, to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the said first grid polar curve, said sub-pixel is the 2i-1 subpixels that couples on the said first grid polar curve;
First deflection voltage is transferred to said 2i-1 subpixels through i bar source electrode line;
Constantly open the second grid line in many gate lines second, to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the said second grid line, said sub-pixel is the 2i subpixels that couples on the said second grid line;
Second deflection voltage is transferred to said 2i subpixels through i bar source electrode line; Wherein, i is a natural number.
8. the driving method of a display panels is characterized in that, comprising:
Constantly open the first grid polar curve in many gate lines first, to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the said first grid polar curve, said sub-pixel is the 2i subpixels that couples on the said first grid polar curve;
First deflection voltage is transferred to said 2i subpixels through i bar source electrode line;
Constantly open the second grid line in many gate lines second, to open the gate charges to the thin film transistor (TFT) of the sub-pixel that couples on the said second grid line, said sub-pixel is the 2i-1 subpixels that couples on the said second grid line;
Second deflection voltage is transferred to said 2i-1 subpixels through i bar source electrode line; Wherein, i is a natural number.
9. a LCD is characterized in that, comprises any described display panels among the claim 1-6.
10. LCD according to claim 9 is characterized in that, said LCD also comprises:
Time schedule controller is used to generate data-signal, clock signal and polarity switch signal;
Gate drivers is used for opening or closing the thin film transistor (TFT) that couples on the gate line according to the order of sequence successively according to said clock signal;
Source electrode driver, being used for according to said polarity switch signal is that the said thin film transistor (TFT) that couples on the source electrode line provides deflection voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100334899A CN102621751A (en) | 2011-01-30 | 2011-01-30 | Liquid crystal display panel and drive method thereof as well as liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100334899A CN102621751A (en) | 2011-01-30 | 2011-01-30 | Liquid crystal display panel and drive method thereof as well as liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102621751A true CN102621751A (en) | 2012-08-01 |
Family
ID=46561753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100334899A Pending CN102621751A (en) | 2011-01-30 | 2011-01-30 | Liquid crystal display panel and drive method thereof as well as liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102621751A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014089859A1 (en) * | 2012-12-10 | 2014-06-19 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driver display method therefor |
| CN104900207A (en) * | 2015-06-24 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, drive method thereof and display device |
| CN107507588A (en) * | 2017-08-28 | 2017-12-22 | 惠科股份有限公司 | The drive circuit and driving method of display panel |
| CN110574097A (en) * | 2016-11-28 | 2019-12-13 | 上海云英谷科技有限公司 | Distributed driving of Liquid Crystal Display (LCD) panels |
| CN110992912A (en) * | 2019-12-27 | 2020-04-10 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111047997A (en) * | 2020-01-03 | 2020-04-21 | 福建华佳彩有限公司 | Display screen structure and driving method thereof |
| WO2020093512A1 (en) * | 2018-11-06 | 2020-05-14 | 惠科股份有限公司 | Pixel driving circuit, array substrate and display device |
| CN111477145A (en) * | 2020-04-09 | 2020-07-31 | 福建华佳彩有限公司 | Display screen structure with optimized power consumption and driving method thereof |
| CN112017607A (en) * | 2020-08-31 | 2020-12-01 | 福建华佳彩有限公司 | Display screen structure and driving method |
| CN113096613A (en) * | 2021-04-09 | 2021-07-09 | 南京芯视元电子有限公司 | Analog pixel circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1674081A (en) * | 2004-03-23 | 2005-09-28 | 株式会社日立显示器 | Liquid crystal display device |
| US20080068516A1 (en) * | 2006-09-15 | 2008-03-20 | Hitachi Displays, Ltd. | Liquid crystal display device |
| US20090102997A1 (en) * | 2007-10-22 | 2009-04-23 | Yi-Chien Wen | Liquid crystal display with data compensation function and method for compensating data of the same |
| CN101667397A (en) * | 2008-09-04 | 2010-03-10 | 乐金显示有限公司 | Liquid crystal display device and method for driving the same |
| CN202049715U (en) * | 2011-01-30 | 2011-11-23 | 青岛海信电器股份有限公司 | Liquid crystal display panel, liquid crystal display and multimedia terminal |
-
2011
- 2011-01-30 CN CN2011100334899A patent/CN102621751A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1674081A (en) * | 2004-03-23 | 2005-09-28 | 株式会社日立显示器 | Liquid crystal display device |
| US20080068516A1 (en) * | 2006-09-15 | 2008-03-20 | Hitachi Displays, Ltd. | Liquid crystal display device |
| US20090102997A1 (en) * | 2007-10-22 | 2009-04-23 | Yi-Chien Wen | Liquid crystal display with data compensation function and method for compensating data of the same |
| CN101667397A (en) * | 2008-09-04 | 2010-03-10 | 乐金显示有限公司 | Liquid crystal display device and method for driving the same |
| CN202049715U (en) * | 2011-01-30 | 2011-11-23 | 青岛海信电器股份有限公司 | Liquid crystal display panel, liquid crystal display and multimedia terminal |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014089859A1 (en) * | 2012-12-10 | 2014-06-19 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driver display method therefor |
| CN104900207A (en) * | 2015-06-24 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, drive method thereof and display device |
| CN104900207B (en) * | 2015-06-24 | 2017-06-06 | 京东方科技集团股份有限公司 | Array base palte and its driving method and display device |
| CN110574097A (en) * | 2016-11-28 | 2019-12-13 | 上海云英谷科技有限公司 | Distributed driving of Liquid Crystal Display (LCD) panels |
| CN110574097B (en) * | 2016-11-28 | 2022-04-26 | 昆山云英谷电子科技有限公司 | Distributed driving of Liquid Crystal Display (LCD) panels |
| CN107507588A (en) * | 2017-08-28 | 2017-12-22 | 惠科股份有限公司 | The drive circuit and driving method of display panel |
| WO2019041336A1 (en) * | 2017-08-28 | 2019-03-07 | 惠科股份有限公司 | Driving circuit and driving method for display panel |
| WO2020093512A1 (en) * | 2018-11-06 | 2020-05-14 | 惠科股份有限公司 | Pixel driving circuit, array substrate and display device |
| CN110992912A (en) * | 2019-12-27 | 2020-04-10 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111047997A (en) * | 2020-01-03 | 2020-04-21 | 福建华佳彩有限公司 | Display screen structure and driving method thereof |
| CN111477145A (en) * | 2020-04-09 | 2020-07-31 | 福建华佳彩有限公司 | Display screen structure with optimized power consumption and driving method thereof |
| CN112017607A (en) * | 2020-08-31 | 2020-12-01 | 福建华佳彩有限公司 | Display screen structure and driving method |
| CN113096613A (en) * | 2021-04-09 | 2021-07-09 | 南京芯视元电子有限公司 | Analog pixel circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102621751A (en) | Liquid crystal display panel and drive method thereof as well as liquid crystal display device | |
| US10242634B2 (en) | Display device | |
| US10297214B2 (en) | High resolution demultiplexer driver circuit | |
| CN103280201B (en) | Gate drive apparatus and display device | |
| CN206194295U (en) | Data line demultiplexer , display substrates , display panel and display device | |
| US20170345384A1 (en) | Demultiplex type display driving circuit | |
| KR100674976B1 (en) | Apparatus and method for driving gate lines using shared circuit in flat panel display | |
| CN104317086A (en) | Method for driving liquid crystal display panel | |
| CN102930840B (en) | Liquid crystal display driving circuit as well as driving method and LCD (Liquid Crystal Display) thereof | |
| US20090289878A1 (en) | Liquid crystal display device and driving method thereof | |
| CN101083062A (en) | Liquid crystal display and driving method thereof | |
| CN101216650A (en) | Liquid crystal display device array substrate and driving method thereof | |
| CN105047166A (en) | Drive method for liquid crystal display panel and liquid crystal display apparatus | |
| US11094276B2 (en) | Gate driver, display apparatus including the same and method of driving display panel using the same | |
| CN102750919A (en) | Display panel as well as drive method and display device thereof | |
| US10311821B2 (en) | Data driver of liquid crystal display having two individually regulable gamma voltages | |
| KR102423424B1 (en) | Liquid display device | |
| CN105390114A (en) | Liquid crystal display device | |
| JP2005234533A (en) | Liquid crystal display and driving method thereof | |
| US20120050245A1 (en) | Charge sharing system and method of lcos display | |
| CN102881272A (en) | Driving circuit, liquid crystal display device and driving method | |
| US9524685B2 (en) | Display apparatus and method for driving the same | |
| CN104880875A (en) | Array substrate and liquid-crystal display panel | |
| CN101963728A (en) | Liquid crystal display | |
| CN103021366B (en) | The polarity reversal driving method of display panels, device and liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120801 |