CN102611450A

CN102611450A - Signal predication folding and interpolating ADC (Analog to Digital Converter) method based on power spectrum estimation

Info

Publication number: CN102611450A
Application number: CN201210068684XA
Authority: CN
Inventors: 邵志标; 张春茗
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2012-03-15
Filing date: 2012-03-15
Publication date: 2012-07-25
Anticipated expiration: 2032-03-15
Also published as: CN102611450B; WO2013134988A1

Abstract

The invention discloses a signal predication folding and interpolating ADC (Analog to Digital Converter) method based on power spectrum estimation, comprising an NF=Ncoarse+Nfine bit pipelined folding and interpolating ADC, a signal predication unit based on the power spectrum estimation, a digital to analog converter and a subtraction unit, wherein the bit pipelined folding and interpolating ADC comprises a front-end single sampling keeping circuit, a distribution type sampling keeping circuit, an analog folding pre-processing circuit, a fine quantization ADC and a coarse quantization ADC; an input signal x(t) of the ADC of an analog front end of an SDR (Software Defined Radio) receiving system is composed of modulation signals which are processed by an ADC analog front end and are received form different standards, wavebands and modes; and the x(t) covers different frequency spectrums and has different signal powers. According to the signal predication folding and interpolating ADC method, the precision and speed boundary problems of the ADC are solved, an input dynamic range of the ADC is improved, and the requirements for the high-performance ADC by an SDR receiver are met.

Description

Signal prediction folding interpolation ADC method based on power spectrum estimation

the technical field is as follows:

the invention relates to a high-speed high-precision ADC (analog-to-digital converter) for a Software Defined Radio (SDR) receiving system, in particular to a signal prediction folding interpolation ADC method based on power spectrum estimation.

Background art:

the development limit of SDR is that the hardware performance can not meet the requirement, and the broadband large dynamic range ADC becomes the bottleneck of SDR development. The conversion rate of the existing ADC with the resolution ratio of more than 20 bits is lower than 1MHz, the conversion rate is 40MHz, the resolution ratio is less than 16 bits, and the requirements of an SDR receiver for processing multiband, multimode and multi-standard signals with wide band and large dynamic range are difficult to meet.

For this purpose, the document [1] J.Mitota.technical variations in the globalization of software radio [ J ]. IEEE Communications Magazine, 1999, 37 (2): 84-89 employ a plurality of parallel ADCs to convert signals by dividing the overall frequency band received by the antenna into a plurality of sub-bands, one ADC for each sub-band. When the rate, the wave band, the mode and the standard of the signal are increased, a large number of ADCs are needed, so that the method is difficult, and a sampling 'blind area' and the like can occur when the signal crosses a sub-band or is divided by a receiving frequency band, so that the signal recovery after the ADC is digitalized is influenced, and the design difficulty of the ADC and even the whole system is increased; document [2] ARobert, P sesgaiah, C Taylor, et al, advanced Based Station Technology [ J ]. IEEE Communications Magazine, 1998, 36 (2): 96-102 adopts analog nonlinear signal compression technology, because the nonlinear distortion introduced by compression is difficult to offset during digital domain decompression, the influence on the SNDR of the system is large, and the realization of large dynamic range and high SNDR becomes difficult; document [3] H Nie, PT substrate.adaptive prediction and cancellation differentiation method for wireless and multistandard software radio base-station receivers [ J ]. IEEE Trans.Vehicular Technology, 2006, 55 (3): 887-. The above techniques for improving the input dynamic range of the ADC rely on increasing the number of circuit chips.

The invention content is as follows:

the invention aims to solve the problems of the precision and the speed boundary of the ADC, and provides a signal prediction folding interpolation ADC method based on power spectrum estimation for a fully integrated signal by combining a signal prediction algorithm based on power spectrum estimation and an improved folding interpolation ADC structure, so that the input dynamic range of the ADC is improved, and the requirements of an SDR receiver on a high-performance ADC are met.

In order to achieve the purpose, the invention adopts the following technical scheme:

the structure of the signal prediction folding interpolation ADC method based on power spectrum estimation is shown in figure 1, and the method comprisesDraw N_F＝N_coarse+N_fineBit-line folding interpolation ADC (within the dashed box), Signal Prediction Unit (SPU) based on power spectrum estimation, digital-to-analog converter (DAC) and subtraction unit. The pipeline folding interpolation ADC comprises a front-end single sample-hold circuit, a distributed sample-hold circuit, an analog folding preprocessing circuit, a fine quantization ADC and a coarse quantization ADC. The input signal x (t) of the ADC of the SDR receiving system analog front end consists of modulated signals from different standards, bands, modes processed by the ADC analog front end, x (t) covers different frequency spectra and has different signal powers. x (t) the sampling value output after passing through the front end single sampling holding circuit is x (n), and x (n) is decomposed into a narrow-band signal x with strong signal power by a subtraction unit_s(n) and a broadband signal x of weak signal power_w(n) is: x (n) ═ x_s(n)+x_w(n) of (a). And x_s(n) and x_w(n) satisfies the following condition:

1)x_s(n) represents all narrow-band strong power sampling signals, the total power P of which_sCoverage total bandwidth range of B_s；x_w(n) represents all broadband low power sampled signals, with total power P_wCoverage total bandwidth range of B_w。

2) If f_gRepresenting the sampling frequency, f, of the ADC_s≥2B_w＞＞B_s，x_w(n) may be derived from Nyquist sampling, and x_s(n) is oversampling at a rate of f_sAnd B_sIs determined by the ratio of (a) to (b).

3) Due to P_s＞＞P_wStatistical properties of x (n) are represented by x_s(n) determining. And x_sOversampling of (n), x (n) or x_s(n) with their adjacent signals x (n-1) or x, respectively_s(n-1) correlation. When a broadband signal x is used_w(n) when excited as input for signal prediction, the signal can be predicted from the previous sample x of a strong signal_s(n-1)、x_s(n-2) estimating the current value x_s(n)。

The coarse quantization ADC is used for carrying out sampling on the nth sampling point output by a front end single sampling hold circuitQuantizes and outputs digital signal e_d(n) of (a). Said power spectrum estimation based Signal Prediction Unit (SPU) is at e_d(n) based on the estimation of the current sample value from the previous sample value, the SPU estimated output value is mainly x_s(n) digital quantity estimation

It is composed of x_sFront sampled value [ x_s(n-1)，x_s(n-2)，...，x_s(n-2P)]Obtained by a power spectrum estimation algorithm. The DAC converts the digital value into an estimated valueConversion into corresponding analog quantities

Therefore, the sampling values x (n) and the analog estimation value of the pipeline folding interpolation ADC (front end single sampling holding circuit) behind the front end single sampling holding circuit

The difference, namely:

e (n) = x (n) - {\hat{x}}_{s} (n) = x_{w} (n) + x_{s} (n) - {\hat{x}}_{s} (n) - - - (1)

at this time, the signal processed by the pipeline folding interpolation ADC is a broadband low-power signal x_w(n) and prediction errorThe dynamic range of the input signal is compressed.

The structure of the invention has a feedback loop consisting of a coarse quantization ADC, an SPU and a DAC, and is estimated according to the first 2P values

The coarse quantization ADC is much less delayed than the fine quantization ADC, so the SPU output estimate can be used

Coding to obtain binary N_p(N) encoding the coarse ADC output to obtain binary N_coarse(N) encoding the fine quantization ADC output to obtain a binary N_fineAnd (n) is regarded as parallel work, and each sampling period is ensured to output a valid binary code. The present invention digitizes the result x of the sampling point x (n)_d(n) is:

x_d(n)＝N_p(n)+N_coarse(n)+N_fine(n) (2)

the resolution N of the signal prediction folding interpolation ADC method based on power spectrum estimation is as follows:

N＝N_p+N_coarse+N_fine (3)

wherein N is_PAnd N_fineResolution of SPU and fine quantization ADC, respectively, and N_coarseIs the number of resolution bits required to resolve the folded interval of the folded interpolated ADC.

The signal prediction algorithm based on power spectrum estimation is characterized in that x_w(n) white Gaussian noise (AWGN), x, which can be regarded as mean zero_s(n) is observed in AWGN environment, and the signal is predicted by Pisarenko harmonic decomposition method

A special autoregressive-moving average (ARMA) process can be modeled with inputs AWGN, and with the order and parameters of Autoregressive (AR) and Moving Average (MA) all the same, satisfying:

wherein,

is white gaussian noise, and is a noise,

is the variance of the noise, a_iAre prediction coefficients. From (3), the ARMA process obeys the normal equation:

is x_s(n) autocorrelation function. The formula of the normal equation (4) is similar to the modified Yule-Waller equation of the ARMA (2P, 2P) process, and the two equations are consistent in form, so the formula (4) can be also constructed into an over-definite equation system, and the order 2P and the prediction coefficient a are solved by using the algorithm of Singular Value Decomposition (SVD) -total least square method (TLS) in the invention in consideration of the accuracy and numerical stability of power spectrum estimation_iObtaining x_sFrequency of each harmonic of (n)

The power P of each harmonic signal_iSatisfies the following formula:

from the above, the power P of each sinusoidal signal can be obtained_i(ii) a The variance of gaussian white noise is:

prediction gain G of signal_P＝10log₁₀((P_s+P_w)/P_e) Is an index for measuring the SNR improvement degree of signal prediction, which is equivalent to that the resolution is improved by about G_P/6.02. The gain G is predicted as described above when using the modern parameterized power spectrum estimation method_PComprises the following steps:

shows G_PWith P_s/P_wIs increased when P is increased_sWhen accurately estimated, the prediction gain G_PReaches the maximum value

Expressed as:

ADVANTAGEOUS EFFECTS OF INVENTION

To prove the effects of the inventionA signal prediction folding interpolation ADC method based on power spectrum estimation with the resolution of 14 bits and the conversion rate of 250MS/s is designed, and a mixed signal process library of 0.18 mu m 1P6M (1.8V power supply voltage) is adopted to design a structure diagram comprising N_F10-bit pipeline folding interpolation ADC, subtraction unit and 8-bit DAC. Wherein the coarse quantization ADC is 5 bits, the fine quantization ADC is 7 bits, the DAC adopts a current steering structure of 5+3 segments to realize the conversion time less than 0.7ns, and the SPU is realized by adopting the signal prediction algorithm based on the power spectrum estimation. And D/A hybrid simulation is carried out on the whole ADC adopting the structure by using a Cadence hybrid signal simulation tool Spectre Verilog.

When the signal received by SDR analog front end is decomposed into x_s(t) and x_w(t), bandwidth and power consumption have the following characteristics: b is_s＝1MHz、B_w＝125MHz、P_s/P _w30 dB. To verify system performance, the ADC input signal is taken:

x(t)＝A_s1 sin(2π×10Kt+θ_s1)+A_s2 sin(2π×100Kt+θ_s2)+

A_s3 sin(2π×1Mt+θ_s3)+n(t)+A_w1 sin(2π×10Mt+θ_w1)+ (9)

A_w2 sin(2π×50Mt+θ_w2)+A_w3 sin(2π×100Mt+θ_w3)

wherein n (t) is additive white Gaussian noise; a. the_si sin(2π×f_sit+θ_si) (i is 1, 2, 3) is a narrow-band signal,

A_{s 1}^{2} / A_{s}^{2} = 6 dB,

A_{s}^{2} / A_{s}^{3} = 6 dB;

A_wi sin(2π×f_wit+θ_wi) (i is 1, 2, 3) is a broadband signal,

A_{w 1}^{2} / A_{w}^{2} = 6 dB,

A_{w}^{2} / A_{w}^{3} = 6 dB;

A_{s 1}^{2} / A_{w 1}^{2} = 66 dB,

A_{w}^{3} / 2 P_{N} = 6.8 dB,

P_Nis the power of n (t)Spectral Density (PSD). Thus, x (t) x after sampling by a front-end single sample-and-hold circuit_s(n) and x_w(n) may be represented as:

for comparison, the input signal of the formula (9) is respectively input into three ADCs of the signal prediction folding interpolation ADC method based on power spectrum estimation, the kernel 10bit pipeline folding interpolation ADC of the signal prediction folding interpolation ADC and the 14bit 250MS/s ideal ADC based on a behavioral level model for digitalization, and x (t) is sampled by a front-end single sampling holding circuit_sThe PSD of (n) and the PSD of the output signal digitized by the three ADCs are shown in fig. 2 (a), (b), (c), and (d). Obviously, in fig. 2(b), the input sine wave signal is buried in noise, and the 10-bit pipeline folding interpolation ADC cannot resolve the low-power wide-band sine wave signal; the signal masked in fig. 2(b) can be resolved by the signal prediction folding interpolation ADC of the present invention (fig. 2(c)) and the 14-bit ideal ADC (fig. 2 (d)). And the PSD distributions of fig. 2(c) and (d) are substantially the same, indicating that the resolution of the signal predictive folding interpolation ADC of the present invention is up to 14 bits. Thus, the SNR of the system is improved by 24dB, corresponding to an improvement of 4 bits [3]]Compared with the prior art, the SNR is improved greatly, which is the result of accurate signal prediction provided by the power spectrum estimation method and the SVD-TLS algorithm thereof.

SNR improvement mainly depends on G_PFIG. 3 is G_PAnd parameter P_s/P_wAnd B_s/f_sThe relationship (2) of (c). In the figure, curve (a) is when B_s/f_sWhen equal to 0.01, G_PDependent parameter P_s/P_wThe relationship of change, as can be seen, with P_s/P_wIncrease of G_P> also increases, contributing to improved SNR. While curve (b) describes when P is_s/P_w＝30dB、f_sAt 250MHz, G_PDependent parameterB_s/f_sThe relationship of the change is obvious when B_s/f_sAt increasing time G_PDecrease and thereby decrease the SNR improvement. When B is present_s/f_sIncreasing, decreasing the cross-correlation of adjacent samples, directly results in an increase in the error of the power estimation, and thus decreases the prediction gain G_P. Reference [3]]In the different encoding modes of FIGS. 6-7, as shown in FIG. 3, the prediction gain G of the present invention_PThe improvement is about 1-4 dB, and the modern power spectrum estimation method and the prediction accuracy of the SVD-STL algorithm are further shown to be high.

Considering the three structures, the ADC simultaneously digitizes signals of IMT-2000 and IS-136 standards received by the SDR receiving system, wherein the signal bandwidth of IMT-2000 IS 5MHz, and the signal bandwidth of IS-136 IS 30 KHz. Table 1 summarizes the main performance parameters achieved when the signal prediction folding interpolation ADC method based on power spectrum estimation, the kernel 10bit pipeline folding interpolation ADC of the signal prediction folding interpolation ADC, and the 14bit 250MHz ideal ADC based on a behavior level model digitize signals of IMT-2000 and IS-136 standards. As seen from the table: the resolution of the signal prediction folding interpolation ADC method based on power spectrum estimation is improved by about 4 bits, which is equivalent to that the SNR is increased by more than 24 dB.

Table 1 the following three major performance parameters when the ADC digitizes signals of IMT-2000 and IS-136 standards (I) signal prediction folding interpolation ADC method based on power spectrum estimation (II) kernel 10bit pipeline folding interpolation ADC (iii) 14bit 250MHz ideal ADC based on behavior level model

Description of the drawings:

FIG. 1 is a diagram illustrating an ADC method structure for signal prediction folding interpolation based on power spectrum estimation according to the present invention;

FIG. 2 shows sample values x of x (t)_sPSD distribution of (n) and PSD distribution of output signals after three ADC digitalization, wherein (a) is x (t) x after front end single sampling and holding sampling_sPSD of (n), (b) PSD of kernel 10bit pipeline folding interpolation ADC output signal, (c) PSD of signal prediction folding interpolation ADC output signal of the present invention, (d) PSD of ideal 14bit ADC output signal;

FIG. 3 shows the prediction gain G_PAnd parameter P_s/P_wAnd B_s/f_sThe relationship of (1);

the specific implementation mode is as follows:

the invention is described in further detail below with reference to the accompanying drawings:

as shown in FIG. 1, the signal prediction folding interpolation ADC method structure based on power spectrum estimation of the invention comprises N_F＝N_coarse+N_fineBit-line folding interpolation ADC (within the dashed box), Signal Prediction Unit (SPU) based on power spectrum estimation, digital-to-analog converter (DAC) and subtraction unit. The pipeline folding interpolation ADC comprises a front-end single sample-hold circuit, a distributed sample-hold circuit, an analog folding preprocessing circuit, a fine quantization ADC and a coarse quantization ADC. The input signal x (t) of the ADC of the SDR receiving system analog front end consists of modulated signals from different standards, bands, modes processed by the ADC analog front end, x (t) covers different frequency spectra and has different signal powers. x (t) the sampling value output after passing through the front end single sampling hold circuit is x (n), and x (n) is decomposed into a narrow-band signal x with strong signal power_s(n) and a broadband signal x of weak signal power_w(n) is: x (n) ═ x_s(n)+x_w(n) of (a). And x_s(n) and x_w(n) satisfies the following condition:

1)x_s(n) represents all narrow-band strong power sampling signals, their total power P_sCoverage total bandwidth range of B_s(ii) a And x_w(n) represents all broadband low power sampled signals, their total power P_wCoverage total bandwidth range of B_w。

2) If f_sRepresents the sampling frequency of the ADC, then f_s≥2B_w＞＞B_sIf the signal x_w(n) may be Nyquist sampling derived, and x_s(n) is oversampling at a rate of f_sAnd B_sIs determined by the ratio of (a) to (b).

3) Due to P_s＞＞P_wStatistical properties of x (n) are represented by x_s(n) determining. Due to x_sOversampling of (n), x (n) or x_s(n) with adjacent signals x (n-1) or x, respectively_s(n-1) there is a strong cross-correlation. As a result: when the broadband signal x_w(n) when excited as input for signal prediction, the signal can be predicted from the previous sample x of a strong signal_s(n-1)、x_sEstimate the current value x_s(n)。

The coarse quantization ADC quantizes the nth sampling point output by the front-end single sampling hold circuit, and the output is a digital signal e_d(n) of (a). Said power spectrum estimation based Signal Prediction Unit (SPU) is at e_d(n) estimating the current sample value according to the previous sample value under the excitation of (n), and forming the sampling signal x of x (n)_s(n) and x_w(n) satisfying the above three conditions, the output of the SPU estimation is mainly x_s(n) estimation of digital quantities

It can be composed of x_s2P previous sample values x_s(n-1)，x_s(n-2)，...，x_s(n-2P)]And obtaining the target by using a power spectrum estimation method. The DAC will estimate the digital quantity

Conversion into corresponding analog quantities

Therefore, the pipeline folding interpolation ADC after the front-end single sample-hold circuit digitizes the sampling values x (n) and the analog estimation value of the front-end single sample-hold circuit

The difference of (a) is represented by the formula (1).

From above, the N_F＝N_coarse+N_fineThe signal processed by the bit-line folding interpolation ADC is a broadband low-power signal x_w(n) and prediction errorThus reducing the dynamic range of the input signal.

Although the structure of the present invention has a feedback loop consisting of coarse quantization ADC, SPU and DAC, the analog quantity is estimated

Is derived from the first 2P values and the coarse quantization ADC delay is much less than the fine quantization, so the SPU outputs an estimate

Obtaining binary N after coding_p(N) encoding the coarse ADC output to obtain binary N_coarse(N) and the fine quantization ADC output are encoded to obtain a binary N_fineAnd (n) can be regarded as parallel work, and each sampling period is ensured to output a valid binary code. The present invention digitizes the result x of the sampling point x (n)_d(n) may be:

x_d(n)＝N_p(n)+N_coarse(n)+N_fine(n) (12)

N＝N_p+N_coarse+N_fine (13)

N_Pand N_fineResolution, N, of SPU and fine quantization ADC, respectively_coarseIs the number of resolution bits required to resolve the folded interval of the folded interpolated ADC.

According to the signal prediction folding interpolation ADC method based on the power spectrum estimation, the algorithm based on the power spectrum estimation comprises modeling of signal prediction and signal prediction gain determination of signal prediction coefficient sum. The incorporation of the SPU and DAC into the folded-interpolation ADC in the present invention improves the resolution of the overall ADC, but these added units also increase the complexity of the system. Also, as is apparent from fig. 1, there is a series signal processing feedback loop comprising: obtaining a predicted signal value in an SPU by coarsely quantizing ADC digitized signal e (n-1)

Then converted into corresponding analog quantity by DACTherefore, in order to guarantee the performance improvement brought by the method adopting the signal prediction, the performance indexes of the linearity and the conversion time of the coarse quantization ADC and DAC and the requirement of the time required by the signal prediction algorithm must be determined. This will be described below.

(1) Signal prediction algorithm based on power spectrum estimation

When sampling signal x (n) can be decomposed into signal x in SDR receiving system_s(n) and x_w(n) when x is assumed_s(n) consists of P real sinusoids, and x_w(n) AWGN, considered as mean zero, is reasonable, so a narrow-band strong power signal x_s(n) is observed in an AWGN environment.

1) Modeling of signal prediction

Signal x_s(n) can be represented by P real sinusoidal signals,x is then_s(n) is:

in the formula: a. the_i，f_iAnd theta_iRespectively, the amplitude, frequency and starting phase of the ith sinusoidal signal. Signal x according to Pisarenko harmonic decomposition method_s(n) can be modeled as a 2P order Autoregressive (AR) model, expressed as:

wherein a is_iAre prediction coefficients. The modes of the roots of the characteristic equation of equation (15) are all 1, so there is symmetry in the coefficients of the characteristic polynomial of the AR model, i.e.: a is_i＝a_2P-iAnd the angular position of the root corresponding to the angular frequency of the sinusoidal signal lies on the unit circle, i.e. on

Thus, a prediction signal can be obtained

Comprises the following steps:

in the formula:

is white gaussian noise and is generated by the noise,

is the noise variance, which is statistically independent of the sine wave signal. By using

In place of x in the formula (16)_s(n-i) to obtain:

equation (17) shows the prediction signal

It can be modeled as a special autoregressive-moving average (ARMA) process with inputs of white gaussian noise (AWGN), AR and Moving Average (MA) all of the same order and parameters.

2) Power spectrum estimation and signal prediction coefficients

To obtain a prediction coefficient a_iMultiplying both sides of the formula (15) by x_s(n-k) and taking mathematical expectation, obtaining:

<math><mfenced open='' close=''> <mtable> <mtr> <mtd> <msub> <msub> <mi>R</mi> <mi>x</mi> </msub> <mi>s</mi> </msub> <mrow> <mo>(</mo> <mi>k</mi> <mo>)</mo> </mrow> <mo>+</mo> <munderover> <mi>Σ</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mrow> <mn>2</mn> <mi>P</mi> </mrow> </munderover> <msub> <mi>a</mi> <mi>i</mi> </msub> <msub> <msub> <mi>R</mi> <mi>x</mi> </msub> <mi>s</mi> </msub> <mrow> <mo>(</mo> <mi>k</mi> <mo>-</mo> <mi>i</mi> <mo>)</mo> </mrow> <mo>=</mo> <mn>0</mn> </mtd> <mtd> <mo>&ForAll;</mo> <mi>k</mi> <mo>-</mo> <mo>-</mo> <mo>-</mo> <mrow> <mo>(</mo> <mn>18</mn> <mo>)</mo> </mrow> </mtd> </mtr> </mtable> </mfenced></math>

in the formula:

is x_s(n) an autocorrelation function, and x_s(n) the sine wave signal is statistically independent of e (n)

Substituting the relationship of equation (19) into equation (18) can yield:

obviously, when k > 2P, the impulse function δ (·) in the summation term on the right side of equation (20) is always equal to zero, so the ARMA process of equation (7) follows the following normal equation by simplifying the above equation:

the formula of the normal equation (21) is similar to the modified Yule-Waller equation of the ARMA (2P, 2P) process, and the two are consistent in form, so the formula (21) can be also constructed into an overdetermined equation system, and the order 2P and the prediction coefficient a are solved by using the algorithm of Singular Value Decomposition (SVD) -total least square method (TLS) for the consideration of the accuracy and numerical stability of power spectrum estimation_i. Based on the above analysis, an ARMA modeling algorithm based on SVD-TLS harmonic recovery is used for signal x_sThe steps of the power spectrum estimation of (n) are briefly described as follows:

(a) first by the autocorrelation function of the previous sample

Constructing an extended autocorrelation matrix of formula (21)

(corresponding to the augmentation matrix) can be expressed as:

in the formula: p_e> 2P, and M > P;

(b) for the accuracy of estimation, the optimal order 2P and prediction coefficient vector are solved by using an SVD-TLS algorithm by adopting the decision condition of TLS estimation

(c) The 2P pair conjugate roots of the characteristic polynomial are calculated according to the following characteristic equation

Wherein: i is 1, …, P;

(d) the conjugate root according to the formula (23) utilizes the relationship

Calculating x_sFrequency of each harmonic of (n)

In order to obtain an estimated signal power

The autocorrelation function can be expressed as:

wherein:

is a sinusoidal signal

And white gaussian noise e (n) affects only the autocorrelation function with lag of zero

The value of (c). Therefore, when the hysteresis is k 1 … P, respectively, it can be obtained from equation (25):

frequency obtained by using step 4 of SVD-TLS-based harmonic recovery method

And an autocorrelation function calculated from previous samples

The power P of each sinusoidal signal can be obtained by solving equation (26)_i. Meanwhile, the variance of gaussian white noise is calculated according to equation (25) as:

prediction gain G of signal_P＝10log₁₀((P_s+P_w)/P_e) Is an index for measuring the SNR improvement degree of signal prediction, which is equivalent to that the resolution is improved by about G_P/6.02. The gain G is predicted as described above when using the modern parameterized power spectrum estimation method_PCan be derived as:

the above formula shows G_PWith P_s/P_wIs increased when P is increased_sWhen accurately estimated, the prediction gain G_PReaches the maximum value

Expressed as:

because, the optimal order 2P and prediction coefficient a of the present invention_iIs to use the decision conditions of the TLS estimation, compare with reference [3]]The method adopting the MSE judgment condition can provide more accurate signal estimation and can obtain higher prediction gain, so that the performance of SNR (namely the improvement of resolution ratio) can be improved more favorably by adopting the power spectrum estimation.

(2) Design considerations for the component modules

(1) Performance requirements of signal prediction unit

From the algorithm of the power spectrum estimation, it is known that the high-order signal prediction can improve the prediction accuracy and further improve the prediction gain, but the calculation difficulty of the solution is obviously increased, and the SPU has a large delay characteristic. When using sinusoidal signals as x_s(n) when the signal P is 1-5 respectively, establishing a behavior level model of each module, and predicting gain G_PAnd f/f_sBy simulating the relationship (2), it can be seen that when f/f is measured_sWhen 0, the curves corresponding to different orders P all reach the maximum prediction gain, because x is then the maximum prediction gain_s(n) ═ Asin θ is the steady state signal. With f/f_sIncrease, G_PThe decrease is significant, the smaller the order, the more the decrease, so it can be concluded that increasing the order P can significantly increase the prediction gain. If the resolution is increased by 4 bits, the order P should be greater than or equal to 2, and when P ≧ 4, the performance improvement is relatively small.

However, the high-order prediction can significantly increase the solution difficulty and the overhead of hardware implementation, and thus, a larger prediction delay affects the working rate of the system. When P is 1-5, the prediction delay is normalized by simulation (with P being 1, f/f)_sTime delay of 0 is normalized) and f/f_sWhen f/f is known_sNot equal to 0, relative to f/f_sThe delay increases slightly for 0 and increasing the order P increases the prediction delay. When P is larger than or equal to 4, the prediction delay is obviously increased because the solving difficulty is improved. With the simulation results and trade-off considerations, P-3, 4 are relatively optimal choices.

(2) Resolution requirements of DAC and coarse quantization ADC

The resolution of the coarse quantization ADC is first determined by the folding factor F_FTo determine, as N_coarseAt the same time, the quantization noise is required not to deteriorate the signal prediction performance, which requires the resolution of the coarse quantization ADC to be N_ed. If N is present_ed≥N_coarseThe resolution of CFC is chosen as N_edOtherwise, N_coarseAs the resolution of CFC, the resolution required to coarsely quantize the ADC is therefore expressed as N_CFC. DAC will predict the signal

Conversion to analogue

The purpose being to follow the high-power signal x_s(n) so that the full scale of the DAC needs to be consistent with the input signal x (n). Also, the error introduced by the noise of the DAC (only the quantization noise is considered in the behavioral level model) will add to e (n), which degrades the performance of the signal prediction unless the noise of the DAC is much smaller than e (n). Thus, the required resolution of the DAC is expressed as N_DAC. Obviously, increasing the resolution of the coarse quantization ADC and DAC effectively ensures the performance improvement of the signal prediction method. However, the tradeoff is that increasing the resolution of the coarse quantization ADC and DAC will reduce the conversion of the corresponding blockRate, which means that the series signal processing flow in fig. 1 requires longer conversion times, thereby limiting the speed of the overall ADC.

(3) Conversion time requirements for DAC and coarse quantization ADC

To obtain e (n), the overall delay of the feedback loop of fig. 1, consisting of coarse quantization ADC, SPU and DAC, cannot exceed one clock cycle. The conversion time of the coarse quantization ADC and DAC must be much less than the clock period. If the resolution ratios of the CFC and the DAC are respectively 5 bits and 8 bits according to the analysis of the resolution ratios. For the ADC with a full parallel structure, when the resolution is 4-5 bits, the sampling rate is generally 1 GHz-4 GHz under the current process level, and the conversion time is less than 1 ns. The DAC with the resolution of 8 bits can realize the conversion rate of 1 GHz-2 GHz, and the conversion time can also be less than 1 ns. Therefore, the conversion time to implement the DAC and coarse quantization ADC would not be a limiting factor if a 250MS/s conversion rate is required for this embodiment. The conversion time of a fine quantization ADC, which usually works in parallel with a coarse quantization ADC, is one clock cycle.

(4) Performance requirements of front-end single sample-and-hold circuit and subtractor

In this embodiment, the signal prediction based on the power spectrum estimation is combined into the 10-bit 250MS/s folding interpolation ADC, and when the SDR receiving system using the ADC of the present invention simulates a signal to be received at the front end, the requirement for the input dynamic range of the folding interpolation ADC is reduced, and the SNR above 24dB can be improved, which is equivalent to the resolution of 14bit under the premise of ensuring the unchanged conversion rate. Whereas the front-end single sample-and-hold circuit is located at the very front of the entire ADC, and x (n) is associated with the analog estimate

The difference of (a) is implemented at the output port of the front-end single sample-and-hold circuit, and therefore the performance requirements for the front-end sample-and-hold circuit are not relaxed, it must meet the 14-bit 250MS/s performance. Also because the input to the subtractor is x (n) and the analog estimate

The dynamic range of the two circuits is the same as that of a front-end single sample-and-hold circuit, so that the linearity of the subtracter needs to meet 14 bits, and the 3dB bandwidth is larger than 250 MHz.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A signal prediction folding interpolation ADC method based on power spectrum estimation is characterized in that:

comprising N_F＝N_coarse+N_fineThe device comprises a bit pipeline folding interpolation ADC, a signal prediction unit based on power spectrum estimation, a digital-to-analog converter and a subtraction unit; the assembly line folding interpolation ADC comprises a front-end single sampling hold circuit, a distributed sampling hold circuit, an analog folding preprocessing circuit, a fine quantization ADC and a coarse quantization ADC; input signals x (t) of ADC of analog front end of SDR receiving system are derived from channels of different standards, wave bands and modesThe ADC simulates the modulated signal composition processed by the front end, x (t) covers different frequency spectra and has different signal powers.

2. The power spectrum estimation-based signal prediction folding interpolation ADC method of claim 1, wherein: the sampling value output by the input signal x (t) after passing through the front end single sampling hold circuit is x (n), and x (n) is decomposed into a narrow-band signal x with strong signal power by a subtraction unit_s(n) and a broadband signal x of weak signal power_w(n) is: x (n) ═ x_s(n)+x_w(n) of (a). And x_s(n) and x_w(n) satisfies the following condition:

1)x_s(n) represents all narrow-band strong power sampling signals, the total power P of which_sCoverage total bandwidth range of B_s；x_w(n) represents all broadband low power sampled signals, with total power P_wCoverage total bandwidth range of B_w；

2) If f_sRepresenting the sampling frequency, f, of the ADC_s≥2B_w＞＞B_s，x_w(n) may be derived from Nyquist sampling, and x_s(n) is oversampling at a rate of f_sAnd B_sDetermining the ratio of (A) to (B);

3) due to p_s＞＞p_wStatistical properties of x (n) are represented by x_s(n) is determined, and x_sOversampling of (n), x (n) or x_s(n) with their adjacent signals x (n-1) or x, respectively_s(n-1) correlation. When a broadband signal x is used_w(n) when excited as input for signal prediction, the signal can be predicted from the previous sample x of a strong signal_s(n-1)、x_s(n-2) estimating the current value x_s(n)。

3. The power spectrum estimation-based signal prediction folding interpolation ADC method of claim 1, wherein:

the coarse quantization ADC quantizes the nth sampling point output by a single front-end sampling and holding circuit and outputs a digital signal e_d(n) of (a). Said power spectrum estimation based Signal Prediction Unit (SPU) is at e_d(n)Based on an estimate of the current sample value from the previous sample value, the SPU estimate output value comprising x_s(n) digital quantity estimationIt is composed of x_sFront sampled value [ x_s(n-1)，x_s(n-2)，...，x_s(n-2P)]Obtained by a power spectrum estimation algorithm.

4. The power spectrum estimation-based signal prediction folding interpolation ADC method of claim 1, wherein:

the DAC converts the digital value into an estimated value

Conversion into corresponding analog quantities

The difference, namely:

e (n) = x (n) - {\hat{x}}_{s} (n) = x_{w} (n) + x_{s} (n) - {\hat{x}}_{s} (n) - - - (1)

at this time, the signal processed by the pipeline folding interpolation ADC is a broadband low-power signal x_w(n) and prediction error

The dynamic range of the input signal is compressed.

5. The power spectrum estimation-based signal prediction folding interpolation ADC method of claim 1, wherein:

the signal prediction algorithm adopted by the signal prediction unit based on the power spectrum estimation is that x is used_w(n) white Gaussian noise, x, as mean zero_s(n) is observed in white Gaussian noise environment, and the Pisarenko harmonic decomposition method is adopted to predict the signal

The method can be modeled into a special autoregressive-moving average process with input of Gaussian white noise and the same autoregressive and moving average orders and parameters, and meets the following requirements:

wherein,is white gaussian noise, and is a noise,is the variance of the noise, a_iIs a prediction coefficient; from (3), the autoregressive-moving average process obeys the following equation:

is x_s(n) an autocorrelation function; the formula of the normal equation (4) is similar to the modified Yule-Waller equation of the autoregressive-moving average (2P, 2P) process, and the two equations are consistent in form, so the formula (4) can be also constructed into an over-definite equation set, the order 2P and the prediction coefficient a are solved by adopting the algorithm of singular value decomposition-total least square method in consideration of the accuracy and numerical stability of power spectrum estimation_iObtaining x_sFrequency of each harmonic of (n)The power P of each harmonic signal_iSatisfies the following formula:

from the above, respective sinusoidal signals can be obtainedPower P of_i(ii) a The variance of gaussian white noise is:

prediction gain G of signal_P＝10log₁₀((P_s+P_w)/P_e) Is an index for measuring the SNR improvement degree of signal prediction, which is equivalent to that the resolution is improved by about G_P/6.02；

The gain G is predicted as described above when using the modern parameterized power spectrum estimation method_PComprises the following steps:

Expressed as: