CN102610589A - Sram memory - Google Patents
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- CN102610589A CN102610589A CN2012100851620A CN201210085162A CN102610589A CN 102610589 A CN102610589 A CN 102610589A CN 2012100851620 A CN2012100851620 A CN 2012100851620A CN 201210085162 A CN201210085162 A CN 201210085162A CN 102610589 A CN102610589 A CN 102610589A
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Abstract
The invention relates to an SRAM memory, comprising a substrate provided with a plurality of memory units which are arranged in rows and columns; a first medium layer covering the memory units; a second medium layer arranged on the first medium layer; and a plurality of bit line sets which are parallel to each other, the bit line set comprises a bit line and a complementary bit line, the bit line set has a plurality of straight line area and a twisted area connected with the straight line area, wherein the straight line area comprises a first straight line area and a second straight line area, the bit line in said straight line area is located on different medium layers, and is parallel to projection of the complementary bit line on the substrate; the bit line in the first straight line overlaps an extension line of the complementary bit line in the second straight line area, the complementary bit line in the first straight line overlaps the extension line of the bit line in the second straight line. In embodiment of the invention, the SRAM memory reduces coupling capacitance between the bit line and the complementary bit line.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of SRAM memory.
Background technology
Static random access memory (SRAM) is as a member in the volatile storage; Have high-speed, low-power consumption and standard technology advantage such as compatibility mutually, be widely used in PC, personal communication, consumption electronic product fields such as (smart card, digital camera, multimedia players).Particularly, high-speed synchronous SRAM is used for the application such as cache buffer memory devices such as work stations, and cache store saves as the data or the instruction that utilize again storage at a high speed is provided.
In the SRAM memory of existing 6T (6transistor) structure; Be used to store and read the same metal level that is positioned at that the set of bit lines (comprising: bit line and paratope line) of the signal of SRAM memory is parallel to each other usually; Between this set of bit lines and the adjacent bit lines group because the cross-interference issue of signal often appears in the existence of coupling capacitance; Cause the signal degradation of set of bit lines transmission, efficient and speed reduce when storing and reading the signal of SRAM memory through set of bit lines.
A kind ofly reduce that the method for coupling capacitance is a distortion set of bit lines separated by a distance between the set of bit lines; With reference to figure 1; Fig. 1 is existing structural representation with twist structured set of bit lines; Said set of bit lines comprises: bit line BL and paratope line BLB; Said set of bit lines has linearity sector 20 and distortion district 10, and the straight line portion 101 of bit line BL and the straight line portion 103 of paratope line BLB 20 are parallel to each other and are positioned at same metal level in the linearity sector, such as: second metal level (M2); The straight line portion 101 of bit line BL twists on the extended line of straight line portion 103 of paratope line BLB through being positioned at its line of torsion 102 with one deck in distortion district 10, and the straight line portion 103 of paratope line BLB twists into through the line of torsion 104 that is positioned at different metal layer (the first or the 3rd metal level) with it in distortion district 10 on the extended line of straight line portion 101 of bit line BL.
Though can reduce the coupling capacitance between set of bit lines and the adjacent bit lines group through above-mentioned distorted-structure, the bit line and the coupling capacitance between the paratope line of each set of bit lines itself can't reduce, and the cross-interference issue of signal still can occur.
More introductions about the SRAM memory please refer to the United States Patent (USP) that publication number is US2011/0007556A1.
Summary of the invention
The problem that the present invention solves provides a kind of SRAM memory, has reduced the coupling capacitance between bit line and the paratope line.
For addressing the above problem, the embodiment of the invention provides a kind of SRAM memory, comprising:
Substrate is positioned at and is a plurality of memory cell that ranks are arranged in the substrate;
Cover first dielectric layer of said memory cell and be positioned at second dielectric layer on first dielectric layer;
The a plurality of set of bit lines that are parallel to each other, said set of bit lines comprises bit line and paratope line, said set of bit lines has a plurality of linearity sectors and the distortion district that is connected the linearity sector,
Wherein, Said linearity sector comprises first linearity sector and second linearity sector; The bit line of said linearity sector and paratope line are positioned at the different medium layer; The bit line of said linearity sector and paratope line are parallel to each other in suprabasil projection, and the extended line of the paratope line of the bit line of said first linearity sector and second linearity sector is overlapping, and the extended line of the bit line of the paratope line of said first linearity sector and second linearity sector is overlapping;
Said distortion district comprises the first distortion district and the second distortion district; Wherein, Twist the bit line on first dielectric layer of first linearity sector to second dielectric layer of second linearity sector in the first distortion district, and the paratope line on second dielectric layer of first linearity sector is twisted to first dielectric layer of second linearity sector; Twist the bit line on second dielectric layer of second linearity sector to first dielectric layer of first linearity sector in the second distortion district, and the paratope line on first dielectric layer of second linearity sector is twisted to second dielectric layer of first linearity sector.
Optional, the spacing between the adjacent distortion district on said each set of bit lines equates.
Optional, the quantity in the distortion district on the different set of bit lines equates.
Optional, the distributing position in the distortion district on the different set of bit lines is identical, and the line between the distortion district of same position is vertical with the bearing of trend of the bit line of set of bit lines and paratope line.
Optional, the bit line of set of bit lines is parallel with the row or the row arragement direction of memory cell with the bearing of trend of paratope line.
Optional, the position of the spacer region between the position in the distortion district on each set of bit lines and two consecutive storage units is corresponding.
Optional, the quantity of corresponding memory cell is 16～256 between adjacent two the distortion districts on each set of bit lines.
Optional, the bit line of each set of bit lines and the paratope line zone outside the distortion district respectively with memory cell in corresponding transistor electrical connection.
Optional; The said first distortion district comprises: be arranged in second dielectric layer first connector and second connector, be positioned at the first bit line folding line on second dielectric layer, be positioned at the first paratope line folding line on first dielectric layer; Bit line on first dielectric layer of first linearity sector twists to second dielectric layer of second linearity sector through first connector and the first bit line folding line, and the paratope line on second dielectric layer of first linearity sector twists to first dielectric layer of second linearity sector through second connector and the first paratope line folding line.
Optional; The said second distortion district comprises: be arranged in second dielectric layer the 3rd connector and the 4th connector, be positioned at the second bit line folding line on first dielectric layer, be positioned at the second paratope line folding line on second dielectric layer; Bit line on second dielectric layer of second linearity sector twists to first dielectric layer of first linearity sector through the 3rd connector and the second bit line folding line, and the paratope line on first dielectric layer of second linearity sector twists to second dielectric layer of first linearity sector through the 4th connector and the second paratope line folding line.
Optional, the same side of said each set of bit lines also has power line, and power line and bit line and paratope line are parallel to each other, and power line is used for power supply to memory cell corresponding crystal pipe being provided.
Optional, said power line is positioned on first dielectric layer.
The present invention also provides a kind of SRAM memory, comprising:
Substrate is positioned at and is a plurality of memory cell that ranks are arranged in the substrate;
Cover first dielectric layer of said memory cell and be positioned at second dielectric layer on first dielectric layer;
The a plurality of set of bit lines that are parallel to each other, said set of bit lines comprises bit line and paratope line, said set of bit lines has a plurality of linearity sectors and the distortion district that is connected the linearity sector,
Wherein, Said linearity sector comprises first linearity sector and second linearity sector; The bit line of said linearity sector and paratope line are positioned at the different medium layer; The bit line of said linearity sector and paratope line are parallel to each other in suprabasil projection, and the extended line of the paratope line of the bit line of said first linearity sector and second linearity sector is overlapping, and the extended line of the bit line of the paratope line of said first linearity sector and second linearity sector is overlapping;
Said distortion district comprises the first distortion district and the second distortion district; Wherein, Twist the bit line on second dielectric layer of first linearity sector to first dielectric layer of second linearity sector in the first distortion district, and the paratope line on first dielectric layer of first linearity sector is twisted to second dielectric layer of second linearity sector; Twist the bit line on first dielectric layer of second linearity sector to second dielectric layer of first linearity sector in the second distortion district, and the paratope line on second dielectric layer of second linearity sector is twisted to first dielectric layer of first linearity sector.
Optional, the spacing between the adjacent distortion district on said each set of bit lines equates.
Optional, the quantity in the distortion district on the different set of bit lines equates.
Optional, the distributing position in the distortion district on the different set of bit lines is identical, and the line between the distortion district of same position is vertical with the bearing of trend of the bit line of set of bit lines and paratope line.
Optional, the bearing of trend of set of bit lines is parallel with the row of memory cell or row arragement direction.
Optional, the position of the spacer region between the position in the distortion district on each set of bit lines and two consecutive storage units is corresponding.
Optional, the quantity of corresponding memory cell is 16～256 between adjacent two distortion districts of each set of bit lines.
Optional, the bit line of each set of bit lines and the paratope line zone outside the distortion district respectively with memory cell in corresponding transistor electrical connection.
Optional; The said first distortion district comprises: be arranged in second dielectric layer first connector and second connector, be positioned at the first bit line folding line on first dielectric layer, be positioned at the first paratope line folding line on second dielectric layer; Bit line on second dielectric layer of first linearity sector twists to first dielectric layer of second linearity sector through first connector and the first bit line folding line, and the paratope line on first dielectric layer of first linearity sector is twisted to second dielectric layer of second linearity sector through second connector and the first paratope line folding line.
Optional; The said second distortion district comprises: be arranged in second dielectric layer the 3rd connector and the 4th connector, be positioned at the second bit line folding line on second dielectric layer, be positioned at the second paratope line folding line on first dielectric layer; Bit line on first dielectric layer of second linearity sector twists to second dielectric layer of first linearity sector through the 3rd connector and the second bit line folding line, and the paratope line on second dielectric layer of second linearity sector twists to first dielectric layer of first linearity sector through the 3rd connector and the second paratope line folding line.
Optional, the same side of said each set of bit lines also has power line, and power line and bit line and paratope line are parallel to each other, and power line is used for power supply to memory cell corresponding crystal pipe being provided.
Optional, said power line is positioned on first dielectric layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
The district makes each set of bit lines neutrality line be positioned at different dielectric layers across with paratope line through distortion, has both reduced the coupling capacitance between the set of bit lines, reduces the coupling capacitance between each set of bit lines neutrality line and the paratope line again;
Further; The distributing position in the distortion district on the different set of bit lines is identical; Line between the distortion district of same position is vertical with the bearing of trend of the bit line of set of bit lines and paratope line; Make that the distance between the bit line on the same dielectric layer and the distance between the distance between the bit line, bit line and the paratope line and the bit line on the different medium layer and the distance between the bit line, bit line and paratope line keeps constant in the set of bit lines; Make between the bit line and bit line of different set of bit lines, between bit line and the paratope line and the coupling capacitance between paratope line and the paratope line keep constant; Certain regional coupling capacitance can not occur than other regional excessive or too small situation, improve the stability of SRAM memory;
Further; Spacing between the adjacent distortion district on said each set of bit lines equates; The quantity in the distortion district on the difference set of bit lines equates, the memory cell that bit line and the better corresponding suprabasil ranks of paratope line are arranged outside the feasible distortion district, thus make connection bit line and the paratope line that the corresponding crystal pipe can be easier in the memory cell; Improve the layout of SRAM memory, reduced the wiring difficulty of each metal connecting line of SRAM memory.
Description of drawings
Fig. 1 is existing structural representation with twist structured set of bit lines;
Fig. 2～Fig. 7 is the structural representation of embodiment of the invention SRAM memory.
Embodiment
The bit line of existing SRAM memory and paratope line are positioned at same metal level; When writing through bit line (paratope line) or reading high level signal; Because the existence of coupling capacitance between bit line and the paratope line, paratope line (bit line) can drag down the level in the bit line, makes that the voltage difference between bit line and the paratope line diminishes; Thereby be difficult to discern the signal condition in bit line or the paratope line, produce crosstalking between the signal.
The inventor proposes a kind of SRAM memory for this reason; Bit line between two adjacent distortion districts is arranged on different dielectric layer (metal level) with paratope line; Increase the distance between bit line and the paratope line, thereby reduced the coupling capacitance between bit line and the paratope line.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.When the embodiment of the invention was detailed, for ease of explanation, sketch map can be disobeyed general ratio and done local the amplification, and said sketch map is example, and it should not limit protection scope of the present invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 is the plan structure sketch map of first embodiment of the invention SRAM memory; Fig. 3 is the cross-sectional view of Fig. 2 along line of cut a-b direction; Fig. 4 is the cross-sectional view of Fig. 2 along line of cut c-d direction.
With reference to figure 2, said SRAM memory comprises:
The substrate (not shown) is positioned at and is a plurality of memory cell (not shown)s that ranks are arranged in the substrate, comprises some transistors in each memory cell, such as: 4,6 or 8;
Cover the first dielectric layer (not shown) of said memory cell and be positioned at the second dielectric layer (not shown) on first dielectric layer;
The a plurality of set of bit lines 50 that are parallel to each other, said set of bit lines comprise bit line BL and the paratope line BLB corresponding with bit line, and said set of bit lines has a plurality of linearity sectors and the distortion district that is connected the linearity sector,
Wherein, Said linearity sector comprises first linearity sector 28 and second linearity sector 29; The bit line of said linearity sector and paratope line are positioned at the different medium layer; The bit line of said linearity sector and paratope line are parallel to each other in suprabasil projection, and the extended line of the paratope line of the bit line of said first linearity sector 28 and second linearity sector 29 is overlapping, and the extended line of the bit line of the paratope line of said first linearity sector 28 and second linearity sector 29 is overlapping;
Said distortion district comprises the 31 and second distortion district 32, the first distortion district; Wherein, Twist the bit line on first dielectric layer of first linearity sector 28 306 to second dielectric layer of second linearity sector 29 in the first distortion district 31, and the paratope line on second dielectric layer of first linearity sector 28 310 is twisted to first dielectric layer of second linearity sector 29; Twist the bit line on second dielectric layer of second linearity sector 29 303 to first dielectric layer of first linearity sector 28 in the second distortion district 32, and the paratope line on first dielectric layer of second linearity sector 29 307 is twisted to second dielectric layer of first linearity sector 28;
Be positioned at the power line Vss of the same side of each set of bit lines 50, power line Vss and bit line and paratope line are parallel to each other, and power line Vss is used for power supply to memory cell corresponding crystal pipe being provided.
Only show 4 set of bit lines 50 among Fig. 2, comprise first set of bit lines, second set of bit lines, the 3rd set of bit lines, the 4th set of bit lines.Have 2 distortion districts on each set of bit lines 50, comprise the 31 and second distortion district 32, the first distortion district.In concrete embodiment; The quantity of said set of bit lines 50 is greater than 4; Distortion district is greater than 2 on each set of bit lines 50, when distortion district on each set of bit lines 50 greater than 2 the time, the structure of set of bit lines 50 distortion districts and linearity sector is the repetition of said structure; Need to prove that 2 on 4 set of bit lines shown in Fig. 2 and each set of bit lines are twisted the district only as an example, and should not limit protection scope of the present invention.
With reference to figure 2, Fig. 3 and Fig. 4; The said first distortion district 31 comprises: be arranged in second dielectric layer 302 first connector 305 and second connector 309, be positioned at the first bit line folding line 304 on second dielectric layer 302, be positioned at the first paratope line folding line 308 on first dielectric layer 301; Bit line 301 on first dielectric layer 301 of first linearity sector 28 twists to second dielectric layer 302 of second linearity sector 29 through first connector 305 and the first bit line folding line 304, and the paratope line 310 on second dielectric layer 302 of first linearity sector 28 twists to first dielectric layer 301 of second linearity sector 29 through second connector 309 and the first paratope line folding line 308.
With reference to figure 2; The said second distortion district 32 comprises: be arranged in second dielectric layer the 3rd connector 311 and the 4th connector 312, be positioned at the second bit line folding line 314 on first dielectric layer, be positioned at the second paratope line folding line 313 on second dielectric layer; Bit line 303 on second dielectric layer of second linearity sector 29 twists to first dielectric layer of first linearity sector 28 through the 3rd connector 311 and the second bit line folding line 314, on second dielectric layer of the paratope line 307 on first dielectric layer of second linearity sector 29 through the 4th connector 312 and second paratope line folding line distortion, 314 to first linearity sectors 28.
Bit line on the first bit line folding line 304 and the second bit line folding line 314 and the respective media layer is same metal level; And the first bit line folding line 304 and the second bit line folding line are skew lines; To save the bit line that distortion district 31 takies and the space of paratope line, more be of value to the layout of SRAM memory.
Paratope line on the first paratope line folding line 308 and the second paratope line folding line 313 and the respective media layer is same metal level; The first paratope line folding line 308 and the second paratope line folding line are skew lines; To save the bit line that distortion district 31 takies and the space of paratope line, more be of value to the layout of SRAM memory.
The district makes each set of bit lines 50 neutrality line be positioned at different dielectric layers across with paratope line through distortion, has both reduced the coupling capacitance between the set of bit lines 50, reduces the coupling capacitance between each set of bit lines 50 neutrality line and the paratope line again.
Since the existence in distortion district, the bit line in each set of bit lines 50 and the paratope line zone outside the distortion district respectively with memory cell in corresponding transistor electrical connection.
The bit line of set of bit lines 50 is parallel with the row or the row arragement direction of memory cell with the bearing of trend of paratope line; The position of the spacer region between the position in the distortion district on said each set of bit lines 50 and two consecutive storage units is corresponding; Said correspondence is meant that the distortion district is in the spacer region of the projection in the substrate 300 between two consecutive storage units; The distortion district is arranged in first dielectric layer 301 and second dielectric layer 302 of the correspondence of the spacer region top between two consecutive storage units; Make the distortion district can not influence being connected of corresponding crystal pipe in bit line and paratope line and the memory cell, such as: bit line and paratope line can be through directly running through first dielectric layer 301 and/or second dielectric layer 302 connector and memory cell in being connected of corresponding crystal pipe.
The distributing position in the distortion district on the different set of bit lines 50 is identical; Line between the distortion district of the same position on the different set of bit lines 50 is vertical with the bearing of trend of the bit line of set of bit lines and paratope line; Make in the set of bit lines 50 distance between the bit line on the same dielectric layer and the distance between the distance between the bit line, bit line and the paratope line and the bit line on the different medium layer and the distance between the bit line, bit line and paratope line keep constant; Make between the bit line and bit line of different set of bit lines, between bit line and the paratope line and the coupling capacitance between paratope line and the paratope line keep constant; Certain regional coupling capacitance can not occur than other regional excessive or too small situation, improve the stability of SRAM memory.
Spacing between the adjacent distortion district on said each set of bit lines 50 equates; The quantity in the distortion district on the different set of bit lines 50 equates; Make the memory cell that bit line and ranks in the better corresponding substrate 300 of paratope line outside the distortion district on the set of bit lines 50 are arranged; Thereby make the corresponding crystal pipe can be easier in the memory cell connection bit line and paratope line, improved the layout of SRAM memory, reduced the wiring difficulty of each metal connecting line of SRAM memory.
Said power line Vss is positioned on first dielectric layer 301.
The quantity of corresponding memory cell is 16～256 between the two adjacent distortion districts on each set of bit lines 50, and the quantity of the memory cell of said correspondence is the quantity of adjacent two memory cell of distortion district between two projections in the substrate 300.
Fig. 5 is the plan structure sketch map of second embodiment of the invention SRAM memory; Fig. 6 is the cross-sectional view of Fig. 5 along line of cut a-b direction; Fig. 7 is the cross-sectional view of Fig. 5 along line of cut c-d direction.
With reference to figure 5, said SRAM memory comprises:
The substrate (not shown) is positioned at and is a plurality of memory cell (not shown)s that ranks are arranged in the substrate, comprises some transistors in each memory cell, such as: 4,6 or 8;
Cover the first dielectric layer (not shown) of said memory cell and be positioned at the second dielectric layer (not shown) on first dielectric layer;
The a plurality of set of bit lines 50 that are parallel to each other, said set of bit lines 50 comprise bit line BL and the paratope line BLB corresponding with bit line BL, and said set of bit lines has a plurality of linearity sectors and the distortion district that is connected the linearity sector,
Wherein, Said linearity sector comprises first linearity sector 28 and second linearity sector 29; The bit line of said linearity sector and paratope line are positioned at the different medium layer; The bit line of said linearity sector and paratope line are parallel to each other in suprabasil projection, and the extended line of the paratope line of the bit line of said first linearity sector 28 and second linearity sector 29 is overlapping, and the extended line of the bit line of the paratope line of said first linearity sector 28 and second linearity sector 29 is overlapping;
Said distortion district comprises the 31 and second distortion district 32, the first distortion district; Wherein, Twist the bit line on second dielectric layer of first linearity sector 28 306 to first dielectric layer of second linearity sector 29 in the first distortion district 31, and the paratope line on first dielectric layer of first linearity sector 28 310 is twisted to second dielectric layer of second linearity sector 29; Twist the bit line on first dielectric layer of second linearity sector 29 303 to second dielectric layer of first linearity sector 28 in the second distortion district 32, and the paratope line on second dielectric layer of second linearity sector 29 307 is twisted to first dielectric layer of first linearity sector 28;
Be positioned at the power line Vss of the same side of each set of bit lines 50, power line Vss and bit line and paratope line are parallel to each other, and power line Vss is used for power supply to memory cell corresponding crystal pipe being provided.
Only show 4 set of bit lines 50 among Fig. 5, comprise first set of bit lines, second set of bit lines, the 3rd set of bit lines, the 4th set of bit lines.Have 2 distortion districts on each set of bit lines 50, comprise the 31 and second distortion district 32, the first distortion district.In concrete embodiment; The quantity of said set of bit lines 50 is greater than 4; Distortion district is greater than 2 on each set of bit lines 50, when distortion district on each set of bit lines 50 greater than 2 the time, the structure of set of bit lines 50 distortion districts and linearity sector is the repetition of said structure; Need to prove that 2 on 4 set of bit lines shown in Fig. 5 and each set of bit lines are twisted the district only as an example, and should not limit protection scope of the present invention.
With reference to figure 5, Fig. 6 and Fig. 7; The said first distortion district 31 comprises: be arranged in second dielectric layer 302 first connector 305 and second connector 309, be positioned at the first bit line folding line 304 on first dielectric layer 301, be positioned at the first paratope line folding line 308 on second dielectric layer 302; Bit line 306 on second dielectric layer 302 of first linearity sector 28 twists to first dielectric layer 301 of second linearity sector 29 through first connector 305 and the first bit line folding line 304, and the paratope line on first dielectric layer 301 of first linearity sector 28 310 is twisted to second dielectric layer 302 of second linearity sector 29 through second connector 309 and the first paratope line folding line 308.
With reference to figure 5; The said second distortion district 32 comprises: be arranged in second dielectric layer the 3rd connector 311 and the 4th connector 312, be positioned at the second bit line folding line 314 on second dielectric layer, be positioned at the second paratope line folding line 313 on first dielectric layer; Bit line 303 on first dielectric layer of second linearity sector 29 twists to second dielectric layer of first linearity sector 28 through the 3rd connector 311 and the second bit line folding line 314, and the paratope line 307 on second dielectric layer of second linearity sector 29 twists to first dielectric layer of first linearity sector 28 through the 3rd connector 312 and the second paratope line folding line 313.
The first bit line folding line 304 and the second bit line folding line 314 are same metal level with the bit line of equivalent layer; And the first bit line folding line 304 and the second bit line folding line are skew lines; To save the bit line that distortion district 31 takies and the space of paratope line, more be of value to the layout of SRAM memory.
The first paratope line folding line 308 and the second paratope line folding line 313 are same metal level with the paratope line of equivalent layer; The first paratope line folding line 308 and the second paratope line folding line are skew lines; To save the bit line that distortion district 31 takies and the space of paratope line, more be of value to the layout of SRAM memory.
Make through distortion district the different dielectric layer that is positioned at of each set of bit lines 50 neutrality line and paratope line intersection both to have reduced the coupling capacitance between the set of bit lines 50, reduce the coupling capacitance between each set of bit lines 50 neutrality line and the paratope line again.
Since the existence in distortion district, the bit line in each set of bit lines 50 and the paratope line zone outside the distortion district respectively with memory cell in corresponding transistor electrical connection.
The bit line of set of bit lines 50 is parallel with the row or the row arragement direction of memory cell with the bearing of trend of paratope line; The position of the spacer region between the position in the distortion district on said each set of bit lines 50 and two consecutive storage units is corresponding; Said correspondence is meant that the distortion district is in the spacer region of the projection in the substrate 300 between two consecutive storage units; The distortion district is arranged in first dielectric layer 301 and second dielectric layer 302 of the correspondence of the spacer region top between two consecutive storage units; Make the distortion district can not influence being connected of corresponding crystal pipe in bit line and paratope line and the memory cell, such as: bit line and paratope line can be through directly running through first dielectric layer 301 and/or second dielectric layer 302 connector and memory cell in being connected of corresponding crystal pipe.
The distributing position in the distortion district on the different set of bit lines 50 is identical; Line between the distortion district of the same position on the different set of bit lines 50 is vertical with the bearing of trend of the bit line of set of bit lines and paratope line; Make in the set of bit lines 50 distance between the bit line on the same dielectric layer and the distance between the distance between the bit line, bit line and the paratope line and the bit line on the different medium layer and the distance between the bit line, bit line and paratope line keep constant; Make between the bit line and bit line of different set of bit lines, between bit line and the paratope line and the coupling capacitance between paratope line and the paratope line keep constant; Certain regional coupling capacitance can not occur than other regional excessive or too small situation, improve the stability of SRAM memory.
Spacing between the adjacent distortion district on said each set of bit lines 50 equates; The quantity in the distortion district on the different set of bit lines 50 equates; Make the memory cell that bit line and ranks in the better corresponding substrate 300 of paratope line outside the distortion district on the set of bit lines 50 are arranged; Thereby make the corresponding crystal pipe can be easier in the memory cell connection bit line and paratope line, improved the layout of SRAM memory, reduced the wiring difficulty of each metal connecting line of SRAM memory.
Said power line Vss is positioned on first dielectric layer 301.
The quantity of corresponding memory cell is 16～256 between adjacent two distortion districts on each set of bit lines 50, and the quantity of the memory cell of said correspondence is the quantity of adjacent two memory cell of distortion district between two projections in the substrate 300.
To sum up; The SRAM memory that the embodiment of the invention provides; Make through distortion district the different dielectric layer that is positioned at of each set of bit lines neutrality line and paratope line intersection both to have reduced the coupling capacitance between the set of bit lines, reduce the coupling capacitance between each set of bit lines neutrality line and the paratope line again;
Further; The distributing position in the distortion district on the different set of bit lines is identical; Line between the distortion district of same position is vertical with the bearing of trend of the bit line of set of bit lines and paratope line; Make that the distance between the bit line on the same dielectric layer and the distance between the distance between the bit line, bit line and the paratope line and the bit line on the different medium layer and the distance between the bit line, bit line and paratope line keeps constant in the set of bit lines; Make between the bit line and bit line of different set of bit lines, between bit line and the paratope line and the coupling capacitance between paratope line and the paratope line keep constant; Certain regional coupling capacitance can not occur than other regional excessive or too small situation, improve the stability of SRAM memory;
Further; Spacing between the adjacent distortion district on said each set of bit lines equates; The quantity in the distortion district on the difference set of bit lines equates, the memory cell that bit line and the better corresponding suprabasil ranks of paratope line are arranged outside the feasible distortion district, thus make connection bit line and the paratope line that the corresponding crystal pipe can be easier in the memory cell; Improve the layout of SRAM memory, reduced the wiring difficulty of each metal connecting line of SRAM memory.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (24)
1. a SRAM memory is characterized in that, comprising:
Substrate is positioned at and is a plurality of memory cell that ranks are arranged in the substrate;
Cover first dielectric layer of said memory cell and be positioned at second dielectric layer on first dielectric layer;
The a plurality of set of bit lines that are parallel to each other, said set of bit lines comprises bit line and paratope line, said set of bit lines has a plurality of linearity sectors and the distortion district that is connected the linearity sector,
Wherein, Said linearity sector comprises first linearity sector and second linearity sector; The bit line of said linearity sector and paratope line are positioned at the different medium layer; The bit line of said linearity sector and paratope line are parallel to each other in suprabasil projection, and the extended line of the paratope line of the bit line of said first linearity sector and second linearity sector is overlapping, and the extended line of the bit line of the paratope line of said first linearity sector and second linearity sector is overlapping;
Said distortion district comprises the first distortion district and the second distortion district; Wherein, Twist the bit line on first dielectric layer of first linearity sector to second dielectric layer of second linearity sector in the first distortion district, and the paratope line on second dielectric layer of first linearity sector is twisted to first dielectric layer of second linearity sector; Twist the bit line on second dielectric layer of second linearity sector to first dielectric layer of first linearity sector in the second distortion district, and the paratope line on first dielectric layer of second linearity sector is twisted to second dielectric layer of first linearity sector.
2. SRAM memory as claimed in claim 1 is characterized in that, the spacing between the adjacent distortion district on said each set of bit lines equates.
3. SRAM memory as claimed in claim 2 is characterized in that, the quantity in the distortion district on the different set of bit lines equates.
4. SRAM memory as claimed in claim 3 is characterized in that, the distributing position in the distortion district on the different set of bit lines is identical, and the line between the distortion district of same position is vertical with the bearing of trend of the bit line of set of bit lines and paratope line.
5. SRAM memory as claimed in claim 1 is characterized in that, the bit line of set of bit lines is parallel with the row or the row arragement direction of memory cell with the bearing of trend of paratope line.
6. SRAM memory as claimed in claim 5 is characterized in that, the position of the spacer region between the position in the distortion district on each set of bit lines and two consecutive storage units is corresponding.
7. SRAM memory as claimed in claim 5 is characterized in that, the quantity of corresponding memory cell is 16～256 between adjacent two the distortion districts on each set of bit lines.
8. SRAM memory as claimed in claim 5 is characterized in that, the bit line of each set of bit lines and the paratope line zone outside distortion district respectively with memory cell in corresponding transistor electrical connection.
9. SRAM memory as claimed in claim 1; It is characterized in that; The said first distortion district comprises: be arranged in second dielectric layer first connector and second connector, be positioned at the first bit line folding line on second dielectric layer, be positioned at the first paratope line folding line on first dielectric layer; Bit line on first dielectric layer of first linearity sector twists to second dielectric layer of second linearity sector through first connector and the first bit line folding line, and the paratope line on second dielectric layer of first linearity sector twists to first dielectric layer of second linearity sector through second connector and the first paratope line folding line.
10. SRAM memory as claimed in claim 1; It is characterized in that; The said second distortion district comprises: be arranged in second dielectric layer the 3rd connector and the 4th connector, be positioned at the second bit line folding line on first dielectric layer, be positioned at the second paratope line folding line on second dielectric layer; Bit line on second dielectric layer of second linearity sector twists to first dielectric layer of first linearity sector through the 3rd connector and the second bit line folding line, and the paratope line on first dielectric layer of second linearity sector twists to second dielectric layer of first linearity sector through the 4th connector and the second paratope line folding line.
11. SRAM memory as claimed in claim 1 is characterized in that the same side of said each set of bit lines also has power line, power line and bit line and paratope line are parallel to each other, and power line is used for power supply to memory cell corresponding crystal pipe being provided.
12. SRAM memory as claimed in claim 11 is characterized in that said power line is positioned on first dielectric layer.
13. a SRAM memory is characterized in that, comprising:
Substrate is positioned at and is a plurality of memory cell that ranks are arranged in the substrate;
Cover first dielectric layer of said memory cell and be positioned at second dielectric layer on first dielectric layer;
The a plurality of set of bit lines that are parallel to each other, said set of bit lines comprises bit line and paratope line, said set of bit lines has a plurality of linearity sectors and the distortion district that is connected the linearity sector,
Wherein, Said linearity sector comprises first linearity sector and second linearity sector; The bit line of said linearity sector and paratope line are positioned at the different medium layer; The bit line of said linearity sector and paratope line are parallel to each other in suprabasil projection, and the extended line of the paratope line of the bit line of said first linearity sector and second linearity sector is overlapping, and the extended line of the bit line of the paratope line of said first linearity sector and second linearity sector is overlapping;
Said distortion district comprises the first distortion district and the second distortion district; Wherein, Twist the bit line on second dielectric layer of first linearity sector to first dielectric layer of second linearity sector in the first distortion district, and the paratope line on first dielectric layer of first linearity sector is twisted to second dielectric layer of second linearity sector; Twist the bit line on first dielectric layer of second linearity sector to second dielectric layer of first linearity sector in the second distortion district, and the paratope line on second dielectric layer of second linearity sector is twisted to first dielectric layer of first linearity sector.
14. SRAM memory as claimed in claim 13 is characterized in that, the spacing between the adjacent distortion district on said each set of bit lines equates.
15. SRAM memory as claimed in claim 14 is characterized in that, the quantity in the distortion district on the different set of bit lines equates.
16. SRAM memory as claimed in claim 15 is characterized in that, the distributing position in the distortion district on the different set of bit lines is identical, and the line between the distortion district of same position is vertical with the bearing of trend of the bit line of set of bit lines and paratope line.
17. SRAM memory as claimed in claim 13 is characterized in that, the bearing of trend of set of bit lines is parallel with the row of memory cell or row arragement direction.
18. SRAM memory as claimed in claim 17 is characterized in that, the position of the spacer region between the position in the distortion district on each set of bit lines and two consecutive storage units is corresponding.
19. SRAM memory as claimed in claim 17 is characterized in that, the quantity of corresponding memory cell is 16～256 between adjacent two distortion districts of each set of bit lines.
20. SRAM memory as claimed in claim 17 is characterized in that, the bit line of each set of bit lines and the paratope line zone outside distortion district respectively with memory cell in corresponding transistor electrical connection.
21. SRAM memory as claimed in claim 13; It is characterized in that; The said first distortion district comprises: be arranged in second dielectric layer first connector and second connector, be positioned at the first bit line folding line on first dielectric layer, be positioned at the first paratope line folding line on second dielectric layer; Bit line on second dielectric layer of first linearity sector twists to first dielectric layer of second linearity sector through first connector and the first bit line folding line, and the paratope line on first dielectric layer of first linearity sector is twisted to second dielectric layer of second linearity sector through second connector and the first paratope line folding line.
22. SRAM memory as claimed in claim 13; It is characterized in that; The said second distortion district comprises: be arranged in second dielectric layer the 3rd connector and the 4th connector, be positioned at the second bit line folding line on second dielectric layer, be positioned at the second paratope line folding line on first dielectric layer; Bit line on first dielectric layer of second linearity sector twists to second dielectric layer of first linearity sector through the 3rd connector and the second bit line folding line, and the paratope line on second dielectric layer of second linearity sector twists to first dielectric layer of first linearity sector through the 3rd connector and the second paratope line folding line.
23. SRAM memory as claimed in claim 13 is characterized in that the same side of said each set of bit lines also has power line, power line and bit line and paratope line are parallel to each other, and power line is used for power supply to memory cell corresponding crystal pipe being provided.
24. SRAM memory as claimed in claim 23 is characterized in that said power line is positioned on first dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100851620A CN102610589A (en) | 2012-03-27 | 2012-03-27 | Sram memory |
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| CN2012100851620A CN102610589A (en) | 2012-03-27 | 2012-03-27 | Sram memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107084697A (en) * | 2017-04-20 | 2017-08-22 | 武汉新芯集成电路制造有限公司 | Memory cell distortion measurement method |
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| CN1607608A (en) * | 2003-10-14 | 2005-04-20 | 松下电器产业株式会社 | Semiconductor memory device |
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| US5014110A (en) * | 1988-06-03 | 1991-05-07 | Mitsubishi Denki Kabushiki Kaisha | Wiring structures for semiconductor memory device |
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