CN102610536A - Method for forming top metal - Google Patents
Method for forming top metal Download PDFInfo
- Publication number
- CN102610536A CN102610536A CN2012100935202A CN201210093520A CN102610536A CN 102610536 A CN102610536 A CN 102610536A CN 2012100935202 A CN2012100935202 A CN 2012100935202A CN 201210093520 A CN201210093520 A CN 201210093520A CN 102610536 A CN102610536 A CN 102610536A
- Authority
- CN
- China
- Prior art keywords
- district
- metal
- level
- layer
- metal level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for forming top metal, comprising the steps of: forming a baffle layer on a metal insulating layer with a tungsten channel, etching the baffle layer to form a through hole, forming a metal layer, and reducing a step difference so as to facilitate subsequently formed photoresistance to completely cover the surface of an apparatus, thereby solving the problem that the top metal cannot be realized by a traditional technique and a traditional photoresistance. On the other hand, lithography alignment is carried out based on the surface of the metal layer of a first area lower than the surface of the metal layer of a second area, so the aligning process is not affected due to deteriorating transmittance caused by metal grains and an increase of thickness, and possible defect in quality is avoided.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of formation method of top-level metallic.
Background technology
In traditional semiconductor fabrication process; Top-level metallic (Top Metal) is an indispensable part, and usually required in the industry top-level metallic thickness can not surpass 4um, still along with the development of association area; Requirement to inductance component progressively improves; More excellent quality factor q value just need be arranged, can improve Q value, and the resistivity of reduction top-level metallic generally adopts top-level metallic to thicken to reach owing to reduce the resistivity of top-level metallic; So More and more factories has been made higher requirement to the thickness of top-level metallic, even can require to reach the thick top-level metallic of 10um.
Top-level metallic can inevitably produce lines in forming process, simultaneously because the increase of thickness; Light transmittance reduces greatly; This makes troubles to photoetching process again, makes that aiming at (alignment) promptly so-called mistake accurate (mis-alignment) can occur than mistake; This serious meeting influences product quality, even causes and scrap.
On the other hand, consider top-level metallic after passivation (passivation), need to make weld pad; Lead-in wire etc.; Normally will adopt photoetching process, the conventional photoresistance (PR) that uses can arrive the thickness of 4.9um, and this formation to the top-level metallic of 4um and following thickness is acceptable.Yet, consider the character of photoresistance, it can not pile up thickness arbitrarily, and such as for the top-level metallic behind the needed 6um, common process and conventional photoresistance can not be satisfied the demand.Be top-level metallic and its step difference of rete formation on every side; The height of this step difference becomes big along with the increase of top-level metallic thickness; After acquiring a certain degree, the height of its step difference has surpassed the height that conventional photoresistance can tire out, and causes photoresistance to cover completely.In order to address the above problem, produced corresponding photoresistance in the industry, but what be to use that this type photoresistance will face is that bigger fund is bought and to the corresponding optimization and the cleaning of equipment, increased production cost undoubtedly greatly.
Summary of the invention
The technical problem that the present invention will solve is to adopt conventional photoresistance to realize the formation of the above top-level metallic of 6um and solve the accurate problem of mistake that causes owing to thickness and the interference of metal lines
For solving the problems of the technologies described above, the present invention provides a kind of formation method of top-level metallic, comprising:
Substrate is provided, has the metal connecting line district on the said substrate;
On said substrate, form the barrier layer, said barrier layer exposes said metal connecting line district;
Form metal level, said metal level comprises the first district's metal level that covers said metal connecting line district, and covers second district's metal level on said barrier layer, and wherein, the surface of first district's metal level is lower than the surface of second district's metal level;
Form first photoresist layer, said first photoresist layer covers said first district's metal level and second district's metal level;
Lithography alignment is carried out on the surface that is lower than second district's metal level based on the surface of first district's metal level, and said first photoresist layer is carried out photoetching;
With first photoresist layer after the photoetching is mask, and etching second district's metal level forms top-level metallic.
Further, for the formation method of said top-level metallic, after forming top-level metallic, also comprise the steps:
Remove first photoresist layer after the photoetching;
Form passivation layer, said passivation layer covers top-level metallic and barrier layer;
Form second photoresist layer, said second photoresist layer covers said passivation layer;
Further, for the formation method of said top-level metallic, the thickness of said second photoresist layer is less than 5um.
Further, for the formation method of said top-level metallic, said barrier layer thickness is 2～6um.
Further, for the formation method of said top-level metallic, said metal connecting line district comprises: the metal dielectric layer between a plurality of tungsten passages and a plurality of tungsten passage.
Further, for the formation method of said top-level metallic, the material on said barrier layer is silicon dioxide and/or silicon nitride.
Further, for the formation method of said top-level metallic, the thickness of said top-level metallic is greater than 6um.
Compared with prior art, the formation method of top-level metallic provided by the invention owing to form earlier one deck barrier layer, makes step difference diminish, and covering device is surperficial fully thereby make the photoresistance of follow-up formation.
On the other hand; Lithography alignment is carried out on the surface that is lower than second district's metal level based on the surface of first district's metal level; Make alignment procedures can not be affected, avoided the defective that possibly occur qualitatively owing to metal lines and thickness increase the light transmission variation that is caused.
Description of drawings
Fig. 1 is the schematic flow sheet of formation method of the top-level metallic of the embodiment of the invention;
Fig. 2～Figure 10 is the cross-sectional view of formation method of the top-level metallic of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the formation method of top-level metallic of the present invention is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Please refer to Fig. 1, it is the schematic flow sheet of formation method of the top-level metallic of the embodiment of the invention.As shown in Figure 1, the formation method of said top-level metallic comprises the steps:
Step S101 provides substrate, has the metal connecting line district on the said substrate;
Step S102 forms the barrier layer on said substrate, said barrier layer exposes said metal connecting line district;
Step S103 forms metal level, and said metal level comprises the first district's metal level that covers said metal connecting line district, and covers second district's metal level on said barrier layer, and wherein, the surface of first district's metal level is lower than the surface of second district's metal level;
Step S104 forms first photoresist layer, and said first photoresist layer covers said first district's metal level and second district's metal level;
Step S105, lithography alignment is carried out on the surface that is lower than second district's metal level based on the surface of first district's metal level, and said first photoresist layer is carried out photoetching;
Step S106 is a mask with first photoresist layer after the photoetching, and etching second district's metal level forms top-level metallic.
Then, please refer to Fig. 1 and Fig. 2～Figure 10, it is the cross-sectional view of formation method of the top-level metallic of the embodiment of the invention.
As shown in Figure 2, substrate 20 is provided, have metal connecting line district 23 on the said substrate 20.Concrete, said substrate 20 comprises substrate 21, and is formed at the metal dielectric layer 22 in the said substrate 21, is formed with tungsten passage 24 in the said metal dielectric layer 22, the metal dielectric layer 22 between adjacent a plurality of tungsten passages 24 reach constitutes metal connecting line districts 23.
Please refer to Fig. 3, form barrier layer 31, said barrier layer 31 covers said substrate 20, promptly on metal dielectric layer 22 and tungsten passage 24, forms barrier layer 31, and said barrier layer 31 can be silicon dioxide (SiO
2), silicon nitride (SiN) or other insulating properties materials, shown in the thickness on barrier layer 31 be 2～6um.
As shown in Figure 4, form patterned light blockage layer 41 on the said barrier layer 31, wherein; Said patterned light blockage layer 41 is negative photoresistance; The thickness of said patterned light blockage layer 41 is 10000～20000 dusts, has through hole 42 in the patterned light blockage layer 41, exposes barrier layer 31.
Please refer to Fig. 5, the said barrier layer 31 of etching forms through hole 51, and the width of said through hole 51 can reach and expose metal connecting line district, below 23.Simultaneously, remove patterned light blockage layer 41 on the barrier layer 31.
Preferably, in above-mentioned steps, also carry out the measurement of critical dimension depth-width ratio (CD Aspect Ratio), make the critical dimension depth-width ratio more than or equal to 2: 1, to reach technological effect preferably.
Please refer to Fig. 6; In said barrier layer 31 and metal connecting line district 23, form metal level 60, said metal level 60 comprises first district's metal level 62 that covers said metal connecting line district 23 and the second district's metal level 61 that covers said barrier layer 31, wherein; The surface of first district's metal level 62 is lower than the surface of second district's metal level 61; Be that metal level 60 has groove 63, said groove 63 will solve the alignment issues that the above metal level of 6um possibly occur greatly, and this will combine Fig. 7 to be elaborated below.
Please refer to Fig. 7, on metal level, form first photoresist layer 71, carry out photoetching process; Obviously be to need to aim at during its photoetching, yet as a rule, metal can have lines when forming; Disturb thereby can produce the aligning in the photoetching process, in addition, along with the increase of metal level 60 thickness; Light transmittance reduces greatly, and problem that mistake aim at and/or can't aim at occur with regard to being easy to this moment, and the present invention has then solved this problem.Concrete; Lithography alignment is carried out on the surface that is lower than second district's metal level based on the surface of first district's metal level; Promptly according to the aligning object of reference (be similar to the function of align mark) of the groove on the metal level 60 63 as photoetching; Carry out lithography alignment, then said first photoresist layer is carried out photoetching process.Because the accuracy of above-mentioned through hole 41 is assurable, and metal level 60 also is even formation,, thereby can be used as the foundation of aligning so said groove 63 also is to have suitable accuracy.In actual production, a plurality of grooves as shown in Figure 7 63 are arranged on the silicon chip, these regularly arranged grooves 63 have been guaranteed the accuracy of alignment procedures in photoetching process, the problem of having avoided mistake to aim at and/or can't aim at has been guaranteed yield.
Please refer to Fig. 8, through having removed first photoresist layer on second district's metal level 61 after the photoetching process, keep first photoresist layer 71 on first district's metal level 61 '.
Please refer to Fig. 9, is mask with first photoresist layer after the photoetching, and etching is removed the second district metal level, form top-level metallic 60 ', certainly, at formation top-level metallic 60 ' afterwards, first photoresist layer on just removable first district's metal level.Then, continue, form passivation layer 91 with reference to figure 9, said passivation layer 91 cover top-level metallics 60 ' with barrier layer 31, wherein, shown in passivation layer 91 can be that silicon dioxide, silicon nitride or the two combine, other materials with similar quality also can.At this moment, because the existence on barrier layer 31, make top-level metallic 60 ' dwindled with the step difference between the rete (, being barrier layer 31) on every side at this.
Please refer to Figure 10, behind the passivation technology, then can go between etc. top-level metallic; At this moment, need carry out photoetching process earlier, can know by above-mentioned analysis; Because step difference has dwindled, maximum has only 4um usually, and this thickness is obviously in the scope that conventional photoresistance can cover; Then second photoresist layer 101 is covered on the passivation layer 91, passivation layer 91 (top-level metallic 60 ') can occur this moment and be exposed to outer situation, subsequent technique also can carry out smoothly.
Compared with prior art, the formation method of top-level metallic provided by the invention owing to form earlier one deck barrier layer, makes step difference diminish, and covering device is surperficial fully thereby make the photoresistance of follow-up formation.
On the other hand; Because metal level is evenly to form; Lithography alignment is carried out on the surface that can be lower than second district's metal level based on the surface of first district's metal level; Promptly according to the aligning object of reference of the groove on the metal level, thereby make alignment procedures can not receive influence, avoided the defective that possibly occur qualitatively owing to metal lines and thickness increase the light transmission variation that is caused as photoetching.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.
Claims (7)
1. the formation method of a top-level metallic is characterized in that, comprising:
Substrate is provided, has the metal connecting line district on the said substrate;
On said substrate, form the barrier layer, said barrier layer exposes said metal connecting line district;
Form metal level, said metal level comprises the first district's metal level that covers said metal connecting line district, and covers second district's metal level on said barrier layer, and wherein, the surface of first district's metal level is lower than the surface of second district's metal level;
Form first photoresist layer, said first photoresist layer covers said first district's metal level and second district's metal level;
Lithography alignment is carried out on the surface that is lower than second district's metal level based on the surface of first district's metal level, and said first photoresist layer is carried out photoetching;
With first photoresist layer after the photoetching is mask, and etching second district's metal level forms top-level metallic.
2. the formation method of top-level metallic as claimed in claim 1 is characterized in that, after forming top-level metallic, also comprises the steps:
Remove first photoresist layer after the photoetching;
Form passivation layer, said passivation layer covers top-level metallic and barrier layer;
Form second photoresist layer, said second photoresist layer covers said passivation layer.
3. the formation method of top-level metallic as claimed in claim 2 is characterized in that, the thickness of said second photoresist layer is less than 5um.
4. the formation method of top-level metallic as claimed in claim 1 is characterized in that, said barrier layer thickness is 2～6um.
5. the formation method of top-level metallic as claimed in claim 1 is characterized in that, said metal connecting line district comprises: the metal dielectric layer between a plurality of tungsten passages and a plurality of tungsten passage.
6. the formation method of top-level metallic as claimed in claim 1 is characterized in that, the material on said barrier layer is silicon dioxide and/or silicon nitride.
7. the formation method of top-level metallic as claimed in claim 1 is characterized in that, the thickness of said top-level metallic is greater than 6um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210093520.2A CN102610536B (en) | 2012-03-31 | 2012-03-31 | A kind of forming method of top-level metallic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210093520.2A CN102610536B (en) | 2012-03-31 | 2012-03-31 | A kind of forming method of top-level metallic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102610536A true CN102610536A (en) | 2012-07-25 |
| CN102610536B CN102610536B (en) | 2016-11-16 |
Family
ID=46527824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210093520.2A Active CN102610536B (en) | 2012-03-31 | 2012-03-31 | A kind of forming method of top-level metallic |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102610536B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154621A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Planarization method and method for forming isolation structure of top metal layer |
| CN102024720A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2012
- 2012-03-31 CN CN201210093520.2A patent/CN102610536B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154621A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Planarization method and method for forming isolation structure of top metal layer |
| CN102024720A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102610536B (en) | 2016-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11037882B2 (en) | Overlay mark | |
| US9508650B2 (en) | Semiconductor device with layout of wiring layer and dummy patterns | |
| US9437415B2 (en) | Layer alignment in FinFET fabrication | |
| CN101047165B (en) | Overlay mark arrangement for reducing overlay shift | |
| CN106597818B (en) | Alignment mark, the method and semiconductor devices for forming alignment mark | |
| JP2013195912A (en) | Mask and manufacturing method of semiconductor device | |
| CN104299960A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| US8022560B2 (en) | Overlay mark | |
| US6821687B2 (en) | Photo mask for fabricating semiconductor device having dual damascene structure | |
| KR20000041461A (en) | Fabrication method of improved image sensor | |
| JP4969724B2 (en) | Semiconductor device, manufacturing method thereof, and database creation method for masking level | |
| CN104299913B (en) | The manufacture method of thin film transistor (TFT) | |
| CN102610536A (en) | Method for forming top metal | |
| CN100547762C (en) | Form the method for contact hole | |
| US20140293469A1 (en) | Color filter layer and method of fabricating the same | |
| CN103839769A (en) | Method for forming patterns | |
| CN113050392B (en) | Alignment test structure, preparation method and alignment test method | |
| CN102437020A (en) | Control wafer and forming method thereof | |
| JP5217527B2 (en) | Electronic devices | |
| CN102479758B (en) | Structure for reducing etching residue | |
| CN111106008B (en) | Planarization reverse etching method | |
| CN102683278A (en) | Chip separation method | |
| CN103579075A (en) | Semiconductor structure for controlling feature sizes with plasma and manufacturing method thereof | |
| CN101750875A (en) | Method for monitoring photoetching quality | |
| US20190131142A1 (en) | Manufacturing method for trench |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140425 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140425 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |