CN102610517A - Method for forming front metal dielectric layer - Google Patents
Method for forming front metal dielectric layer Download PDFInfo
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- CN102610517A CN102610517A CN2012100646382A CN201210064638A CN102610517A CN 102610517 A CN102610517 A CN 102610517A CN 2012100646382 A CN2012100646382 A CN 2012100646382A CN 201210064638 A CN201210064638 A CN 201210064638A CN 102610517 A CN102610517 A CN 102610517A
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Abstract
The invention discloses a method for forming a front metal dielectric layer. The method includes: providing a semiconductor substrate with an NMOS (N-channel metal oxide semiconductor) transistor and a PMOS (P-channel metal oxide semiconductor) transistor; depositing a buffer oxidization layer; depositing a first etching barrier layer with high pressure stress on the buffer oxidization layer; depositing a first front metal dielectric layer with pressure stress; coating photoresist on a PMOS area of the semiconductor substrate and etching the buffer oxidization layer, the first etching barrier layer and the first front metal dielectric layer on an NMOS after photoetching; depositing a second etching barrier layer with high tensile stress on the surface of a semiconductor device; depositing a second front metal dielectric layer with tensile stress on the second etching barrier layer; and grinding and polishing the second front metal dielectric layer. By the aid of the front metal dielectric layer formed by the method, the carrier mobility of the NMOS and the PMOS can be simultaneously increased, so that the performance of the semiconductor device is improved.
Description
Technical field
The present invention relates to microelectronic, relate in particular to a kind of method that forms preceding metal and dielectric matter layer.
Background technology
Along with the integrated circuit characteristic line breadth narrows down to below the 90nm, people have introduced the electromobility that heavily stressed silicon nitride technology improves charge carrier gradually.Through on N/PMOS the deposition height draw with the high pressure stress silicon nitride as via etch stop the layer (Contact Etch Stop a Layer; CESL); Especially below the 65nm processing procedure; In order to improve the electromobility of N/PMOS simultaneously, need sometimes simultaneously deposition high draw with the high pressure stress silicon nitride on different MOS.After the etch stop layer deposition is accomplished; Metal and dielectric matter layer before need depositing subsequently; What adopt at present is to utilize the method for high-density plasma (HDP CVD) to deposit, and also has to adopt high-aspect-ratio processing procedure (HARP, High Aspect Ratio Process) to deposit.The membrane stress of these two kinds of processing procedure depositions is different; Wherein HDP processing procedure film has compression; And HARP processing procedure film has tension stress; Single deposition HDP or HARP film can only be favourable to a kind of transistorized carrier mobility wherein, so this method has limited and at utmost improves transistorized performance.
Shown in figure 1a to Fig. 1 e, in the method for metal and dielectric matter layer, comprise the following steps basically that before existing formation process chart is referring to shown in Figure 2:
A kind of NMOS of having and PMOS are provided transistorized Semiconductor substrate 0, and deposition one first buffer oxide layer 1 and has first etch stop layer 2 of high tensile stress on Semiconductor substrate 0, i.e. silicon nitride layer, and effect is shown in Fig. 1 a after the completion;
The nmos area territory of 4 coating semiconductor substrates 0 with photoresist carries out after the photoetching first buffer oxide layer 1, first etch stop layer 2 of top, PMOS zone are carried out etching, and design sketch is shown in Fig. 1 b after accomplishing;
Deposit second buffer oxide layer 7 at semiconductor device surface and also adopt silicon nitride layer with second etch stop layer, 5, the second etch stop layers 5 with high pressure stress, effect is shown in Fig. 1 c after accomplishing;
The PMOS of 4 coating semiconductor substrates 0 zone carries out after the photoetching second buffer oxide layer 7 and second etch stop layer 5 above the nmos area territory being carried out etching with photoresist, and effect is shown in Fig. 1 d after accomplishing;
Metal and dielectric matter layer 8 (utilizing HDP or HARP to accomplish) before the deposition on semiconductor device, and grind and polish, the effect after final the completion is shown in Fig. 1 e.
A kind of among HDP film or the HARP film of the pmd layer that utilizes above-mentioned existing method preparation, still, (HDP is a compression, and the range of stress is at 100Mpa～300MPa on the contrary because HDP is with HARP membrane stress situation; HARP is a tension stress, and the range of stress is in that 100Mpa～200MPa), they are merely able to help a kind of transistorized performance boost.
Summary of the invention
To the problem of above-mentioned existence, the purpose of this invention is to provide a kind of method that forms two stress etch stop layers and preceding metal and dielectric matter layer.This method has taken into full account the difference of different its deposit film stress of CVD processing procedure; The preceding metal and dielectric matter layer that has compression at the PMOS area deposition; And the preceding metal and dielectric matter layer that has tension stress at the nmos area area deposition; Metal and dielectric matter layer helps improving simultaneously the carrier mobility of PMOS and NMOS before adopting this method formed, thereby improves the performance of semiconductor device.
The objective of the invention is to realize through following technical proposals:
The method of metal and dielectric matter layer is characterized in that before a kind of the formation, comprises the following steps:
A kind of NMOS of having and PMOS are provided transistorized Semiconductor substrate;
Deposition one buffer oxide layer on said Semiconductor substrate;
Deposition one has first etch stop layer of high pressure stress on said buffer oxide layer;
On said first etch stop layer deposition one have compression first before metal and dielectric matter layer;
Apply the PMOS zone of said Semiconductor substrate with photoresist, carry out after the photoetching metal and dielectric matter layer before the buffer oxide layer above the nmos area territory, first etch stop layer and first being carried out etching;
Second etch stop layer that has high tensile stress in the semiconductor device surface deposition;
On second etch stop layer deposition have tension stress second before metal and dielectric matter layer;
The second preceding metal and dielectric matter layer is carried out grinding and polishing.
The method of metal and dielectric matter layer before the above-mentioned formation, wherein, said buffer oxide layer is a silicon oxide layer.
The method of metal and dielectric matter layer before the above-mentioned formation, wherein, said first etch stop layer and said second etch stop layer are silicon nitride layer.
The method of metal and dielectric matter layer before the above-mentioned formation, wherein, said deposition process with first preceding metal and dielectric matter layer of compression is HDP CVD, the compression scope is at 100MPa～300MPa.
The method of metal and dielectric matter layer before the above-mentioned formation, wherein, said deposition process with second preceding metal and dielectric matter layer of tension stress is SACVD, the tension stress scope is at 100MPa～200MPa.
The method of metal and dielectric matter layer before the above-mentioned formation, wherein, said SACVD is HARP.
The method of metal and dielectric matter layer before the above-mentioned formation; Wherein, The thickness of said buffer oxide layer is 50～200; The thickness of said first etch stop layer or said second etch stop layer is 200～800, and the thickness of metal and dielectric matter layer is 1000～10000 before the said first preceding metal and dielectric matter layer or said second.
The method of metal and dielectric matter layer before the above-mentioned formation, wherein, the depositing temperature of all said depositing operations is 300 ℃～500 ℃.
Compared with present technology, beneficial effect of the present invention is:
Metal and dielectric matter layer helps improving simultaneously the carrier mobility of PMOS and NMOS before adopting this method formed, thereby improves the performance of semiconductor device.The inventive method is compared with existing method, on technology step simple relatively, lacked one illumination, from device performance, can improve the carrier mobility of NMOS/PMOS simultaneously.
Description of drawings
Fig. 1 a, Fig. 1 b, Fig. 1 c, Fig. 1 d and Fig. 1 e are respectively the processing step decomposing state sketch mapes of the method for metal and dielectric matter layer before forming in the prior art;
Fig. 2 is the schematic process flow diagram of the method for metal and dielectric matter layer before forming in the prior art;
Fig. 3 a, Fig. 3 b, Fig. 3 c, Fig. 3 d and Fig. 3 e are respectively the processing step decomposing state sketch mapes of the method for metal and dielectric matter layer before the present invention forms;
Fig. 4 is the schematic process flow diagram of the method for metal and dielectric matter layer before the present invention forms.
Embodiment
Below in conjunction with schematic diagram and concrete operations embodiment the present invention is described further.
Shown in Fig. 3 a to Fig. 3 e, simultaneously referring to shown in Figure 4, the method for metal and dielectric matter layer specifically comprised the following steps: before the present invention formed
A kind of NMOS of having and PMOS are provided transistorized Semiconductor substrate 0; Deposition one buffer oxide layer 1 on Semiconductor substrate 0; Deposition one has first etch stop layer 2 of high pressure stress on buffer oxide layer 1; On first etch stop layer 2 deposition one have compression first before metal and dielectric matter layer 3, buffer oxide layer 1 is a silicon oxide layer, the completion after effect shown in Fig. 3 a;
The PMOS of 4 coating semiconductor substrates zone carries out after the photoetching metal and dielectric matter layer 3 before the buffer oxide layer 1 above the nmos area territory, first etch stop layer 2 and first being carried out etching with photoresist, and effect is shown in Fig. 3 b after accomplishing;
Shown in Fig. 3 c, has second etch stop layer 5 of high tensile stress in the semiconductor device surface deposition;
On second etch stop layer 5 deposition have tension stress second before metal and dielectric matter layer 6, the completion after effect shown in Fig. 3 d, first etch stop layer 2 and second etch stop layer 5 are silicon nitride layer.
At last the second preceding metal and dielectric matter layer 6 is carried out grinding and polishing, effect is shown in Fig. 3 e after accomplishing.
In above-mentioned preparation technology's flow process, the deposition process with first preceding metal and dielectric matter layer 3 of compression is high-density plasma chemical vapor deposition technology (HDP CVD), and the compression scope is at 100MPa～300MPa.Deposition process with second preceding metal and dielectric matter layer 6 of tension stress is a time atmospheric pressure chemical vapor deposition method (SACVD), is specially high-aspect-ratio making technology (HARP), and the tension stress scope is at 100MPa～200MPa.Wherein, The thickness of buffer oxide layer 1 is 50～200; The thickness of first etch stop layer 2 or second etch stop layer 5 is 200～800; The thickness of the metal and dielectric matter layer 3 or the second preceding metal and dielectric matter layer 6 is 1000～10000 before first, and the depositing temperature of depositing operation is 300 ℃～500 ℃.
More than specific embodiment of the present invention is described in detail, but the present invention is not restricted to the specific embodiment of above description, it is just as example.To those skilled in the art, any equivalent modifications and alternative also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of having done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (8)
1. the method for the preceding metal and dielectric matter layer of formation is characterized in that, comprises the following steps:
A kind of NMOS of having and PMOS are provided transistorized Semiconductor substrate;
Deposition one buffer oxide layer on said Semiconductor substrate;
Deposition one has first etch stop layer of high pressure stress on said buffer oxide layer;
On said first etch stop layer deposition one have compression first before metal and dielectric matter layer;
Apply the PMOS zone of said Semiconductor substrate with photoresist, carry out after the photoetching metal and dielectric matter layer before the buffer oxide layer above the nmos area territory, first etch stop layer and first being carried out etching;
Second etch stop layer that has high tensile stress in the semiconductor device surface deposition;
On second etch stop layer deposition have tension stress second before metal and dielectric matter layer;
The second preceding metal and dielectric matter layer is carried out grinding and polishing.
2. the method for metal and dielectric matter layer is characterized in that said buffer oxide layer is a silicon oxide layer before the formation as claimed in claim 1.
3. the method for metal and dielectric matter layer is characterized in that said first etch stop layer and said second etch stop layer are silicon nitride layer before the formation as claimed in claim 1.
4. the method for metal and dielectric matter layer is characterized in that before the formation as claimed in claim 1, and said deposition process with first preceding metal and dielectric matter layer of compression is HDP CVD, and the compression scope is at 100MPa～300MPa.
5. the method for metal and dielectric matter layer is characterized in that before the formation as claimed in claim 1, and said deposition process with second preceding metal and dielectric matter layer of tension stress is SACVD, and the tension stress scope is at 100MPa～200MPa.
6. the method for metal and dielectric matter layer is characterized in that said SACVD is HARP before the formation as claimed in claim 5.
7. the method for metal and dielectric matter layer before the formation as claimed in claim 1; It is characterized in that; The thickness of said buffer oxide layer is 50～200; The thickness of said first etch stop layer or said second etch stop layer is 200～800, and the thickness of metal and dielectric matter layer is 1000～10000 before the said first preceding metal and dielectric matter layer or said second.
8. the method for metal and dielectric matter layer is characterized in that the depositing temperature of all said depositing operations is 300 ℃～500 ℃ before the formation as claimed in claim 1.
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| CN2012100646382A CN102610517A (en) | 2012-03-13 | 2012-03-13 | Method for forming front metal dielectric layer |
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| CN2012100646382A CN102610517A (en) | 2012-03-13 | 2012-03-13 | Method for forming front metal dielectric layer |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050260810A1 (en) * | 2004-05-21 | 2005-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for selectively forming strained etch stop layers to improve FET charge carrier mobility |
| CN1822337A (en) * | 2005-01-15 | 2006-08-23 | 应用材料公司 | Substrate having silicon germanium material and stressed silicon nitride layer |
| CN101226900A (en) * | 2007-01-18 | 2008-07-23 | 国际商业机器公司 | Structure and method of fabricating electrical structure having improved charge mobility |
| CN101256982A (en) * | 2007-02-28 | 2008-09-03 | 联华电子股份有限公司 | Method for manufacturing strain silicium complementary metal oxide semiconductor transistor |
| US20090020791A1 (en) * | 2007-07-16 | 2009-01-22 | Shaofeng Yu | Process method to fabricate cmos circuits with dual stress contact etch-stop liner layers |
| US20090020823A1 (en) * | 2007-07-20 | 2009-01-22 | Tomohiro Fujita | Semiconductor device and method for manufacturing the same |
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2012
- 2012-03-13 CN CN2012100646382A patent/CN102610517A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050260810A1 (en) * | 2004-05-21 | 2005-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for selectively forming strained etch stop layers to improve FET charge carrier mobility |
| CN1822337A (en) * | 2005-01-15 | 2006-08-23 | 应用材料公司 | Substrate having silicon germanium material and stressed silicon nitride layer |
| CN101226900A (en) * | 2007-01-18 | 2008-07-23 | 国际商业机器公司 | Structure and method of fabricating electrical structure having improved charge mobility |
| CN101256982A (en) * | 2007-02-28 | 2008-09-03 | 联华电子股份有限公司 | Method for manufacturing strain silicium complementary metal oxide semiconductor transistor |
| US20090020791A1 (en) * | 2007-07-16 | 2009-01-22 | Shaofeng Yu | Process method to fabricate cmos circuits with dual stress contact etch-stop liner layers |
| US20090020823A1 (en) * | 2007-07-20 | 2009-01-22 | Tomohiro Fujita | Semiconductor device and method for manufacturing the same |
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Application publication date: 20120725 |