CN102609395A - Variable-size block-shaped FFT (fast Fourier transform) operation device with single outer and inner interleaving structure - Google Patents
Variable-size block-shaped FFT (fast Fourier transform) operation device with single outer and inner interleaving structure Download PDFInfo
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Abstract
The invention provides a variable-size block-shaped FFT operation device with a single outer and inner interleaving structure. The device mainly comprises one or more block-shaped operation devices, a twiddle factor storage device, an in-block interleaving address storage device, an out-of-block storage controller, an out-of-block interleaving address storage device, an out-of-block data storage device and an out-of-block data path selector, wherein the block-shaped operation device includes an in-block input data path selector, a butterfly-shaped operation device, an in-block storage controller, an in-block data storage device, and an in-block output data path selector. According to the invention, a user can automatically generate all data interleaving addresses and twiddle factor values according to a selected data bit width, and store the data interleaving addresses and twiddle factor values to a corresponding storage device for call by hardware. The device provided by the invention supports FFT operation of arbitrary 2n points, and can obviate dispersion of addressing space after blocking treatment so as to improve data closure. Meanwhile, the data interleaving addressing complexity is lowered because both the data in each block and all out-of-block data have the identical interleaving mode.
Description
Technical field
The present invention relates to field of computer architecture, particularly a kind of variable-sized block FFT arithmetic unit of single inside and outside pilotaxitic texture.
Background technology
FFT is the improvement and the optimization of DFT (DFT), utilizes the relevant mathematical property of DFT, improves calculated performance through using various algorithms cleverly.Need huge calculated amount owing to realize Fourier transform on computers, the appearance of FFT just makes these theories and method to realize on computers and to popularize just.
The Cooley-Tukey algorithm is first kind of fft algorithm, and it can use matrix and tensor product denotational description following:
Wherein F is the Fourier matrix,
ω
N=exp (2 π i/N), 0≤p, q＜N,
is rotated factor matrix, is defined as:
Ir is a unit matrix.
Below explanation will be used above symbolic representation.
FFT has the address discrete feature on algorithm origin property, i.e. the complete butterfly structure output of each grade always can not be delivered to complete butterfly input of next stage fully.This address discrete feature is for the closure of data, and the full parallelization processing of algorithm is unfavorable.When the fft algorithm of long sequence is broken down into a plurality of short sequence FFT algorithm, can have the lot of data exchange, this has just reduced the efficient of algorithm parallelization.Block FFT can disperse control within limits with data address, and can make interblock data interlacing mode single, but can not guarantee that interleaving mode is single in the piece, and it is too numerous and diverse that this just makes hardware realize.In addition, this method is for general 2
nThe count calculating support difficulty comparatively of FFT, it is too small to use the scope of counting.Therefore, the unicity of the inside and outside interleaving mode of research, and framework difference 2 flexibly
nThe block FFT arithmetic unit of counting is comparatively necessary.
Document that can reference has following several pieces:
[1]J.W.Cooley?and?J.W.Tukey，“An?algorithm?for?the?machine?calculation?of?complex?Fourier?series，”Math.Comput.，vol.19，no.2，1969；
[2]C.S.Bums?and?P.W.Eschenbacher，“An?in-place，in-order?prime?factor?FFT?algorithm，”IEEE?Trans.Acoust.，Speech，Signal?Processing，vol.ASSP-29，pp.806-817，-1979；
[3]Bevan?M.Baas.“An?Approach?to?Low-Power，High-Performance?FAST?FOURIER?TRANSFORM?PROCESSOR?DESIGN”，Stanford?University，1999。
Document [1] discloses a kind of fft algorithm first, and document [2] discloses a kind of parallel fft algorithm, and document [3] discloses a kind of low-power consumption fft algorithm.
Summary of the invention
The technical matters that (one) will solve
Technical matters to be solved by this invention is: traditional FFT arithmetic unit data interlacing scope is big, and interlace mode is not unique, causes that thus hardware configuration is complicated, the problem that operation efficiency is low.In addition, the present invention is used to also solve that traditional FFT arithmetic unit computational data is counted and bit wide is fixed, and uses the problem of underaction.
(2) technical scheme
The objective of the invention is in order to overcome the shortcoming of prior art, disclosed FFT arithmetic unit has used the block decomposition method of single inside and outside pilotaxitic texture.
The present invention proposes a kind of FFT arithmetic unit, is used to accomplish 2
nPoint FFT calculates, and n is a natural number, it is characterized in that; Comprise: one or more block arithmetic units; Be respectively applied for the independent of N_local point FFT computing block and calculate, wherein this N_local is the number of data points that a block arithmetic unit once can read in and calculate, and is not more than 2
nThe outer data storage device of piece is used to store the data of calculating through N_local point FFT; The piece file memory controller is used for 1 N_local point of every completion FFT and calculates, and according to the outer data interlacing address of correct piece result of calculation is deposited into said outer data storage device; The piece address storage devices that interweaves outward is used for the needed interleaving address of storage block file memory controller.
(3) beneficial effect
FFT arithmetic unit of the present invention can carry out the FFT computing with the variable-sized block fft algorithm of single inside and outside pilotaxitic texture; Not only retrained the discretize degree of data address; Reduced communication-cost, and increased the closure of data, made algorithm be easier to parallelization; In addition, the present invention has greatly improved the dirigibility of hardware designs, counts for difference, and the FFT of different bit wides calculates need not change hardware structure.
Description of drawings
Fig. 1 is the structural representation of FFT arithmetic unit provided by the invention;
Fig. 2 is the tupe synoptic diagram that the present invention calculates 16 FFT;
Fig. 3 is that the present invention carries out interlace mode synoptic diagram in 8 fft blocks;
Fig. 4 is that the present invention carries out 64 fft blocks pattern diagram that interweaves outward.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
Block decomposition method can solve the excessive hardware complexity that causes of data interlacing scope, and can improve the data closure of calculating.Single inside and outside pilotaxitic texture can be simplified hardware designs, reduces the data reading times.In order to adapt to the data point of multiple bit wide, according to the present invention, the user can generate all data interlacing addresses and twiddle factor numerical value automatically according to selected data bit width, deposits corresponding memory storage in and supplies hardware to call.
FFT arithmetic unit of the present invention support any 2
nThe FFT that (n is a natural number) counts calculates, and its technical scheme that adopts is following:
FFT arithmetic unit of the present invention mainly comprises: the outer data storage device of one or more block arithmetic units, piece, piece file memory controller and the piece address storage devices that interweaves outward.
In addition, FFT arithmetic unit of the present invention also can comprise the outer data path selector switch of twiddle factor memory storage and piece.
Block arithmetic unit is used for the independent calculating of N_local point FFT computing block, and (N_local is the number of data points that a block arithmetic unit once can read in and calculate, and is not more than 2
n).Always import under the definite situation of bit wide at block arithmetic unit, can import the data of difference " bit wide-number of data points " array configuration flexibly.
The outer data storage device of piece is connected with block arithmetic unit, is used to store the data of calculating through N_local point FFT.Depositing the data of the outer data storage device of this piece in, is the data that sequence by the proper data interleaved order, the completion subsequent operation of can directly peeking.
The piece file memory controller is connected with the outer data storage device of block arithmetic unit and piece respectively, is used for 1 N_local point of every completion FFT and calculates, and according to the outer data interlacing address of correct piece result of calculation is deposited into the outer data storage device of piece.Wherein the outer data interlacing address of the piece address storage devices that directly outside, interweaves reads in.
The piece address storage devices that interweaves outward is connected with the piece file memory controller, is used for according to the needed interleaving address of arithmetic unit execution order storage block file memory controller.The piece equal calculated in advance in address that interweaves outward is good and deposit the piece address storage devices that interweaves in outward, does not calculate at the scene during use, reads the address storage devices that directly outside this piece, interweaves.
The disclosed FFT arithmetic unit of the present invention, all pieces address that interweaves outward is all identical, this is not only less storage space, and reduced addressing circuit design complexities, increased the extent for multiplexing of hardware.
The present invention interweaves the position inverted sequence and general piece interweaves outward combines, and offers the piece file memory controller.Owing to except that last piece, interweave outside the difference of address, other any pieces address that interweaves outward is all identical, and the piece file memory controller only need read in two secondary data in the whole service process, significantly reduced the data accessing operation.
The twiddle factor memory storage is connected with block arithmetic unit, is used for storing block arithmetic unit according to the arithmetic unit execution order and carries out the needed twiddle factor of butterfly computation.The equal calculated in advance of twiddle factor is good and deposit the twiddle factor memory storage in, does not calculate at the scene during use, directly reads from memory storage.
The outer data path selector switch of piece is connected with the outer data storage device of piece, is used to the data of depositing in the outer data storage device of piece, selects different output whereabouts.
Block arithmetic unit mainly comprises: output data path selector switch in data storage device and the piece in butterfly computation device, piece stored controller, the piece.
The butterfly computation device is used to import multiplying each other of data point and twiddle factor and adds reducing.
Data storage device is connected with the butterfly computation device in the piece, is used to store the data through the one-level butterfly computation.Depositing the data of data storage device in this piece in, is the data that sequence by the proper data interleaved order, and the next stage butterfly computation can directly read in data according to this order.
Piece stored controller respectively with butterfly computation device and piece in data storage device be connected, be used for butterfly computation device result of calculation is deposited data storage device in the piece according to data interlacing address in the correct piece.Wherein in the piece data interlacing address directly in the piece interleaving address memory storage read in.
In addition, block arithmetic unit also can comprise input data path selector switch and the interior output data path selector switch of piece in the piece.
Input data path selector switch is connected with the butterfly computation device in the piece, is used to select to get into the Data Source of butterfly computation device.
The output data path selector switch is connected with the interior data storage device of piece in the piece, is used to the data of depositing in the data storage device in the piece, selects different output whereabouts.
Said interior output data path selector switch can be merged into a device with input data path selector switch in the piece, separately lists just for convenience of description at this.
FFT arithmetic unit of the present invention also can comprise interleaving address memory storage in the piece, and said interior interleaving address memory storage is connected with piece stored controller, is used for according to the needed interleaving address of arithmetic unit execution order storage block stored controller.The interior equal calculated in advance of interleaving address of piece is good and deposit interleaving address memory storage in the piece in, does not calculate at the scene during use, directly in this piece, reads the interleaving address memory storage.
The disclosed FFT arithmetic unit of the present invention, interleaving address is all identical in the piece of arbitrary number of level, this is not only less storage space, and reduced addressing circuit design complexities, increased the extent for multiplexing of hardware.In addition, because interleaving address is all identical in the piece of arbitrary number of level, piece stored controller only need read in a secondary data in the whole service process, significantly reduced the data accessing operation.
Below in conjunction with Figure of description a kind of embodiment of the present invention is elaborated.
As shown in Figure 1, FFT arithmetic unit of the present invention comprises: interweave outward address storage devices, the outer data storage device of piece and the outer data path selector switch of piece of interleaving address memory storage, piece file memory controller, piece in a plurality of block arithmetic units, twiddle factor memory storage, piece.
Said block arithmetic unit is mainly used in the independent calculating of carrying out small size FFT computing block.If N_local is the number of data points that a block arithmetic unit once can read in and calculate, N_bit is the bit wide of data point, and L_local is for calculating the required progression of N_local point FFT, then 2
nThe large scale FFT computing block that (n is a natural number) counts can be broken down into
(following explanation is all supposed
Greater than 1,
Equaling at 1 o'clock, also can release identical result) (N_local is not more than 2 to the individual N_local FFT computing block of ordering
n).
Shown in Fig. 2 example, 16 FFT can resolve into 48 FFT computing blocks.Always import under the definite situation of bit wide N_local*N_bit at block arithmetic unit, not only can import N_local N_bit bit data (not specified (NS) place in the following explanation is all by this form input), also can import following form data flexibly:
……
4N_local N_bit/4 bit data,
2N_local N_bit/2 bit data,
N_local/2 2N_bit bit data,
N_local/4 4N_bit bit data
……
As shown in Figure 1, block arithmetic unit comprises: output data path selector switch in input data path selector switch, butterfly computation device, piece stored controller, the interior data storage device of piece and the piece in the piece.
Input data path selector switch is used to select to get into the Data Source of butterfly computation device in the piece.When calculating preceding 2
nDuring the first order butterfly computation of/N_local N_local point FFT computing block, the data that get into the butterfly computation device directly from external memory read in (as Fig. 2 the 1st, the 1st grade of butterfly computation of 2FFT computing block); When calculating first order butterfly that other N_local points FFT calculates and calculate the 1st grade of butterfly computation of 4N_local point FFT computing block (in like Fig. 2 the 3rd), data data storage device outside piece of entering butterfly computation device reads in; When calculating other grades butterfly and calculate the 2nd, 3 grade of butterfly computation of 2N_local point FFT computing block (in like Fig. 2 the 1st), the data of entering butterfly computation device data storage device in the piece reads in.
The butterfly computation device is mainly used in the following operation of N_local data points:
Xo+W*Xe
Xo-W*Xe
Accomplish above computing, promptly accomplished the one-level butterfly computation.Wherein Xo is N_local/2 the vector that the input data point is formed that is positioned on the odd positions, and Xe is positioned at the vector that the locational N_local/2 of even number input data point formed, and W is corresponding twiddle factor vector.The data of forming Xo and Xe are all through input data path selector switch input in the piece.Forming the data of W imports from the twiddle factor memory storage.A block arithmetic unit once reads in the N_local data points, need carry out L_local level butterfly computation.When to carry out
individual to
when individual N_local point FFT calculates (in like Fig. 2 the 3rd, 4N_local point FFT computing block); Need carry out n mod L_local (, then needing the L_local level) level butterfly computation if n mod L_local is 0.Device among the present invention is an example with the butterfly computation of base 2, but practical application is not limited only to the situation of base 2.
The twiddle factor memory storage is used for storing successively the needed twiddle factor of butterfly computation.The equal calculated in advance of twiddle factor is good and deposit the twiddle factor memory storage in, does not calculate at the scene during use, directly reads from memory storage.The generation formula of twiddle factor is:
wherein i be the progression that is arranged in whole FFT computation process (down with).Can calculate the twiddle factor of any one-level through the twiddle factor computing formula.
Piece stored controller is used for the butterfly computation device is calculated the N_local data points of accomplishing, and deposits data storage device in the piece according to data interlacing address in the correct piece.Wherein in the piece data interlacing address directly in the piece interleaving address memory storage read in.
The interleaving address memory storage is used for the needed interleaving address of storage block stored controller successively in the piece.The interior equal calculated in advance of interleaving address of piece is good and deposit interleaving address memory storage in the piece in, does not calculate at the scene during use, directly reads from memory storage.The computing formula of interleaving address is the interior interlace mode example of piece of 8 spot sizes for
Fig. 3 in the piece.
The disclosed FFT arithmetic unit of the present invention, interleaving address is all identical in the piece of arbitrary number of level, this is not only less storage space (only needing N_local data of storage), and reduced addressing circuit design complexities, increased the extent for multiplexing of hardware.In addition, because interleaving address is all identical in the piece of arbitrary number of level, piece stored controller only need read in a secondary data in the whole service process, significantly reduced the data accessing operation.
When data point is read in the array configuration of counting according to different bit wides, as:
……
4N_local N_bit/4 bit data,
2N_local N_bit/2 bit data,
N_local/2 2N_bit bit data,
N_local/4 4N_bit bit data
……
This device all only needs to calculate
and deposit interleaving address memory storage in the piece in, can offer piece stored controller and be used for data addressing.
Data storage device is used to store the data through the one-level butterfly computation in the piece.Depositing the data of this memory storage in, is the data that sequence by the proper data interleaved order, and the next stage butterfly computation can directly read in data according to this order.
The output data path selector switch is mainly the data of depositing in the data storage device in the piece in the piece, selects different output whereabouts.When having calculated
individual n mod L_local (if n mod L_local is 0 to
individual N_local point FFT computing block; Then be the L_local level) level is during butterfly computation (as among Fig. 2 the 3rd, the 1st grade of butterfly computation of 4N_local point FFT computing block), data directly deposit piece data storage device outward in; When having calculated the L_local level butterfly computation of other small sizes FFT, data deposit in the outer data storage device of piece (as among Fig. 2 the 1st, the 3rd level butterfly computation of 2N_local point FFT computing block); When having calculated other situation butterfly computations, data read in by the butterfly computation device (as among Fig. 2 the 1st, the 1st, 2 grade of butterfly computation of 2N_local point FFT computing block).This device can be merged into a device with input data path selector switch in the piece, separately lists just for convenience of description at this.
When the piece file memory controller is used for 1 N_local point FFT calculating of every calculating completion, result of calculation is deposited into the outer data storage device of piece according to the outer data interlacing address of correct piece.Wherein the outer data interlacing address of the piece address storage devices that directly outside piece, interweaves reads in.
The piece address storage devices that interweaves outward is used for the needed interleaving address of storage block file memory controller successively.The piece equal calculated in advance in address that interweaves outward is good and deposit the piece address storage devices that interweaves in outward, does not calculate at the scene during use, and the address storage devices that directly outside piece, interweaves is read.Interweave the outward computing formula of address of piece is piece that 64 FFT computing blocks are broken down into 8 the FFT computing blocks pattern example that interweaves outward for
Fig. 4.
The disclosed FFT arithmetic unit of the present invention, the piece of the arbitrary number of level address that interweaves outward is all identical, this is not only less storage space, and reduced addressing circuit design complexities, increased the extent for multiplexing of hardware.
When data point is read in the array configuration of counting according to different bit wides, as:
……
4N_local N_bit/4 bit data,
2N_local N_bit/2 bit data,
N_local/2 2N_bit bit data,
N_local/4 4N_bit bit data
……
This device all only needs to calculate
and deposit the piece address storage devices that interweaves in outward, can offer the piece file memory controller and be used for data addressing.
Calculating last
individual during (in the 3rd, 4N_local point FFT computing block) like Fig. 2 to
individual N_local point FFT computing block; Piece interweave outward the computing formula of address for
this position inverted sequence is interweaved with general piece outside interweave and combine, offer the piece file memory controller.Owing to except that last piece, interweave outside the difference of address, other any pieces address that interweaves outward is all identical, and the piece file memory controller only need read in two secondary data in the whole service process, significantly reduced the data accessing operation.
When data point is read in the array configuration of counting according to different bit wides, as:
……
4N_local N_bit/4 bit data,
2N_local N_bit/2 bit data,
N_local/2 2N_bit bit data,
N_local/4 4N_bit bit data
……
This device all only needs to calculate:
……，
……
And deposit the piece address storage devices that interweaves in outward, can offer the piece file memory controller and be used for data addressing.
The outer data storage device of piece is used to store the data of calculating through N_local point FFT.Every calculating accomplishes 2
N-L_localIndividual N_local point FFT calculates, and has deposited complete 2 in this memory storage in
nThe individual data that sequenced by the correct data interleaved order.Carry out next 2
N-L_localWhen individual N_local point FFT calculates, can directly data be read in according to this order.
The outer data path selector switch of piece is mainly the data of depositing in the outer data storage device of piece, selects different output whereabouts.When to have calculated
individual to
when individual N_local point FFT calculates the 1st grade of butterfly computation of 4N_local point FFT computing block (in like Fig. 2 the 3rd), data directly deposit external memory in; When the N_local point FFT that has calculated other situation calculates (in like Fig. 2 the 1st, 2N_local point FFT computing block), data are read in by block arithmetic unit.The invention provides a kind of variable-sized block FFT arithmetic unit of single inside and outside pilotaxitic texture, the thought that this device uses piecemeal to handle is decomposed into a plurality of independently small size FFT computing blocks with large scale FFT computing.The data interlacing scope of small size FFT computing block is little and interleaving mode is consistent, has reduced structure complexity and has read power consumption, has improved the access speed and calculating closure of data.Piecemeal is handled the back only needs less global data to interweave, and the mode that all global datas interweave is consistent.After the piece fixed size, this device can be handled the data of different bit wides flexibly.
FFT arithmetic unit among the present invention has carried out block decomposition too to be disperseed to avoid addressing space, and the calculating of can once peeking simultaneously is multistage, reduces the access data number of times.Its advance is embodied in:
The data bit width that can select according to the user generates corresponding block of decomposition pattern automatically.If hardware configuration uses fixing block size, when the user changes bit wide, only need to generate corresponding twiddle factor, inside and outside interleaving address, other structures do not need to change;
Data interlacing pattern in each piece is identical, and the data interlacing pattern outside all pieces is identical.Adopt the variable-sized block fft algorithm of single inside and outside pilotaxitic texture, not only retrained the discretize degree of data address, reduced communication-cost, and increased the closure of data, make algorithm be easier to parallelization.
Support any 2
nThe FFT computing of counting has greatly improved the dirigibility of hardware designs, need not change hardware structure for the FFT computing that difference is counted.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a FFT arithmetic unit is used to accomplish 2
nPoint FFT calculates, and n is a natural number, it is characterized in that, comprising:
One or more block arithmetic units are respectively applied for the independent of N_local point FFT computing block and calculate, and wherein this N_local is the number of data points that a block arithmetic unit once can read in and calculate, and is not more than 2
n
The outer data storage device of piece is connected with said block arithmetic unit, is used to store the data of calculating through N_local point FFT;
The piece file memory controller is connected with the outer data storage device of said block arithmetic unit and piece respectively, is used for 1 N_local point of every completion FFT and calculates, and according to the outer data interlacing address of correct piece result of calculation is deposited into said outer data storage device;
The piece address storage devices that interweaves outward is connected with said file memory controller, is used for the needed interleaving address of storage block file memory controller.
2. FFT arithmetic unit as claimed in claim 1 is characterized in that, all pieces address that interweaves outward is all identical.
3. FFT arithmetic unit as claimed in claim 1 is characterized in that, said FFT arithmetic unit also comprises:
The twiddle factor memory storage is connected with said block memory storage, is used to store said block arithmetic unit and carries out the needed twiddle factor of butterfly computation.
4. FFT arithmetic unit as claimed in claim 1 is characterized in that, said FFT arithmetic unit also comprises:
The outer data path selector switch of piece is connected with said outer data storage device, is used to the data of depositing in the said outer data storage device and selects different output whereabouts.
5. FFT arithmetic unit as claimed in claim 1 is characterized in that,
Said block arithmetic unit comprises:
The butterfly computation device is used to import multiplying each other and adding reducing of data point and twiddle factor;
Data storage device in the piece is connected with said butterfly computation device, is used to store the data through the one-level butterfly computation;
Piece stored controller, respectively with said butterfly computation device and piece in data storage device be connected, be used for the result of calculation of said butterfly computation device is deposited into said interior data storage device according to data interlacing address in the correct piece;
6. FFT arithmetic unit as claimed in claim 5 is characterized in that, said block arithmetic unit also comprises:
Input data path selector switch is connected with said butterfly computation device in the piece, is used to select to get into the Data Source of said butterfly computation device.
7. FFT arithmetic unit as claimed in claim 5 is characterized in that, said block arithmetic unit also comprises:
Output data path selector switch in the piece is connected with said interior data storage device, is used to the data of depositing in the said interior data storage device and selects different output whereabouts.
8. FFT arithmetic unit as claimed in claim 5 is characterized in that, said FFT arithmetic unit also comprises:
Interleaving address memory storage in the piece is connected with said stored controller, is used to store the said needed interleaving address of stored controller.
9. FFT arithmetic unit as claimed in claim 8 is characterized in that, interleaving address is all identical in all pieces.
10. FFT arithmetic unit as claimed in claim 8; It is characterized in that; Said FFT arithmetic unit uses the input data of different bit wides; And, only, can be configured said FFT arithmetic unit through changing the value that said interior interleaving address memory storage, piece interweave and store in address storage devices and the twiddle factor memory storage outward.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050114421A1 (en) * | 2003-11-26 | 2005-05-26 | Gibb Sean G. | Interleaving memory |
| WO2005052798A1 (en) * | 2003-11-26 | 2005-06-09 | Cygnus Communications Canada Co. | Interleaving memory |
| CN101504637A (en) * | 2009-03-19 | 2009-08-12 | 北京理工大学 | Point-variable real-time FFT processing chip |
| CN102033852A (en) * | 2009-09-30 | 2011-04-27 | 中兴通讯股份有限公司 | Device and method for implementing FFT and IFFT operation |
-
2011
- 2011-12-22 CN CN201110436062.3A patent/CN102609395B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050114421A1 (en) * | 2003-11-26 | 2005-05-26 | Gibb Sean G. | Interleaving memory |
| WO2005052798A1 (en) * | 2003-11-26 | 2005-06-09 | Cygnus Communications Canada Co. | Interleaving memory |
| CN101504637A (en) * | 2009-03-19 | 2009-08-12 | 北京理工大学 | Point-variable real-time FFT processing chip |
| CN102033852A (en) * | 2009-09-30 | 2011-04-27 | 中兴通讯股份有限公司 | Device and method for implementing FFT and IFFT operation |
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