CN102609218B - Method for implementing parallel-flash translation layer and parallel-flash translation layer system - Google Patents
Method for implementing parallel-flash translation layer and parallel-flash translation layer system Download PDFInfo
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Abstract
The invention discloses a parallel-flash layer translating method, which comprises the following steps: establishing a mixed address mapping mechanism which makes a page group and a block as an unit, wherein the page group can be divided into a logic page group and a physical page group, the block can be divided into a logic block and a physical block; when the quantity of I/O requests sent by a file system is larger than a predetermined request threshold value, establishing an I/O request queue and putting the I/O requests which are beyond the predetermined request threshold value in the I/O request queue; dividing the I/O requests of the I/O request queue into a plurality of groups of I/O request sub-queues according to the mixed address mapping mechanism; and carrying out parallel reading-writing operation to each group of I/O request sub-queues, wherein each group of the I/O request sub-queues comprise a plurality of I/O requests and the plurality of I/O requests can operate parallelly. The method utilizes excellent parallel-flash feature completely through the parallel reading-writing operation; writing-in and erasing time is reduced; thus, complexity is reduced; and high performance is obtained. The invention also discloses a parallel-flash translation layer system.
Description
Technical field
The present invention relates to computer memory technical field, particularly a kind of parallel-flash translation layer method and system.
Background technology
At present, nand flash memory is widely used in mobile electronic product, as mobile phone, MP3/MP4 player, digital camera, palm PC, panel computer, notebook computer etc.Usual flash memory for replacing disc driver, as non-volatile secondary storage media.Compared with disk, flash memory allows random access, has that energy consumption is low, handling capacity is high, volume is little, an advantage such as shock resistance and portability.The main cause that mobile electronic device manufacturer and user more and more pay attention to flash memory is, the capacity of nand flash memory constantly increases, but its price constantly declines.But, nand flash memory write and time of erase operation consumption longer be the main performance bottleneck of storage system.
Flash translation layer (FTL) (FTL, Flash Translation Layer) is a middle layer of file system and lower floor's flash memory, for file system provides one with the same operation-interface of disk.Use flash translation layer (FTL) the erase operation of flash memory can be delayed, application program is normally run fast.In general, flash translation layer (FTL) can not reduce the write operation of file system to flash memory, because its core is to provide the mapping of logical address to physical address.
Flash translation layer (FTL) can be divided three classes: page maps, block maps and mixed-use developments flash translation layer (FTL).Page is the primitive of read-write flash memory.Block is the primitive of Flash memory erase operations.Page maps flash translation layer (FTL) good performance, but needs more internal memory to carry out memory address map information.Block maps flash translation layer (FTL) and can save a large amount of for storing the memory headroom of map information, but their Performance comparision is low.Mixed-use developments flash translation layer (FTL) provides the balance of high-performance and low request memory, however usually too complicated, be not easy to realize.
Conventional flash memory conversion layer seldom considers the parallel work-flow attribute that flash memory provides, and the time of nand flash memory write and erase operation consumption constrains the flash memory storage performance of electronic product.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency.
For this reason, first object of the present invention is to provide a kind of parallel-flash translation layer method, and the method, by concurrent reading and concurrent writing, makes full use of the good characteristic of paralleling flash memory, reduces write and erase time, thus reduces complexity, obtains high-performance.Second object of the present invention is to provide a kind of parallel-flash translation layer system.
For achieving the above object, the embodiment of first aspect present invention proposes a kind of parallel-flash translation layer method, comprises the steps: to set up the combined address mapping mechanism that page group and block are unit, wherein, page group can be divided into logical page (LPAGE) group and Physical Page group, and block can be divided into logical block and physical block; When the quantity of the I/O request that file system sends exceedes default request threshold value, set up I/O request queue, and described I/O request queue is put in the I/O request exceeding described default request threshold value; Many group I/O are divided into ask subqueue according to described combined address mapping mechanism to the I/O request in described I/O request queue, the operation of subqueue concurrent reading and concurrent writing is asked to the described I/O that often organizes, wherein, often organize described I/O and ask subqueue to comprise multiple I/O and ask, described multiple I/O asks can parallel work-flow.
According to parallel-flash translation layer method of the present invention, abundant excavation also utilizes the parallel property of paralleling flash memory, can automatically by can parallel work-flow process on paralleling flash memory simultaneously, the time of process data input and output and storage system garbage reclamation is reduced with this, and the memory headroom reduced for storing map information, thus reduction complexity, promote the efficiency of storage system, obtain high-performance.
In one embodiment of the invention, described foundation page group and block are the combined address mapping mechanism of unit, comprise further: paralleling flash memory is divided into multiple physical block, and each described physical block is divided into multiple Physical Page group;
Logical block data is divided into multiple logical page (LPAGE) group;
Described Physical Page component is assigned to described logical page (LPAGE) group by the physical block of described paralleling flash memory;
When described logical page (LPAGE) group upgrades, again the described Physical Page component on the described physical block of correspondence is assigned to described logical page (LPAGE) group.
In one embodiment of the invention, if after the data after the renewal of described logical block exceed the memory capacity of the described object page group of corresponding described physical block, distribute new physical block to described logical block.
In one embodiment of the invention, arrange indications to the multiple described Physical Page group of same described logical page (LPAGE) group, wherein, it is valid data or invalid data that described indications is used to indicate described Physical Page group.
In one embodiment of the invention, it is characterized in that, the size arranging each described page group is 2-4 kilobyte, and the size of each described piece is 128-256 kilobyte.
In one embodiment of the invention, described described often group on store electricity daughter board that I/O asks the I/O in subqueue to ask concurrent reading and concurrent writing to operate in can to walk abreast to be performed.
In one embodiment of the invention, the described store electricity daughter board size walked abreast is 256 or 512 megabyte.
In one embodiment of the invention, described parallel-flash translation layer method also comprises the steps:
According to the indications of described Physical Page group, reclaim and be labeled as the maximum data block of invalid data, set up and reclaim set of blocks;
Searching from described recovery set of blocks can the physical block of parallel erase, and the physical block of parallel erase can carry out parallel erase operations to described.
In one embodiment of the invention, parallel-flash translation layer method also comprises the steps:
Arrange list of free blocks, wherein, described list of free blocks stores the physical block after erasing;
From described list of free blocks, choose idle physical block distribute to described logical block.
The embodiment of second aspect present invention proposes a kind of parallel-flash translation layer system, comprise: set up module, described mixed module of setting up for setting up the combined address mapping mechanism that page group and block are unit, wherein, page group can be divided into logical page (LPAGE) group and Physical Page group, and block can be divided into logical block and physical block; Request processing module, described request processing module is used for, when the quantity of the I/O request that file system sends exceedes default request threshold value, setting up I/O request queue, and described I/O request queue being put in the I/O request exceeding described default request threshold value; Parallel work-flow module, described parallel work-flow module is used for being divided into many group I/O to ask subqueue according to described combined address mapping mechanism to the I/O request in described I/O request queue, the operation of subqueue concurrent reading and concurrent writing is asked to the described I/O that often organizes, wherein, often organizing described I/O asks subqueue to comprise multiple I/O and ask, and described multiple I/O asks can parallel work-flow.
According to parallel-flash translation layer system of the present invention, abundant excavation also utilizes the parallel property of paralleling flash memory, can automatically by can parallel work-flow process on paralleling flash memory simultaneously, the time of process data input and output and storage system garbage reclamation is reduced with this, and the memory headroom reduced for storing map information, thus reduction complexity, promote the efficiency of storage system, obtain high-performance.
In one embodiment of the invention, described module of setting up sets up the combined address mapping mechanism that page group and block are unit, comprise further: paralleling flash memory is divided into multiple physical block by described module of setting up, and each described physical block is divided into multiple Physical Page group, and logical block data is divided into multiple logical page (LPAGE) group, described Physical Page component is assigned to described logical page (LPAGE) group by the physical block of described paralleling flash memory, and when described logical page (LPAGE) group upgrades, again the described Physical Page component on the described physical block of correspondence is assigned to described logical page (LPAGE) group.
In one embodiment of the invention, if after the data after the renewal of described logical block exceed the memory capacity of the described object page group of corresponding described physical block, then described module of setting up distributes new physical block to described logical block.
In one embodiment of the invention, the described multiple described Physical Page group of module to same described logical page (LPAGE) group of setting up arranges indications, and wherein, it is valid data or invalid data that described indications is used to indicate described Physical Page group.
In one embodiment of the invention, the described size setting up each described page group of module installation is 2-4 kilobyte, and the size of each described piece is 128-256 kilobyte.
In one embodiment of the invention, described request processing module performs described often group on store electricity daughter board that I/O asks the I/O in subqueue to ask concurrent reading and concurrent writing to operate in can to walk abreast.
In one embodiment of the invention, the described store electricity daughter board size walked abreast is 256 or 512 megabyte.
In one embodiment of the invention, also comprise as lower module:
Recycling module, described recycling module has the data block of maximum invalid data for reclaiming, set up and reclaim set of blocks;
Erasing module, described erasing module is used for searching from described recovery set of blocks can the physical block of parallel erase, the physical block of parallel erase can carry out erase operation simultaneously.
In one embodiment of the invention, also comprise as lower module:
Free list module, described free list module is used for the physical block after by erasing and puts in the list of free blocks of system, when system needs to distribute new described physical block to described logical block time, from described list of free blocks, idle physical block is selected to distribute.
The aspect that the present invention adds and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 is the FB(flow block) of the parallel-flash translation layer method according to the embodiment of the present invention;
Fig. 2 is the processing flow chart of the parallel-flash translation layer method and system according to the embodiment of the present invention;
Fig. 3 is the expansion FB(flow block) of the parallel-flash translation layer method according to the embodiment of the present invention; And
Fig. 4 is the structural representation of the parallel-flash translation layer system according to the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
With reference to description below and accompanying drawing, these and other aspects of embodiments of the invention will be known.Describe at these and in accompanying drawing, specifically disclose some particular implementation in embodiments of the invention, representing some modes of the principle implementing embodiments of the invention, but should be appreciated that the scope of embodiments of the invention is not limited.On the contrary, embodiments of the invention comprise fall into attached claims spirit and intension within the scope of all changes, amendment and equivalent.
Below with reference to Fig. 1 and Fig. 2, the parallel-flash translation layer method according to the embodiment of the present invention is described.
Step S110: set up the combined address mapping mechanism that page group and block are unit, wherein, page group can be divided into logical page (LPAGE) group and Physical Page group, and block can be divided into logical block and physical block.In one embodiment of the invention, the size arranging each page of group is 2 ~ 4 kilobyte, and the size of each piece is 128 ~ 256 kilobyte.Be understandable that, only for exemplary purposes, the embodiment of the present invention is not limited to this to the size of above-mentioned page group and block.
Be that the process of the combined address mapping mechanism of unit is described in detail to setting up page group and block below.
Step S111: paralleling flash memory is divided into multiple physical block, and each physical block is divided into multiple Physical Page group.
Paralleling flash memory as shown in Figure 2 can be divided into four physical blocks, and numbering is respectively 1,2,3,4.Be understandable that, the division shown in Fig. 2 is only one embodiment of the present of invention, and embodiments of the invention are not limited to this.
Each physical block is divided into multiple Physical Page group, such as, physical block 1 is divided into n Physical Page group, physical block 2 ~ 4 can the like, do not repeat them here.
Step S112: logical block data is divided into multiple logical page (LPAGE) group;
Step S113: on the physical block of paralleling flash memory, Physical Page component is assigned to logical page (LPAGE) group;
The logical page (LPAGE) group obtained in step S112 is assigned to by dividing the Physical Page component obtained in step S111.
Step S114: when logical page (LPAGE) group upgrades, again the Physical Page component on the physical block of correspondence is assigned to logical page (LPAGE) group.
The memory capacity of each physical block is limited.After there is repeatedly renewal in the logical page (LPAGE) in logical block, if the data after upgrading exceed the memory capacity of the object page group of corresponding physical block, the physical block that this logical block originally distributed cannot store the data of this logical block, then need to distribute new physical block to this logical block.
Because the data in Physical Page group comprise invalid data and valid data, in order to distinguish above-mentioned data, need to arrange indications to multiple Physical Page groups of same logical page (LPAGE) group, wherein, it is valid data or invalid data that indications is used to indicate Physical Page group.Such as, being 0 by the Physical Page group echo depositing invalid data, is 1 by the Physical Page group echo depositing valid data.Be understandable that, the indications 0 and 1 of above-mentioned setting is only that the embodiment of the present invention is not limited to this for exemplary purposes.
S120: set up I/O request queue, puts into I/O request queue by exceeding the I/O request presetting request threshold value.
As shown in Figure 2, file system is by input, output interface transmission data.When the quantity of the I/O request that file system sends exceedes default request threshold value, set up I/O request queue, and put into I/O request queue by exceeding the I/O request presetting request threshold value.It should be noted that, when the data of the I/O request that file system sends exceed default request threshold value, can think that the I/O request of current system is for high density state.
In one embodiment of the invention, preset request threshold value to be arranged according to system state by system manager.
S130: be divided into many group I/O to ask subqueue the I/O request in I/O request queue according to combined address mapping mechanism.Start from first I/O request of request queue, find and can the I/O of parallel work-flow ask, be divided into same group.Ask the operation of subqueue concurrent reading and concurrent writing to often organizing I/O, the request processed is removed from I/O request queue.Wherein, often organize I/O and ask subqueue to comprise multiple I/O and ask, multiple I/O asks can parallel work-flow.
By the way, can in advance to can the I/O request of executed in parallel divide into groups, to can the I/O request of parallel work-flow process, thus the operating efficiency of flash memory can be improved, and then improve the speed of whole system process data.
In one embodiment of the invention, perform often organizing on store electricity daughter board that I/O asks subqueue concurrent reading and concurrent writing to operate in can to walk abreast, the store electricity daughter board size that can walk abreast is 256 or 512 megabyte.
As shown in Figure 2, parallel-flash translation layer also needs to carry out parallel garbage reclamation control to paralleling flash memory.Because be assigned with along with physical block and use, need to reclaim it and clear up, erasing is marked as the invalid data block of 0 to recycle.Be described in detail below in conjunction with Fig. 3.
Step S140: reclaim the data block with maximum invalid data, sets up and reclaims set.
This step can be divided into following two steps further:
Step S141: according to the indications of Physical Page group, i.e. valid data identifier 1 or invalid data identifier 0, reclaim and be labeled as the maximum data block of invalid data (data identifier is 0), sets up and reclaim set of blocks;
Step S142: search can the physical block of parallel erase from reclaiming set of blocks, and to the physical block of parallel erase carrying out parallel erase operations.
Step S150: list of free blocks is set, wherein, list of free blocks stores the physical block after erasing; From list of free blocks, choose idle physical block distribute to logical block.
The parallel property of paralleling flash memory is fully excavated, utilized to parallel-flash translation layer method according to the present invention, can automatically by can parallel work-flow process on paralleling flash memory simultaneously, the time of process data input and output and storage system garbage reclamation is reduced with this, and the memory headroom reduced for storing map information, thus reduction complexity, promote the efficiency of storage system, obtain high-performance.
As shown in Figure 3, embodiments provide a kind of parallel-flash translation layer system, comprise and set up module 100: combined address mapping mechanism sets up module for setting up the combined address mapping mechanism that page group and block are unit, wherein, page group can be divided into logical page (LPAGE) group and Physical Page group, and block can be divided into logical block and physical block; Request processing module 110: when request processing module 110 presets request threshold value for exceeding when the quantity of the I/O request that file system sends, set up I/O request queue, and put into I/O request queue by exceeding the I/O request presetting request threshold value; Parallel work-flow module 120: parallel work-flow module is used for being divided into many group I/O to ask subqueue according to combined address mapping mechanism to the I/O request in I/O request queue, the operation of subqueue concurrent reading and concurrent writing is asked to many group I/O, wherein, often organizing I/O asks subqueue to comprise multiple I/O and ask, and multiple I/O asks can parallel work-flow.
Set up module 100 for setting up the combined address mapping mechanism that page group and block are unit, further function comprises: set up module 100 and paralleling flash memory is divided into multiple physical block, and each physical block is divided into multiple Physical Page group.Paralleling flash memory as shown in Figure 2 can be divided into four physical blocks, and numbering is respectively 1,2,3,4.Be understandable that, the division shown in Fig. 2 is only one embodiment of the present of invention, and embodiments of the invention are not limited to this.Set up module 100 and each physical block be divided into multiple Physical Page group, such as, physical block 1 is divided into n Physical Page group, physical block 2 ~ 4 can the like, do not repeat them here.Set up module 100 and logical block data is divided into multiple logical page (LPAGE) group; Physical Page component is assigned to logical page (LPAGE) group by the physical block of paralleling flash memory; When logical page (LPAGE) group upgrades, set up module 100 and again the Physical Page component on the physical block of correspondence is assigned to logical page (LPAGE) group.The memory capacity of each physical block is limited.After there is repeatedly renewal in the logical page (LPAGE) in logical block, if the data after upgrading exceed the memory capacity of the object page group of corresponding physical block, the physical block that this logical block originally distributed cannot store the data of this logical block, then set up module 100 and distribute new physical block to this logical block.
Setting up the size that module 100 arranges each page of group is 2 ~ 4 kilobyte, and the size of each piece is 128 ~ 256 kilobyte.Be understandable that, only for exemplary purposes, the embodiment of the present invention is not limited to this to the size of above-mentioned page group and block.
Because the data in Physical Page group comprise invalid data and valid data, in order to distinguish above-mentioned data, set up module 100 to need to arrange indications to multiple Physical Page groups of same logical page (LPAGE) group, wherein, it is valid data or invalid data that indications is used to indicate Physical Page group.Such as, setting up module 100 by the Physical Page group echo depositing invalid data is 0, is 1 by the Physical Page group echo depositing valid data.Be understandable that, the indications 0 and 1 of above-mentioned setting is only that the embodiment of the present invention is not limited to this for exemplary purposes.
When request processing module 110 presets request threshold value for exceeding when the quantity of the I/O request that file system sends, set up I/O request queue, and put into I/O request queue by exceeding the I/O request presetting request threshold value.It should be noted that, when the data of the request of data that file system sends exceed default request threshold value, can think that the I/O request of current system is for high density state.In one embodiment of the invention, the default request threshold value in request processing module 110 can be arranged according to system state by system manager.
I/O request in I/O request queue is divided into many group I/O to ask subqueue according to combined address mapping mechanism by parallel work-flow module 120.Parallel work-flow module 120 starts from first I/O request of request queue, finds and can the I/O of parallel work-flow ask, be divided into same group.Parallel work-flow module 120 asks the operation of subqueue concurrent reading and concurrent writing to often organizing I/O, the request processed is removed from I/O request queue.Wherein, often organize I/O and ask subqueue to comprise multiple I/O and ask, multiple I/O asks can parallel work-flow.By the way, parallel work-flow module 120 can in advance to can the I/O request of executed in parallel divide into groups, and to can the I/O request of parallel work-flow process, thus can improve the operating efficiency of flash memory, and then improve the speed of whole system process data.
In one embodiment of the invention, parallel work-flow module 120 performs often organizing on store electricity daughter board that I/O asks subqueue concurrent reading and concurrent writing to operate in can to walk abreast, and the store electricity daughter board size that can walk abreast is 256 or 512 megabyte.
Complete with upper module and operate the concurrent reading and concurrent writing of paralleling flash memory, along with physical block is marked as the increasing number of invalid data, system needs to reclaim the physical block in paralleling flash memory and clear up.System adopts module 130-150 to complete this function.
Recycling module 130: for reclaiming the data block with maximum invalid data, sets up and reclaims set of blocks.Recycling module 130 according to the indications of Physical Page group, i.e. valid data identifier 1 or invalid data identifier 0, recycling module 130 reclaim be labeled as the maximum data block of invalid data (data identifier is 0), set up reclaim set of blocks;
Erasing module 140: for search can the physical block of parallel erase from reclaiming in set of blocks, the physical block of parallel erase can carry out erase operation simultaneously.
Free list module 150: for putting in the list of free blocks of system by the physical block after erasing, when system needs to distribute new physical block to logical block time, free list module 150 selects idle physical block to distribute from list of free blocks.
The parallel property of paralleling flash memory is fully excavated, utilized to parallel-flash translation layer system according to the present invention, can automatically by can parallel work-flow process on paralleling flash memory simultaneously, the time of process data input and output and storage system garbage reclamation is reduced with this, and the memory headroom reduced for storing map information, thus reduction complexity, promote the efficiency of storage system, obtain high-performance.
Describe and can be understood in process flow diagram or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiments of the invention person of ordinary skill in the field.
In flow charts represent or in this logic otherwise described and/or step, such as, the sequencing list of the executable instruction for realizing logic function can be considered to, may be embodied in any computer-readable medium, for instruction execution system, device or equipment (as computer based system, comprise the system of processor or other can from instruction execution system, device or equipment instruction fetch and perform the system of instruction) use, or to use in conjunction with these instruction execution systems, device or equipment.With regard to this instructions, " computer-readable medium " can be anyly can to comprise, store, communicate, propagate or transmission procedure for instruction execution system, device or equipment or the device that uses in conjunction with these instruction execution systems, device or equipment.The example more specifically (non-exhaustive list) of computer-readable medium comprises following: the electrical connection section (electronic installation) with one or more wiring, portable computer diskette box (magnetic device), random access memory (RAM), ROM (read-only memory) (ROM), erasablely edit ROM (read-only memory) (EPROM or flash memory), fiber device, and portable optic disk ROM (read-only memory) (CDROM).In addition, computer-readable medium can be even paper or other suitable media that can print described program thereon, because can such as by carrying out optical scanning to paper or other media, then carry out editing, decipher or carry out process with other suitable methods if desired and electronically obtain described program, be then stored in computer memory.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple step or method can with to store in memory and the software performed by suitable instruction execution system or firmware realize.Such as, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: the discrete logic with the logic gates for realizing logic function to data-signal, there is the special IC of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, this program perform time, step comprising embodiment of the method one or a combination set of.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, also can be that the independent physics of unit exists, also can be integrated in a module by two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.If described integrated module using the form of software function module realize and as independently production marketing or use time, also can be stored in a computer read/write memory medium.
The above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and describe embodiments of the invention, for the ordinary skill in the art, be appreciated that and can carry out multiple change, amendment, replacement and modification to these embodiments without departing from the principles and spirit of the present invention, scope of the present invention is by claims and equivalency thereof.
Claims (14)
1. a parallel-flash translation layer method, is characterized in that, comprising:
Set up the combined address mapping mechanism that page group and block are unit, wherein, described page group can be divided into logical page (LPAGE) group and Physical Page group, described piece can be divided into logical block and physical block, indications is arranged to the multiple described Physical Page group of same described logical page (LPAGE) group, according to the indications of described Physical Page group, reclaim and be labeled as the maximum data block of invalid data, set up and reclaim set of blocks, searching from described recovery set of blocks can the physical block of parallel erase again, and the physical block of parallel erase can carry out parallel erase operations to described, it is valid data or invalid data that wherein said indications is used to indicate described Physical Page group,
When the quantity of the I/O request that file system sends exceedes default request threshold value, set up I/O request queue, and described I/O request queue is put in the I/O request exceeding described default request threshold value;
Many group I/O are divided into ask subqueue according to described combined address mapping mechanism to the I/O request in described I/O request queue, the operation of subqueue concurrent reading and concurrent writing is asked to the described I/O that often organizes, wherein, often organize described I/O and ask subqueue to comprise multiple I/O and ask, described multiple I/O asks can parallel work-flow.
2. parallel-flash translation layer method as claimed in claim 1, it is characterized in that, described foundation page group and block are the combined address mapping mechanism of unit, comprise further:
Paralleling flash memory is divided into multiple physical block, and each described physical block is divided into multiple Physical Page group;
Logical block data is divided into multiple logical page (LPAGE) group;
Described Physical Page component is assigned to described logical page (LPAGE) group by the physical block of described paralleling flash memory;
When described logical page (LPAGE) group upgrades, again the described Physical Page component on the described physical block of correspondence is assigned to described logical page (LPAGE) group.
3. parallel-flash translation layer method as claimed in claim 2, is characterized in that, if after the data after the renewal of described logical block exceed the memory capacity of the described Physical Page group of corresponding described physical block, distribute new physical block to described logical block.
4. the parallel-flash translation layer method according to any one of claim 2-3, is characterized in that, the size arranging each described page group is 2 ~ 4 kilobyte, and the size of each described piece is 128 ~ 256 kilobyte.
5. parallel-flash translation layer method as claimed in claim 1, is characterized in that, describedly performs described often group on store electricity daughter board that I/O asks the I/O in subqueue to ask concurrent reading and concurrent writing to operate in can to walk abreast.
6. parallel-flash translation layer method as claimed in claim 5, it is characterized in that, the described store electricity daughter board size walked abreast is 256 or 512 megabyte.
7. parallel-flash translation layer method as claimed in claim 1, is characterized in that, also comprise the steps:
Arrange list of free blocks, wherein, described list of free blocks stores the physical block after erasing;
From described list of free blocks, choose idle physical block distribute to described logical block.
8. a parallel-flash translation layer system, is characterized in that, comprising:
Set up module, described module of setting up is for setting up the combined address mapping mechanism that page group and block are unit, the described multiple Physical Page groups of module to same logical page (LPAGE) group of setting up arrange indications, wherein, it is valid data or invalid data that described indications is used to indicate described Physical Page group, wherein, described page group can be divided into logical page (LPAGE) group and Physical Page group, and described piece can be divided into logical block and physical block;
Recycling module, described recycling module has the data block of maximum invalid data for reclaiming, set up and reclaim set of blocks;
Erasing module, described erasing module is used for searching from described recovery set of blocks can the physical block of parallel erase, the physical block of parallel erase can carry out erase operation simultaneously;
Request processing module, described request processing module is used for, when the quantity of the I/O request that file system sends exceedes default request threshold value, setting up I/O request queue, and described I/O request queue being put in the I/O request exceeding described default request threshold value;
Parallel work-flow module, described parallel work-flow module is used for being divided into many group I/O to ask subqueue according to described combined address mapping mechanism to the I/O request in described I/O request queue, the operation of subqueue concurrent reading and concurrent writing is asked to the described I/O that often organizes, wherein, often organizing described I/O asks subqueue to comprise multiple I/O and ask, and described multiple I/O asks can parallel work-flow.
9. parallel-flash translation layer system as claimed in claim 8, it is characterized in that, paralleling flash memory is divided into multiple physical block by described module of setting up, and each described physical block is divided into multiple Physical Page group, and logical block data is divided into multiple logical page (LPAGE) group, described Physical Page component is assigned to described logical page (LPAGE) group by the physical block of described paralleling flash memory, and when described logical page (LPAGE) group upgrades, the described Physical Page component on the described physical block of correspondence is assigned to described logical page (LPAGE) group by described module of setting up again.
10. parallel-flash translation layer system as claimed in claim 8, it is characterized in that, if after the data after described logical block upgrades exceed the memory capacity of the described Physical Page group of corresponding described physical block, then described module of setting up distributes new physical block to described logical block.
11. parallel-flash translation layer system according to any one of claim 9-10, it is characterized in that, the described size setting up each described page group of module installation is 2 ~ 4 kilobyte, and the size of each described piece is 128 ~ 256 kilobyte.
12. parallel-flash translation layer system as claimed in claim 8, is characterized in that, describedly perform described often group on store electricity daughter board that I/O asks the I/O in subqueue to ask concurrent reading and concurrent writing to operate in can to walk abreast.
13. parallel-flash translation layer system as claimed in claim 12, is characterized in that, the described store electricity daughter board size walked abreast is 256 or 512 megabyte.
14. parallel-flash translation layer system as claimed in claim 11, is characterized in that, also comprise as lower module:
Free list module, described free list module is used for the physical block after by erasing and puts in the list of free blocks of system, when system needs to distribute new described physical block to described logical block time, from described list of free blocks, idle physical block is selected to distribute.
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| CN107391392A (en) * | 2017-07-21 | 2017-11-24 | 重庆大学 | A kind of garbage reclamation optimization method based on flash memory device Concurrent Feature |
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| CN108108309A (en) * | 2017-12-29 | 2018-06-01 | 苏州大学 | It is related to concurrent access method, solid state disk and the computer of more nand flash memories |
| KR102527132B1 (en) * | 2018-01-19 | 2023-05-02 | 에스케이하이닉스 주식회사 | Memory system and operating method of memory system |
| CN109104336B (en) * | 2018-09-27 | 2022-08-05 | 平安普惠企业管理有限公司 | Service request processing method and device, computer equipment and storage medium |
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