CN102569417A - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereof Download PDFInfo
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- CN102569417A CN102569417A CN201210053150XA CN201210053150A CN102569417A CN 102569417 A CN102569417 A CN 102569417A CN 201210053150X A CN201210053150X A CN 201210053150XA CN 201210053150 A CN201210053150 A CN 201210053150A CN 102569417 A CN102569417 A CN 102569417A
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Abstract
The invention relates to a thin film transistor and a manufacturing method thereof. The thin film transistor comprises a substrate, a gate, a gate insulating layer, an oxide semiconductor layer, a protective layer, a source and a drain. The gate, the gate insulating layer and the oxide semiconductor layer are arranged on the substrate in sequence. The protective layer is arranged on the oxide semiconductor layer; and the side edge of the protective layer is aligned with the side edge of the oxide semiconductor layer. The source and the drain are arranged above the protective layer. The manufacturing method of the thin film transistor comprises the following steps of: providing a substrate and forming a gate on the substrate; next, forming a gate insulating layer on the gate and forming an oxide semiconductor layer to completely cover the gate insulating layer; and then forming a protective layer to completely cover the oxide semiconductor layer; and patterning the protective layer and the oxide semiconductor layer so that the side edge of the protective layer is aligned with the oxide semiconductor layer.
Description
Technical field
The invention relates to a kind of thin-film transistor and preparation method thereof, refer to have thin-film transistor of oxide semiconductor layer and preparation method thereof in a kind of image element structure that can be used for display floater especially.
Background technology
(thin film transistor TFT) has been widely used in the active array-type two-d display panel as active member, in order to drive devices such as active display panels, active organic electroluminescent display panel thin-film transistor.Wherein, Because oxide semiconductor thin-film transistor has the high electrically uniformity of electrical characteristic and amorphous silicon film transistor of the high carrier mobility of low-temperature polysilicon film transistor, so the display unit of application oxide semiconductor thin-film transistor becomes the important directions of industry technical development gradually.
Known thin-film transistor comprises a gate, one source pole, a drain and as the monoxide semiconductor layer of transistor channels.When making thin-film transistor with existing manufacturing technology; Usually can utilize micro image etching procedure patterning oxide semiconductor layer earlier; And then form a metal level with the metal sputtering processing procedure, then with this metal level of micro image etching procedure patterning with members such as the source electrode that forms data line and thin-film transistor and drains.
Yet in this source/drain processing procedure, the oxide semiconductor layer regular meeting that is positioned at source electrode and drain below is because of the electricity slurry that touches sputter process or photoresistance liquid, the etching solution of micro image etching procedure, causes broken string or electrically makes a variation.Therefore, the damage that how in the thin-film transistor processing procedure, reduces oxide semiconductor layer is the improved problem of correlation technique person institute desire to improve electrical reliability in fact.
Summary of the invention
The object of the present invention is to provide a kind of thin-film transistor (thin film transistor, TFT) and preparation method thereof, to improve the electrical reliability of thin-film transistor.
A preferred embodiment of the present invention provides a kind of thin-film transistor, comprises a substrate, a gate, a gate insulation layer, monoxide semiconductor layer, a protective layer, one source pole and a drain.Gate, gate insulation layer and oxide semiconductor layer are arranged on the substrate in regular turn.Protective layer is arranged on the oxide semiconductor layer, and the side of the side of protective layer and oxide semiconductor layer trims.Source electrode and drain are arranged at the protective layer top.
Another preferred embodiment of the present invention provides a kind of manufacture method of thin-film transistor, and its step is following: a substrate is provided, and forms a gate on substrate.Then, form a gate insulation layer on gate, and form the comprehensive covering gate insulation layer of monoxide semiconductor layer.Subsequently, form the comprehensive capping oxide semiconductor layer of a protective layer.Patterning protective layer and oxide semiconductor layer trim the side of protective layer and the side of oxide semiconductor layer.
The present invention provides a protective layer to be arranged at the oxide semiconductor layer top; And the side of protective layer and the side of oxide semiconductor layer trim; That is to say that protective layer and oxide semiconductor layer have identical pattern, that is protective layer can overlapping fully and capping oxide semiconductor.Therefore; Protective layer of the present invention can effectively be avoided the oxide semiconductor layer of the direct contact protection layer of electricity slurry, water, oxygen, hydrogen, cleaning fluid or the etching solution etc. in the successive process or in environment below; Keeping the integrality of oxide semiconductor layer, and then promote the electrical reliability of thin-film transistor.
Description of drawings
Fig. 1 has illustrated the sketch map of the thin-film transistor of a preferred embodiment of the present invention.
Fig. 2 to Fig. 7 has illustrated the manufacture method sketch map of the thin-film transistor of a preferred embodiment of the present invention.
Among the figure: 10 thin-film transistors, 12 substrates, 14 gates, 16 gate insulation layer; 18,18 ' oxide semiconductor layer, 20,20 ' first protective layer, 22,22 ' second protective layer, 24,24 ' protective layer; 24A contacts hole, 26 source electrodes, 28 drains; 32 flat insulator layer, 34 transparent pixel electrodes, D1 spacing.
Embodiment
Know under the present invention the general art of technical field and can further understand the present invention for making, the hereinafter spy enumerates a preferred embodiment of the present invention, and cooperate appended graphic, specify constitution content of the present invention and the effect desiring to reach.
Please refer to Fig. 1.Fig. 1 has illustrated the sketch map of the thin-film transistor of a preferred embodiment of the present invention.Thin-film transistor 10 comprises a substrate 12, a gate 14, a gate insulation layer 16, monoxide semiconductor layer 18, a protective layer 24, one source pole 26 and a drain 28.Substrate 12 can comprise hard substrate for example glass substrate, quartz base plate, plastic substrate etc., or the soft substrate plate of other bendable materials.Gate 14, source electrode 26 can be for example metal of electric conducting material with the material of drain 28, comprise the combination of aluminium, molybdenum, chromium, tungsten, copper or above-mentioned metal.The material of gate insulation layer 16 can comprise for example silica, silicon nitride, silicon oxynitride or other dielectric materials.The material of oxide semiconductor layer 18 comprise indium gallium zinc oxide (In-Ga-Zn-O, IGZO), indium-zinc oxide (In-Zn-O, IZO), the mixture of zinc oxide (ZnO) or above-mentioned material.And the material of protective layer 24 comprises the mixture of Si oxide, titanium oxide, aluminum oxide or above-mentioned material.
It should be noted that protective layer 24 comprises that one first protective layer 20 and one second protective layer 22 are arranged on the oxide semiconductor layer 18 in regular turn.First protective layer 20 and second protective layer 22 is preferable is made up of same material, and a preferred thickness of first protective layer 20 is the thickness less than second protective layer 22, but not as limit.The employed operand power of processing procedure (power) that wherein forms first protective layer 20 is less than the employed operand power of processing procedure that forms second protective layer 22; The deposition velocity that can make the processing procedure that forms first protective layer 20 is in fact less than the deposition velocity of the processing procedure that forms second protective layer 22; That is to say; The one first thickness uniformity of first protective layer 20 can be in fact less than the one second thickness uniformity of second protective layer 22; Wherein the thickness uniformity is meant the upward difference of the one-tenth-value thickness 1/10 of each point of surface, that is the one-tenth-value thickness 1/10 of each point is comparatively close on the surface of first protective layer 20.In addition; First protective layer 20 has a first film density, and second protective layer 22 has one second density of film, and the first film density is greater than second density of film; That is to say that the surface molecular distribution density of first protective layer 20 is the surface molecular distribution densities greater than second protective layer 22.
Please refer to Fig. 2 to Fig. 7.Fig. 2 to Fig. 7 has illustrated the manufacture method sketch map of the thin-film transistor of a preferred embodiment of the present invention.Present embodiment is an example with the thin-film transistor in the image element structure that forms display floater.As shown in Figure 2, a substrate 12 is provided, and forms a gate 14 on substrate 12.Substrate 12 can comprise hard substrate for example glass substrate, quartz base plate, plastic substrate etc., or the soft substrate plate of other bendable materials.The method that forms gate 14 can comprise the following step: at first, on substrate 12, form a first metal layer (figure does not show), then this first metal layer of patterning is to form a plurality of gate lines (figure does not show) and at least one gate 14.Subsequently, form gate insulation layer 16 on gate 14, and form monoxide semiconductor layer 18 ' the comprehensive covering gate insulation layer 16.The material of oxide semiconductor layer 18 ' comprise indium gallium zinc oxide (In-Ga-Zn-O, IGZO), indium-zinc oxide (In-Zn-O, IZO), the mixture of zinc oxide (ZnO) or above-mentioned material.
Afterwards, as shown in Figure 3, form a protective layer 24 ' the comprehensive capping oxide semiconductor layer 18 '.The method that forms protective layer 24 ' comprises the segmented deposition manufacture process, and its step comprises: carry out one first deposition manufacture process, form one first protective layer, 20 ' the comprehensive capping oxide semiconductor layer 18 '; And carry out one second deposition manufacture process, form one second protective layer, 22 ' comprehensive covering first protective layer 20 '.Wherein first protective layer 20 ' has a first film density, and second protective layer 22 ' has one second density of film.The material of first protective layer 20 ' and second protective layer 22 ' comprises the mixture of Si oxide, titanium oxide, aluminum oxide or above-mentioned material.Wherein first deposition manufacture process has one first operand power (power), and second deposition manufacture process has one second operand power, and first operand power is less than second operand power.In addition; First deposition manufacture process and second deposition manufacture process all can comprise a chemical vapour deposition (CVD) (chemical vapor deposition; CVD) processing procedure; For example plasma enhanced chemical vapor deposition (PECVD) processing procedure or physical vapour deposition (PVD) processing procedure (physical vapor deposition, PVD), sputter (sputter) processing procedure for example.In the present embodiment; Forming protective layer 24 ' with the physical vapour deposition (PVD) processing procedure is example; Employed first operand power employed second operand power when carrying out second deposition manufacture process that is to say that the gas molecule dissociation yield of first deposition manufacture process can be less than the gas molecule dissociation yield of second deposition manufacture process when carrying out first deposition manufacture process; Therefore; First deposition rate will be in fact less than second deposition rate, and the thickness uniformity on surface that makes first protective layer 20 ' is in fact less than the thickness uniformity on the surface of second protective layer 22 ', and wherein the thickness uniformity is meant that the surface goes up the difference of the one-tenth-value thickness 1/10 of each point.And under the situation of first deposition rate less than second deposition rate, the first film density is in fact greater than second density of film, that is the surface molecular distribution density of first protective layer 20 ' is in fact greater than the surface molecular distribution density of second protective layer 22 '.Deposition rate also can be adjusted by changing predecessor kind, predecessor flow velocity or concentration, reaction chamber pressure, reaction chamber temperature or electricity slurry operating condition etc.
It should be noted that; Owing to forming first protective layer 20 ' before; The surface of oxide semiconductor layer 18 ' is directly to be exposed in the environment, for avoiding that oxide semiconductor layer 18 ' is caused direct damage, so the present invention's first deposition manufacture process physical vapour deposition (PVD) processing procedure that for example operand power is lower to have first operand power earlier; Form first protective layer, 20 ' complete capping oxide semiconductor layer 18 ', to guarantee the integrality of oxide semiconductor layer 18 '.In addition, still must meet considering of production capacity, therefore be formed on the oxide semiconductor layer 18 ' at first protective layer 20 '; That is to say; After oxide semiconductor layer 18 ' directly is not exposed in the environment, can further adopt have second operand power second deposition manufacture process for example the higher physical vapour deposition (PVD) processing procedure of operand power form second protective layer 22 ' and cover first protective layer 20 ' fully to increase deposition rate; Save to form the required sedimentation time of protective layer 24 ' with predetermined altitude; That is to say that keeping the production of protective layer 24 ', and reduction generates the time that protective layer 24 ' consumed.In addition, the step that forms oxide semiconductor layer 18 ' can be carried out in same reaction chamber with the step that forms protective layer 24 ', also helps reducing the processing procedure time.
Then; As shown in Figure 4; Carry out a micro image etching procedure with patterning protective layer 24 ' and oxide semiconductor layer 18 ', its step comprises: form a patterning mask layer (figure do not show) on protective layer 24 ', and the patterning mask layer protective layer 24 ' of overlapping; Remove and be not patterned protective layer 24 ' and the oxide semiconductor layer 18 ' that mask layer covers; And removal patterning mask layer.This processing procedure can make the side of protective layer 24 and the side of oxide semiconductor layer 18 trim.It should be noted that when etch process carries out that protective layer 24 can effectively be avoided the oxide semiconductor layer 18 of direct contact protection layer 24 below such as cleaning fluid or etching solution in the processing procedure, reduces the damage of oxide semiconductor layer 18.In addition, protective layer 24 and oxide semiconductor layer 18 can be with the light shields with identical patterns, that is same patterning mask layer; Carry out the definition of position and shape, for example: in the present embodiment, the width of the width of defined protective layer 24 and defined oxide semiconductor layer 18 all is equal to the width of gate 14 in fact; But not as limit; Therefore, after etch process was accomplished, remaining protective layer 24 still can be overlapping fully and be covered remaining oxide semiconductor layer 18; Avoid oxide semiconductor layer 18 directly to be exposed in the environment, to keep the character of oxide semiconductor layer 18.
As shown in Figure 5; Subsequently; Carry out a micro image etching procedure again to form at least two contact hole 24A in protective layer 24; Contact hole 24A is used for part exposed oxide semiconductor layer 18, makes oxide semiconductor layer 18 can see through contact hole 24A and is connected with drain (figure does not show) with the source electrode (figure does not show) of follow-up formation.In addition, patterning oxide semiconductor layer 18 ' is reached with the step same halftoning light shield also capable of using (half-tone mask) that formation contacts hole 24A with the step of protective layer 24 ', uses number to reduce light shield.In more detail; The halftoning light shield comprises a transparency carrier and is located at one on the transparency carrier and covers pattern and at least two half and pass through zone (half-tone region); Wherein covering pattern is the pattern that is used to define remaining oxide semiconductor layer 18 and remaining protective layer 24, and a plurality of zone of partly passing through is the pattern that is used to define the contact hole.Its step comprises: on protective layer 24 ', the material of photoresist layer comprises photoresist to form a photoresist layer (figure does not show); Use the halftoning light shield to carry out the exposure imaging step as the cover curtain, with the design transfer of halftoning light shield to photoresist layer, form one first patterning mask layer (figure does not show) on protective layer 24 '; Remove the protective layer 24 ' and the oxide semiconductor layer 18 ' that are not covered, and form the precalculated position that one second patterning mask layer is used to expose contact hole 24A by the first patterning mask layer; Remove the protective layer 24 ' that is not covered, to form contact hole 24A in protective layer 24 by the second patterning mask layer; Remove the second patterning mask layer at last.Wherein, Form the method for the second patterning mask layer; Comprise the dry ecthing procedure or the wet etching processing procedure that are carried out when removing not the protective layer 24 ' that covered by the first patterning mask layer and oxide semiconductor layer 18 '; Remove the thin part of the first patterning mask layer simultaneously, just contact the precalculated position of hole 24A, to form the second patterning mask layer.In addition, also can extraly carry out a cineration step and remove the thin part of the first patterning mask layer, to form the second patterning mask layer.Be arranged in protective layer 24 formed a plurality of contacts hole 24A of same gate 14 tops, spacings of the space D 1 of these contacts hole 24A or the oxide semiconductor layer 18 that exposed by contact hole 24A are equal to the length of channel region of the thin-film transistor of follow-up formation in fact.
Form contact hole 24A in protective layer 24 after; As shown in Figure 6; Form one second metal level (figure does not show) on protective layer 24; And patterning second metal level is to form a plurality of data lines (figure does not show), at least one source electrode 26 and at least one drain 28, and wherein source electrode 26 contacts with oxide semiconductor layer 18 via the hole 24A that respectively contacts in the protective layer 24 respectively with drain 28.So far, accomplished thin-film transistor 10 of the present invention.
For thin-film transistor 10 of the present invention also is applicable in the image element structure of display floater.Subsequently, as shown in Figure 7, can further form a flat insulator layer 32 in source electrode 26 and drain 28 tops, the material of flat insulator layer 32 for example can be organic transparent insulation material: resin; Remove part flat insulator layer 32 afterwards, the method for removal comprises carries out a dry ecthing procedure, makes flat insulator layer 32 have at least one contact hole 32A, and the contact hole 32A of flat insulator layer 32 at least partly exposes drain 28; And on flat insulator layer 32, form a transparent electrode layer (figure does not show); Its material can be transparent conductive material for example indium tin oxide (ITO) or indium-zinc oxide (IZO) etc.; And the patterned transparent electrode layer is to form transparent pixel electrode 34; Wherein, transparent pixel electrode 34 electrically connects via the contact hole 32A and the drain 28 of flat insulator layer 32.
In sum; The present invention provides a protective layer to be arranged at the oxide semiconductor layer top, and wherein the side of the side of protective layer and oxide semiconductor layer trims, and that is to say; Protective layer has identical pattern with oxide semiconductor layer; That is when patterning protective layer and oxide semiconductor, protective layer can overlapping fully and capping oxide semiconductor.In addition; Protective layer of the present invention is to form via the segmented deposition manufacture process, comprises first deposition manufacture process of implementing to have low operand power earlier, forms the complete capping oxide semiconductor layer of first protective layer; Provide oxide semiconductor layer tentatively to protect effect with first protective layer; Second deposition manufacture process of implementing to have higher operand power again forms second protective layer, to keep the production of protective layer, avoids the processing procedure overlong time.Therefore; Protective layer of the present invention and segmented protective layer deposition manufacture process can effectively be avoided the oxide semiconductor layer of the direct contact protection layer of electricity slurry, water, oxygen, hydrogen, cleaning fluid or the etching solution etc. in the processing procedure or in environment below; Keeping the integrality of oxide semiconductor layer, and then promote the electrical reliability of thin-film transistor.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. a thin-film transistor is characterized in that, comprising:
One substrate;
One gate is arranged on this substrate;
One gate insulation layer is arranged on this gate;
The monoxide semiconductor layer is arranged on this gate insulation layer;
One protective layer comprise that one first protective layer and one second protective layer are arranged on this oxide semiconductor layer in regular turn, and the side of the side of this protective layer and this oxide semiconductor layer trims; And
An one source pole and a drain are arranged at this protective layer top.
2. thin-film transistor according to claim 1 is characterized in that: the material of this oxide semiconductor layer comprises the mixture of indium gallium zinc oxide, indium-zinc oxide, zinc oxide or above-mentioned material.
3. thin-film transistor according to claim 1 is characterized in that: this first protective layer has a first film density, and this second protective layer has one second density of film, and this first film density is greater than this second density of film.
4. thin-film transistor according to claim 1 is characterized in that: this protective layer has at least two contact holes, and this source electrode contacted with this oxide semiconductor layer via respectively contacting the hole respectively with this drain.
5. thin-film transistor according to claim 1 is characterized in that: the area of this gate is more than or equal to the area of this oxide semiconductor layer, to cover this oxide semiconductor layer.
6. the manufacture method of a thin-film transistor is characterized in that, comprises the following steps:
One substrate is provided;
Form a gate on this substrate;
Form a gate insulation layer on this gate;
Form this gate insulation layer of the comprehensive covering of monoxide semiconductor layer;
Form this oxide semiconductor layer of the comprehensive covering of a protective layer, the step that wherein forms this protective layer comprises:
Carry out one first deposition manufacture process, form this oxide semiconductor layer of the comprehensive covering of one first protective layer; And
Carry out one second deposition manufacture process, form this first protective layer of the comprehensive covering of one second protective layer; And
This protective layer of patterning and this oxide semiconductor layer trim the side of this protective layer and the side of this oxide semiconductor layer.
7. the manufacture method of thin-film transistor according to claim 6, it is characterized in that: this first deposition manufacture process has one first operand power, and this second deposition manufacture process has one second operand power, and this first operand power is less than this second operand power.
8. the manufacture method of thin-film transistor according to claim 6, it is characterized in that: the material that forms this oxide semiconductor layer comprises the mixture of indium gallium zinc oxide, indium-zinc oxide, zinc oxide or above-mentioned material.
9. the manufacture method of thin-film transistor according to claim 6, it is characterized in that: the step of this oxide semiconductor layer of patterning and this protective layer comprises:
Form a patterning mask layer on this protective layer, and this patterning mask layer this protective layer of overlapping;
Remove this protective layer and this oxide semiconductor layer that are not covered by this patterning mask layer; And
Remove this patterning mask layer.
10. the manufacture method of thin-film transistor according to claim 6; It is characterized in that: after the step of this protective layer of patterning and this oxide semiconductor layer; Other comprises formation at least two contact holes in this protective layer, exposes this oxide semiconductor layer with part.
11. the manufacture method of thin-film transistor according to claim 10 is characterized in that: after the step that forms these contact holes, other comprises:
Form a metal level on this protective layer; And
This metal level of patterning is characterized in that to form an one source pole and a drain: this source electrode contacted with this oxide semiconductor layer via respectively contacting the hole respectively with this drain.
12. the manufacture method of thin-film transistor according to claim 6 is characterized in that: the step that forms this oxide semiconductor layer can be carried out in same reaction chamber with the step that forms this protective layer.
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| CN103681487A (en) * | 2013-12-13 | 2014-03-26 | 华映视讯（吴江）有限公司 | Thin film transistor substrate and manufacturing method thereof |
| WO2014047980A1 (en) * | 2012-09-26 | 2014-04-03 | 深圳市华星光电技术有限公司 | Method for manufacturing thin-film transistor active device and thin-film transistor active device manufactured thereby |
| CN106098617A (en) * | 2016-08-01 | 2016-11-09 | 信利（惠州）智能显示有限公司 | A kind of wide viewing angle pattern TFT substrate preparation method |
| WO2018120570A1 (en) * | 2016-12-30 | 2018-07-05 | 惠科股份有限公司 | Manufacturing process for display panel |
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| CN101416320A (en) * | 2006-01-31 | 2009-04-22 | 出光兴产株式会社 | TFT substrate, reflective TFT substrate, and manufacturing method thereof |
| CN101901839A (en) * | 2009-05-29 | 2010-12-01 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
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| CN101416320A (en) * | 2006-01-31 | 2009-04-22 | 出光兴产株式会社 | TFT substrate, reflective TFT substrate, and manufacturing method thereof |
| CN101901839A (en) * | 2009-05-29 | 2010-12-01 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014047980A1 (en) * | 2012-09-26 | 2014-04-03 | 深圳市华星光电技术有限公司 | Method for manufacturing thin-film transistor active device and thin-film transistor active device manufactured thereby |
| CN103681487A (en) * | 2013-12-13 | 2014-03-26 | 华映视讯（吴江）有限公司 | Thin film transistor substrate and manufacturing method thereof |
| CN106098617A (en) * | 2016-08-01 | 2016-11-09 | 信利（惠州）智能显示有限公司 | A kind of wide viewing angle pattern TFT substrate preparation method |
| WO2018120570A1 (en) * | 2016-12-30 | 2018-07-05 | 惠科股份有限公司 | Manufacturing process for display panel |
| US10816864B2 (en) | 2016-12-30 | 2020-10-27 | HKC Corporation Limited | Method of manufacturing a display panel and avoiding peeling layers |
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Application publication date: 20120711 |