CN102569254A - Semiconductor structure and production method thereof - Google Patents
Semiconductor structure and production method thereof Download PDFInfo
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- CN102569254A CN102569254A CN2010106017243A CN201010601724A CN102569254A CN 102569254 A CN102569254 A CN 102569254A CN 2010106017243 A CN2010106017243 A CN 2010106017243A CN 201010601724 A CN201010601724 A CN 201010601724A CN 102569254 A CN102569254 A CN 102569254A
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Abstract
The invention discloses a semiconductor structure and a production method thereof. The semiconductor structure comprises a semiconductor substrate, an isolation layer, a first metal layer and a second metal layer. The semiconductor substrate comprises a substrate upper surface and a semiconductor element. The semiconductor element is arranged below the substrate upper surface. The isolation layer is provided with a first side and a second side which are opposite to each other. The first metal layer is arranged on the substrate upper surface. The first metal layer and the second metal layer are respectively arranged on the first side and the second side. The lower surface of the second metal layer is arranged below the substrate upper surface.
Description
Technical field
The present invention relates to semiconductor structure and manufacturing approach thereof, particularly relate to semiconductor structure and manufacturing approach thereof with contact hole.
Background technology
Along with development of integrated circuits; From large-scale integrated circuit (large scale integration), ultra-large type integrated circuit (very large scale integration), further to very big type integrated circuit (ultra large scale integration); The semiconductor element size is all significantly dwindled, to cooperate the integrated circuit area of reduction day by day.The lifting of integrated level is that semiconductor fabrication process is brought many challenges.
Along with the trend of microization, the developing direction of technology mainly is to concentrate on to use shallow junction (shallow) manufacture craft to avoid the problem of collapse (breakdown)/electric leakage (leakage).Therefore general contact hole is designed with identical height, and its degree of depth can not surpass the semiconductor-based end.Therefore contact hole and through separator and the path between the contact hole semiconductor element of being separated by be long.This path can produce big voltage drop to the voltage of bestowing through contact hole, causes RC to postpone and the slack-off problem of semiconductor element service speed.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor structure and manufacturing approach thereof.Contact hole in the semiconductor structure (contact) is formed by the low-down metal of resistance; And contact hole extends to the below of the upper surface of substrate at the semiconductor-based end from the separator of top, the semiconductor-based end; Therefore the distance between contact hole and the semiconductor element is little; And when voltage is sent to semiconductor element via contact hole, between the voltage drop that produces also little.This can help to reduce the service speed that RC postpones and promote semiconductor element.
According to the object of the invention, a kind of semiconductor structure is proposed.Semiconductor structure comprises semiconductor substrate, a separator, a first metal layer and one second metal level.The semiconductor-based end, comprise a upper surface of substrate and semiconductor element.Semiconductor element is under upper surface of substrate.Separator has a relative first side and a second side.The first metal layer is arranged on the upper surface of substrate.The first metal layer and second metal level are respectively on first side and second side.The lower surface of second metal level is below upper surface of substrate.
According to the object of the invention, a kind of manufacturing approach of semiconductor structure is proposed also.Manufacturing approach may further comprise the steps.The semiconductor substrate is provided.The semiconductor-based end, comprise a upper surface of substrate.In the semiconductor-based end, forming a shallow trench isolation leaves.In the semiconductor-based end, form semiconductor element.Semiconductor element is under upper surface of substrate., shallow trench isolation forms an interlayer dielectric layer on leaving.Shallow trench isolation is from forming a separator with interlayer dielectric layer.Separator has a relative first side and a second side.On upper surface of substrate, form a first metal layer.And, form one second metal level.The first metal layer and second metal level are respectively on first side and second side.The lower surface of second metal level is below upper surface of substrate.
For letting above-mentioned purpose of the present invention, characteristic and the advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended accompanying drawing, elaborates as follows:
Description of drawings
Fig. 1 illustrates the semiconductor structure of first embodiment of the invention;
Fig. 2 to Fig. 8 illustrates the manufacture craft of the semiconductor structure of first embodiment as shown in Figure 1;
Fig. 9 illustrates the semiconductor structure of second embodiment of the invention;
Figure 10 illustrates the semiconductor structure of third embodiment of the invention;
Figure 11 to Figure 18 illustrates the manufacture craft of the semiconductor structure of the 3rd embodiment shown in figure 10;
Figure 19 illustrates a step of the semiconductor structure manufacture craft of the 4th embodiment;
Figure 20 illustrates the semiconductor structure of fourth embodiment of the invention;
Figure 21 illustrates the semiconductor structure of fifth embodiment of the invention;
Figure 22 illustrates the semiconductor structure of sixth embodiment of the invention.
The main element symbol description
2,50,60,94,102,122: semiconductor structure
3,66: the semiconductor-based end
4,56,68,114: semiconductor layer
8: separator
10,16,51,75,86,104,124: semiconductor element
12: the first metal layer
14,57: the second metal levels
14a, 82: the first metal section and parts
14b, 84: the second metal section and parts
18,64,67,77: shallow trench isolation leaves
20,65,88: interlayer dielectric layer
22,24,52,53,54,62,70,72,106,108,110,126,128,130,134: semiconductor portions
26, the lower surface of 58: the second metal levels
28,59: upper surface of substrate
30,76: metal silicified layer
32,79: the lower surface that shallow trench isolation leaves
The 3rd side of 34: the first metal section and parts
The four side of 36: the first metal section and parts
The 5th side of 38: the second metal section and parts
The 6th side of 40: the second metal section and parts
41: the first side of separator
43: the second side of separator
44,45,46,74,78,82,90: opening
63,92: etching stopping layer
D11, D41: first distance
D21, D42: second distance
D31: the 3rd distance
D32: the 4th distance
Embodiment
First embodiment
Fig. 1 illustrates the semiconductor structure of first embodiment of the invention.Please with reference to Fig. 1, semiconductor structure 2 comprises the for example semiconductor-based end 3, separator 8, the first metal layer 12, second metal level 14 and semiconductor element 16.The semiconductor-based end 3, can comprise the for example silicon materials of polysilicon.The semiconductor-based end 3, have a upper surface of substrate 28.The semiconductor-based end 3, comprise for example semiconductor layer 4 and semiconductor element 10.
Please with reference to Fig. 1, separator 8 for example comprise shallow trench isolation from 18 with interlayer dielectric layer 20.Shallow trench isolation can be dual shallow trench isolation (dual STI) from 18.Separator 8 has a relative first side 41 and a second side 43.The first metal layer 12 and second metal level 14 are separately positioned on a first side 41 and the second side 43.Second metal level 14 comprises the for example first metal section and part 14a and the second metal section and part 14b.The second metal section and part 14b is arranged on the first metal section and part 14a.The first metal layer 12 and second metal level 14 comprise for example tungsten.Semiconductor structure 2 also can comprise metal silicified layer 30, is arranged between the semiconductor-based end 3 and the first metal layer 12, or is arranged between the semiconductor-based end 3 and second metal level 14.In certain embodiments, metal silicified layer 30 can be set.
Please with reference to Fig. 1, in second metal level 14, the 3rd side 34 that the first metal section and part 14a is relative and first distance B 11 between the four side 36 can be less than relative the 5th side 38 of the second metal section and part 14b and the second distance D21 between the 6th side 40.The 3rd side 34 and the 5th side 38 can be and align, and be as shown in Figure 1.The lower surface 26 of second metal level 14 can be positioned at the below of upper surface of substrate 28.In an embodiment, the 3rd distance B 31 between the lower surface 26 of the upper surface of substrate 28 and second metal level 14 can be greater than 1000 dusts.Upper surface of substrate 28 and shallow trench isolation can be 500 dust to 4000 dusts from the 4th distance B 41 between 18 the lower surface 32.The 3rd distance B 31 cuts the 4th distance B 41 can equal-1500 dust to 3000 dusts.
Please with reference to Fig. 1, in this embodiment, semiconductor element 10 is diodes, and can comprise the semiconductor portions 22 and semiconductor portions 24 of different conductivity types.In one embodiment, for instance, semiconductor portions 22 has the N conductivity type, and semiconductor portions 24 has the P+ conductivity type, and semiconductor layer 4 has the P-conductivity type.Semiconductor element 16 can comprise memory for example Ovonics unified memory (PCM), resistive ram (RRAM), nonvolatile memory (NVM) or the like.Because the lower surface 26 of second metal level 14 that resistance is very little is positioned at the below of upper surface of substrate 28, in other words, second metal level 14 is close with semiconductor element 10, and the resistance therefore is little.Therefore, the external electric pressure energy efficiently through second metal level 14 be sent to semiconductor element 10 for example diode and promote service speed driving semiconductor element 16.
Fig. 2 to Fig. 8 illustrates the manufacture craft of the semiconductor structure 2 of first embodiment as shown in Figure 1.Please, on the semiconductor-based end 3, form shallow trench isolation from 18 with reference to Fig. 2.Please, form semiconductor layer 4 and semiconductor portions 22 at the semiconductor-based end 3 to inject doping mode with reference to Fig. 3.Please, form semiconductor portions 24 to inject the semiconductor-based end 3 of doping mode on semiconductor portions 22 with reference to Fig. 4.Please, on 18, form interlayer dielectric layer 20, and in interlayer dielectric layer 20, form opening 44 and opening 45 at shallow trench isolation with reference to Fig. 5.
Then, remove semiconductor portions 24 that opening 45 exposes and semiconductor portions 22 to form opening as shown in Figure 6 46.Please, utilize autoregistration metal silication method, form metal silicified layer 30 on the surface at the semiconductor-based end 3 that opening 44 and opening 46 expose with reference to Fig. 7.In certain embodiments, the formation step of metal silicified layer 30 is omitted.Please, then, in opening 44, form the first metal layer 12, and in opening 46, form second metal level 14 with reference to Fig. 8.Then, on the first metal layer 12, form semiconductor element 16 to form semiconductor structure as shown in Figure 12.
Second embodiment
Fig. 9 illustrates the semiconductor structure of second embodiment of the invention.The semiconductor structure of Fig. 9 and Fig. 1 different be in, the semiconductor element 51 of semiconductor structure 50 is bipolar junction transistors, and can comprise semiconductor portions 52, semiconductor portions 53 and semiconductor portions 54.In one embodiment, for instance, semiconductor portions 52, semiconductor portions 54 have the N conductivity type, and semiconductor portions 53 has the P+ conductivity type, and semiconductor layer 56 has the P-conductivity type.
Please with reference to Fig. 9; Because the lower surface 58 of second metal level 57 that resistance is very little is below upper surface of substrate 59; In other words, second metal level 57 is close with semiconductor element 51, and the resistance therefore is little; That is the voltage drop between second metal level 57 and the semiconductor element 51 can be little.Therefore, the external electric pressure energy is sent to the for example bipolar junction transistor of semiconductor element 51 with driving semiconductor element 75 through second metal level 57 efficiently, and promotes service speed.
In an embodiment, the 3rd distance B 32 between the lower surface 58 of the upper surface of substrate 59 and second metal level 57 can be greater than 1000 dusts.Upper surface of substrate 59 and shallow trench isolation can be 500 dust to 4000 dusts from the 4th distance B 42 between 77 the lower surface 79.The 3rd distance B 32 cuts the 4th distance B 42 can equal-1500 dust to 3000 dusts.
The 3rd embodiment
Figure 10 illustrates the semiconductor structure of third embodiment of the invention.The semiconductor structure of Figure 10 and Fig. 1 different be in, semiconductor structure 60 has semiconductor portions 62.Semiconductor portions 62 is below second metal level 84.In one embodiment, for instance, semiconductor portions 62 is the N conductivity type with semiconductor portions 70, and the doping content of semiconductor portions 62 (N+) is the doping content (N) greater than semiconductor portions 70.In addition, semiconductor structure 60 also has etching stopping layer 63, be arranged at shallow trench isolation from 64 and interlayer dielectric layer 65 between.Etching stopping layer 63 can comprise silicon nitride or silicon oxynitride.
Figure 11 to Figure 18 illustrates the manufacture craft of the semiconductor structure 60 of the 3rd embodiment shown in figure 10.Please, on the semiconductor-based end 66, form shallow trench isolation from 67 with reference to Figure 11.Please, form semiconductor layer 68 and semiconductor portions 70 at the semiconductor-based end 66 to inject doping mode with reference to Figure 12.Please, form semiconductor portions 72 to inject the semiconductor-based end 66 of doping mode on semiconductor portions 70 with reference to Figure 13.Please, remove part semiconductor substrate 66, and form semiconductor portions 62 at the semiconductor-based ends 66 that opening 74 exposes to inject doping mode with formation opening 74 with reference to Figure 14.Please with reference to Figure 15, expose at the semiconductor-based end 66 the surface form metal silicified layer 76.Please, on 67, form etching stopping layer 63 with shallow trench isolation at the semiconductor-based end 66 with reference to Figure 16.Please, on etching stopping layer 63, form interlayer dielectric layer 65 with reference to Figure 17.
Please with reference to Figure 18, the interlayer dielectric layer 65 that removes part removes the etching stopping layer 63 that opening 78 and opening 80 expose then to form opening 78 and opening 80.In the step that removes interlayer dielectric layer 65, etching stopping layer 63 can avoid the material of its below to be damaged.In an embodiment, be to remove etching stopping layer 63 to etching method, and etching stopping layer 63 is the etching speed greater than the level direction in the etching speed of vertical direction with non-grade.Therefore, after etching step, be positioned at shallow trench isolation in the opening 78 and can be retained from the etching stopping layer 63 on 67 sidewalls.Then, respectively at the formation the first metal layer 82 and second metal level 84 in opening 80 and the opening 78, and on the first metal layer 82, form semiconductor element 86, to accomplish semiconductor structure shown in figure 10 60.
The 4th embodiment
The manufacture of the semiconductor structure of the 4th embodiment is similar haply with the 3rd embodiment.Wherein, therefore in interlayer dielectric layer, form the bigger error of step tolerable of opening, product is not had the defective that has a strong impact on and can not produce because semiconductor structure has etching stopping layer.Please with reference to Figure 19, in certain embodiments, for instance, the etching process error that removes interlayer dielectric layer 88 causes the offset of opening 90.Etching stopping layer 92 can protect the material of its below not to be etched damage.Therefore can form semiconductor structure shown in figure 20 94 at last.
The 5th embodiment
Figure 21 illustrates the semiconductor structure of fifth embodiment of the invention.The semiconductor structure of Figure 21 and Figure 10 different be in, the semiconductor element 104 of semiconductor structure 102 is bipolar junction transistors, and can comprise semiconductor portions 106, semiconductor portions 108 and semiconductor portions 110.In one embodiment, for instance, semiconductor portions 106 has the N conductivity type with semiconductor portions 110, and semiconductor portions 108 has the P+ conductivity type, and semiconductor layer 114 has the P-conductivity type.
The 6th embodiment
Figure 22 illustrates the semiconductor structure of sixth embodiment of the invention.The semiconductor structure of Figure 22 and Figure 20 different be in, the semiconductor element 124 of semiconductor structure 122 is bipolar junction transistors, and can comprise semiconductor portions 126, semiconductor portions 128 and semiconductor portions 130.In one embodiment, for instance, semiconductor portions 126 has the N conductivity type with semiconductor portions 130, and semiconductor portions 128 has the P+ conductivity type, and semiconductor layer 134 has the P-conductivity type.
Above-mentioned semiconductor element can be according to circumstances modulation suitably.For instance, diode can be PN or NP diode.Bipolar junction transistor can be PNP or the bipolar junction transistor of NPN.Second metal level also can be used with thin-film transistor (TFT) collocation.
In an embodiment of the present invention, contact hole is to be formed by the second very little metal level of resistance, and the lower surface of second metal level is positioned at the below of the upper surface of substrate at the semiconductor-based end.Therefore, can produce little voltage drop between second metal level and the semiconductor element,, and promote service speed so the voltage of input can be efficiently is sent to diode or bipolar junction transistor driving memory from second metal.In the process of making semiconductor structure, can before forming interlayer dielectric layer, form etching stopping layer.Etching stopping layer can avoid the material of its below to be damaged.Therefore in interlayer dielectric layer, form the bigger error of step tolerable of opening, and can bad influence not arranged product.
Though disclosed the present invention in conjunction with above preferred embodiment, yet it is not in order to limiting the present invention, anyly be familiar with this operator, do not breaking away from the spirit and scope of the present invention, can do a little change and retouching.Therefore protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (10)
1. semiconductor structure comprises:
The semiconductor-based end, comprise upper surface of substrate and semiconductor element, and this semiconductor element is under this upper surface of substrate;
Separator has a relative first side and a second side;
The first metal layer is arranged on this upper surface of substrate; And
Second metal level, on this first side and this second side, the lower surface of this second metal level is below this upper surface of substrate respectively for this first metal layer and this second metal level.
2. semiconductor structure as claimed in claim 1; Wherein this second metal level comprises first metal section and part and second metal section and part; This second metal section and part is on this first metal section and part; This first metal section and part has relative one the 3rd side and a four side, and this second metal section and part has one the 5th relative side and one the 6th side, and the distance of one first between the 3rd side and this four side is less than the second distance between the 5th side and the 6th side.
3. semiconductor structure as claimed in claim 1, wherein the 3rd side aligns with the 5th side.
4. semiconductor structure as claimed in claim 1; Wherein, This separator comprises that shallow trench isolation leaves and interlayer dielectric layer, and this interlayer dielectric layer is arranged at this shallow trench isolation from last, and the distance of one the 3rd between the lower surface of this upper surface of substrate and this second metal level is greater than 1000 dusts; Between the lower surface that this upper surface of substrate and shallow trench isolation leave one the 4th distance is 500 dust to 4000 dusts, and the 3rd distance cuts the 4th distance and equals-1500 dust to 3000 dusts.
5. semiconductor structure as claimed in claim 1 also comprises a metal silicified layer, is arranged between this semiconductor-based end and this first metal layer, or is arranged between this semiconductor-based end and this second metal level.
6. semiconductor structure as claimed in claim 1, wherein this separator comprises that shallow trench isolation leaves and interlayer dielectric layer, this semiconductor structure also comprises etching stopping layer, be provided with this shallow trench isolation from and this interlayer dielectric layer between.
7. the manufacturing approach of a semiconductor structure comprises:
The semiconductor substrate is provided, and this semiconductor-based end, comprise a upper surface of substrate;
In this semiconductor-based end, forming a shallow trench isolation leaves;
In this semiconductor-based end, form semiconductor element, this semiconductor element is under this upper surface of substrate;
Leave formation one interlayer dielectric layer at this shallow trench isolation, this shallow trench isolation is from forming a separator with this interlayer dielectric layer, and this separator has a relative first side and a second side;
On this upper surface of substrate, form a first metal layer; And
Form one second metal level, on this first side and this second side, the lower surface of this second metal level is below this upper surface of substrate respectively for this first metal layer and this second metal level.
8. the manufacturing approach of semiconductor structure as claimed in claim 7; Wherein this second metal level comprises first metal section and part and second metal section and part; This second metal section and part is on this first metal section and part; This first metal section and part has relative one the 3rd side and a four side, and this second metal section and part has one the 5th relative side and one the 6th side, and the distance of one first between the 3rd side and this four side is less than the second distance between the 5th side and the 6th side.
9. the manufacturing approach of semiconductor structure as claimed in claim 7; Wherein the distance of one the 3rd between the lower surface of this upper surface of substrate and this second metal level is greater than 1000 dusts; Between the lower surface that this upper surface of substrate and shallow trench isolation leave one the 4th distance is 500 dust to 4000 dusts, and the 3rd distance cuts the 4th distance and equals-1500 dust to 3000 dusts.
10. the manufacturing approach of semiconductor structure as claimed in claim 7 also comprises:
Before this shallow trench isolation leaves this interlayer dielectric layer of formation, form an etching stopping layer and leave last in this semiconductor-based end and this shallow trench isolation;
After this shallow trench isolation leaves this interlayer dielectric layer of formation, remove this interlayer dielectric layer of a part in this interlayer dielectric layer, to form an opening; And
Remove this etching stopping layer that this opening exposes.
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| CN2010106017243A CN102569254A (en) | 2010-12-22 | 2010-12-22 | Semiconductor structure and production method thereof |
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| CN2010106017243A CN102569254A (en) | 2010-12-22 | 2010-12-22 | Semiconductor structure and production method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549329A (en) * | 2003-05-23 | 2004-11-24 | 南亚科技股份有限公司 | Method for producing bit line contact window plug with mosaic structure |
| CN101369552A (en) * | 2007-08-16 | 2009-02-18 | 联华电子股份有限公司 | Protection method for shallow plough groove isolation structure and protection layer using the same |
| CN101452889A (en) * | 2007-12-03 | 2009-06-10 | 力晶半导体股份有限公司 | Manufacturing method for non-volatile memory |
| CN102468267A (en) * | 2010-10-28 | 2012-05-23 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
-
2010
- 2010-12-22 CN CN2010106017243A patent/CN102569254A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549329A (en) * | 2003-05-23 | 2004-11-24 | 南亚科技股份有限公司 | Method for producing bit line contact window plug with mosaic structure |
| CN101369552A (en) * | 2007-08-16 | 2009-02-18 | 联华电子股份有限公司 | Protection method for shallow plough groove isolation structure and protection layer using the same |
| CN101452889A (en) * | 2007-12-03 | 2009-06-10 | 力晶半导体股份有限公司 | Manufacturing method for non-volatile memory |
| CN102468267A (en) * | 2010-10-28 | 2012-05-23 | 旺宏电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20120711 |